1 #ifndef __POWERNV_PCI_H
2 #define __POWERNV_PCI_H
12 /* Precise PHB model for error management */
14 PNV_PHB_MODEL_UNKNOWN
,
20 #define PNV_PCI_DIAG_BUF_SIZE 8192
21 #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
22 #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
23 #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
24 #define PNV_IODA_PE_MASTER (1 << 3) /* Master PE in compound case */
25 #define PNV_IODA_PE_SLAVE (1 << 4) /* Slave PE in compound case */
26 #define PNV_IODA_PE_VF (1 << 5) /* PE for one VF */
27 #define PNV_IODA_PE_PEER (1 << 6) /* PE has peers */
29 /* Data associated with a PE, including IOMMU tracking etc.. */
35 #define PNV_IODA_MAX_PEER_PES 8
36 struct pnv_ioda_pe
*peers
[PNV_IODA_MAX_PEER_PES
];
38 /* A PE can be associated with a single device or an
39 * entire bus (& children). In the former case, pdev
40 * is populated, in the later case, pbus is.
43 struct pci_dev
*parent_dev
;
48 /* Effective RID (device RID for a device PE and base bus
49 * RID with devfn 0 for a bus PE)
54 unsigned int pe_number
;
56 /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
57 struct iommu_table_group table_group
;
59 /* 64-bit TCE bypass region */
60 bool tce_bypass_enabled
;
61 uint64_t tce_bypass_base
;
63 /* MSIs. MVE index is identical for for 32 and 64 bit MSI
64 * and -1 if not supported. (It's actually identical to the
69 /* PEs in compound case */
70 struct pnv_ioda_pe
*master
;
71 struct list_head slaves
;
73 /* Link in list of PE#s */
74 struct list_head list
;
77 #define PNV_PHB_FLAG_EEH (1 << 0)
80 struct pci_controller
*hose
;
81 enum pnv_phb_type type
;
82 enum pnv_phb_model model
;
90 #ifdef CONFIG_DEBUG_FS
96 unsigned int msi_base
;
97 unsigned int msi32_support
;
98 struct msi_bitmap msi_bmp
;
100 int (*msi_setup
)(struct pnv_phb
*phb
, struct pci_dev
*dev
,
101 unsigned int hwirq
, unsigned int virq
,
102 unsigned int is_64
, struct msi_msg
*msg
);
103 void (*dma_dev_setup
)(struct pnv_phb
*phb
, struct pci_dev
*pdev
);
104 void (*fixup_phb
)(struct pci_controller
*hose
);
105 int (*init_m64
)(struct pnv_phb
*phb
);
106 void (*reserve_m64_pe
)(struct pci_bus
*bus
,
107 unsigned long *pe_bitmap
, bool all
);
108 unsigned int (*pick_m64_pe
)(struct pci_bus
*bus
, bool all
);
109 int (*get_pe_state
)(struct pnv_phb
*phb
, int pe_no
);
110 void (*freeze_pe
)(struct pnv_phb
*phb
, int pe_no
);
111 int (*unfreeze_pe
)(struct pnv_phb
*phb
, int pe_no
, int opt
);
114 /* Global bridge info */
115 unsigned int total_pe_num
;
116 unsigned int reserved_pe_idx
;
118 /* 32-bit MMIO window */
119 unsigned int m32_size
;
120 unsigned int m32_segsize
;
121 unsigned int m32_pci_base
;
123 /* 64-bit MMIO window */
124 unsigned int m64_bar_idx
;
125 unsigned long m64_size
;
126 unsigned long m64_segsize
;
127 unsigned long m64_base
;
128 unsigned long m64_bar_alloc
;
131 unsigned int io_size
;
132 unsigned int io_segsize
;
133 unsigned int io_pci_base
;
136 struct mutex pe_alloc_mutex
;
137 unsigned long *pe_alloc
;
138 struct pnv_ioda_pe
*pe_array
;
140 /* M32 & IO segment maps */
141 unsigned int *m64_segmap
;
142 unsigned int *m32_segmap
;
143 unsigned int *io_segmap
;
147 struct irq_chip irq_chip
;
149 /* Sorted list of used PE's based
150 * on the sequence of creation
152 struct list_head pe_list
;
153 struct mutex pe_list_mutex
;
155 /* Reverse map of PEs, will have to extend if
156 * we are to support more than 256 PEs, indexed
159 unsigned char pe_rmap
[0x10000];
161 /* 32-bit TCE tables allocation */
162 unsigned long tce32_count
;
164 /* TCE cache invalidate registers (physical and
167 phys_addr_t tce_inval_reg_phys
;
168 __be64 __iomem
*tce_inval_reg
;
171 /* PHB and hub status structure */
173 unsigned char blob
[PNV_PCI_DIAG_BUF_SIZE
];
174 struct OpalIoP7IOCPhbErrorData p7ioc
;
175 struct OpalIoPhb3ErrorData phb3
;
176 struct OpalIoP7IOCErrorData hub_diag
;
181 extern struct pci_ops pnv_pci_ops
;
182 extern int pnv_tce_build(struct iommu_table
*tbl
, long index
, long npages
,
183 unsigned long uaddr
, enum dma_data_direction direction
,
184 struct dma_attrs
*attrs
);
185 extern void pnv_tce_free(struct iommu_table
*tbl
, long index
, long npages
);
186 extern int pnv_tce_xchg(struct iommu_table
*tbl
, long index
,
187 unsigned long *hpa
, enum dma_data_direction
*direction
);
188 extern unsigned long pnv_tce_get(struct iommu_table
*tbl
, long index
);
190 void pnv_pci_dump_phb_diag_data(struct pci_controller
*hose
,
191 unsigned char *log_buff
);
192 int pnv_pci_cfg_read(struct pci_dn
*pdn
,
193 int where
, int size
, u32
*val
);
194 int pnv_pci_cfg_write(struct pci_dn
*pdn
,
195 int where
, int size
, u32 val
);
196 extern struct iommu_table
*pnv_pci_table_alloc(int nid
);
198 extern long pnv_pci_link_table_and_group(int node
, int num
,
199 struct iommu_table
*tbl
,
200 struct iommu_table_group
*table_group
);
201 extern void pnv_pci_unlink_table_and_group(struct iommu_table
*tbl
,
202 struct iommu_table_group
*table_group
);
203 extern void pnv_pci_setup_iommu_table(struct iommu_table
*tbl
,
204 void *tce_mem
, u64 tce_size
,
205 u64 dma_offset
, unsigned page_shift
);
206 extern void pnv_pci_init_ioda_hub(struct device_node
*np
);
207 extern void pnv_pci_init_ioda2_phb(struct device_node
*np
);
208 extern void pnv_pci_init_npu_phb(struct device_node
*np
);
209 extern void pnv_pci_ioda_tce_invalidate(struct iommu_table
*tbl
,
210 __be64
*startp
, __be64
*endp
, bool rm
);
211 extern void pnv_pci_reset_secondary_bus(struct pci_dev
*dev
);
212 extern int pnv_eeh_phb_reset(struct pci_controller
*hose
, int option
);
214 extern void pnv_pci_dma_dev_setup(struct pci_dev
*pdev
);
215 extern void pnv_pci_dma_bus_setup(struct pci_bus
*bus
);
216 extern int pnv_setup_msi_irqs(struct pci_dev
*pdev
, int nvec
, int type
);
217 extern void pnv_teardown_msi_irqs(struct pci_dev
*pdev
);
219 /* Nvlink functions */
220 extern void pnv_npu_tce_invalidate_entire(struct pnv_ioda_pe
*npe
);
221 extern void pnv_npu_tce_invalidate(struct pnv_ioda_pe
*npe
,
222 struct iommu_table
*tbl
,
224 unsigned long npages
,
226 extern void pnv_npu_init_dma_pe(struct pnv_ioda_pe
*npe
);
227 extern void pnv_npu_setup_dma_pe(struct pnv_ioda_pe
*npe
);
228 extern int pnv_npu_dma_set_bypass(struct pnv_ioda_pe
*npe
, bool enabled
);
229 extern int pnv_npu_dma_set_mask(struct pci_dev
*npdev
, u64 dma_mask
);
231 #endif /* __POWERNV_PCI_H */