arch/powerpc/platforms/powernv/vas.h

   1 /*
   2  * Copyright 2016-17 IBM Corp.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9
  10 #ifndef _VAS_H
  11 #define _VAS_H
  12 #include <linux/atomic.h>
  13 #include <linux/idr.h>
  14 #include <asm/vas.h>
  15
  16 /*
  17  * Overview of Virtual Accelerator Switchboard (VAS).
  18  *
  19  * VAS is a hardware "switchboard" that allows senders and receivers to
  20  * exchange messages with _minimal_ kernel involvment. The receivers are
  21  * typically NX coprocessor engines that perform compression or encryption
  22  * in hardware, but receivers can also be other software threads.
  23  *
  24  * Senders are user/kernel threads that submit compression/encryption or
  25  * other requests to the receivers. Senders must format their messages as
  26  * Coprocessor Request Blocks (CRB)s and submit them using the "copy" and
  27  * "paste" instructions which were introduced in Power9.
  28  *
  29  * A Power node can have (upto?) 8 Power chips. There is one instance of
  30  * VAS in each Power9 chip. Each instance of VAS has 64K windows or ports,
  31  * Senders and receivers must each connect to a separate window before they
  32  * can exchange messages through the switchboard.
  33  *
  34  * Each window is described by two types of window contexts:
  35  *
  36  *      Hypervisor Window Context (HVWC) of size VAS_HVWC_SIZE bytes
  37  *
  38  *      OS/User Window Context (UWC) of size VAS_UWC_SIZE bytes.
  39  *
  40  * A window context can be viewed as a set of 64-bit registers. The settings
  41  * in these registers configure/control/determine the behavior of the VAS
  42  * hardware when messages are sent/received through the window. The registers
  43  * in the HVWC are configured by the kernel while the registers in the UWC can
  44  * be configured by the kernel or by the user space application that is using
  45  * the window.
  46  *
  47  * The HVWCs for all windows on a specific instance of VAS are in a contiguous
  48  * range of hardware addresses or Base address region (BAR) referred to as the
  49  * HVWC BAR for the instance. Similarly the UWCs for all windows on an instance
  50  * are referred to as the UWC BAR for the instance.
  51  *
  52  * The two BARs for each instance are defined Power9 MMIO Ranges spreadsheet
  53  * and available to the kernel in the VAS node's "reg" property in the device
  54  * tree:
  55  *
  56  *      /proc/device-tree/vasm@.../reg
  57  *
  58  * (see vas_probe() for details on the reg property).
  59  *
  60  * The kernel maps the HVWC and UWC BAR regions into the kernel address
  61  * space (hvwc_map and uwc_map). The kernel can then access the window
  62  * contexts of a specific window using:
  63  *
  64  *       hvwc = hvwc_map + winid * VAS_HVWC_SIZE.
  65  *       uwc = uwc_map + winid * VAS_UWC_SIZE.
  66  *
  67  * where winid is the window index (0..64K).
  68  *
  69  * As mentioned, a window context is used to "configure" a window. Besides
  70  * this configuration address, each _send_ window also has a unique hardware
  71  * "paste" address that is used to submit requests/CRBs (see vas_paste_crb()).
  72  *
  73  * The hardware paste address for a window is computed using the "paste
  74  * base address" and "paste win id shift" reg properties in the VAS device
  75  * tree node using:
  76  *
  77  *      paste_addr = paste_base + ((winid << paste_win_id_shift))
  78  *
  79  * (again, see vas_probe() for ->paste_base_addr and ->paste_win_id_shift).
  80  *
  81  * The kernel maps this hardware address into the sender's address space
  82  * after which they can use the 'paste' instruction (new in Power9) to
  83  * send a message (submit a request aka CRB) to the coprocessor.
  84  *
  85  * NOTE: In the initial version, senders can only in-kernel drivers/threads.
  86  *       Support for user space threads will be added in follow-on patches.
  87  *
  88  * TODO: Do we need to map the UWC into user address space so they can return
  89  *       credits? Its NA for NX but may be needed for other receive windows.
  90  *
  91  */
  92
  93 #define VAS_WINDOWS_PER_CHIP            (64 << 10)
  94
  95 /*
  96  * Hypervisor and OS/USer Window Context sizes
  97  */
  98 #define VAS_HVWC_SIZE                   512
  99 #define VAS_UWC_SIZE                    PAGE_SIZE
 100
 101 /*
 102  * Initial per-process credits.
 103  * Max send window credits:    4K-1 (12-bits in VAS_TX_WCRED)
 104  * Max receive window credits: 64K-1 (16 bits in VAS_LRX_WCRED)
 105  *
 106  * TODO: Needs tuning for per-process credits
 107  */
 108 #define VAS_WCREDS_MIN                  16
 109 #define VAS_WCREDS_MAX                  ((64 << 10) - 1)
 110 #define VAS_WCREDS_DEFAULT              (1 << 10)
 111
 112 /*
 113  * VAS Window Context Register Offsets and bitmasks.
 114  * See Section 3.1.4 of VAS Work book
 115  */
 116 #define VAS_LPID_OFFSET                 0x010
 117 #define VAS_LPID                        PPC_BITMASK(0, 11)
 118
 119 #define VAS_PID_OFFSET                  0x018
 120 #define VAS_PID_ID                      PPC_BITMASK(0, 19)
 121
 122 #define VAS_XLATE_MSR_OFFSET            0x020
 123 #define VAS_XLATE_MSR_DR                PPC_BIT(0)
 124 #define VAS_XLATE_MSR_TA                PPC_BIT(1)
 125 #define VAS_XLATE_MSR_PR                PPC_BIT(2)
 126 #define VAS_XLATE_MSR_US                PPC_BIT(3)
 127 #define VAS_XLATE_MSR_HV                PPC_BIT(4)
 128 #define VAS_XLATE_MSR_SF                PPC_BIT(5)
 129
 130 #define VAS_XLATE_LPCR_OFFSET           0x028
 131 #define VAS_XLATE_LPCR_PAGE_SIZE        PPC_BITMASK(0, 2)
 132 #define VAS_XLATE_LPCR_ISL              PPC_BIT(3)
 133 #define VAS_XLATE_LPCR_TC               PPC_BIT(4)
 134 #define VAS_XLATE_LPCR_SC               PPC_BIT(5)
 135
 136 #define VAS_XLATE_CTL_OFFSET            0x030
 137 #define VAS_XLATE_MODE                  PPC_BITMASK(0, 1)
 138
 139 #define VAS_AMR_OFFSET                  0x040
 140 #define VAS_AMR                         PPC_BITMASK(0, 63)
 141
 142 #define VAS_SEIDR_OFFSET                0x048
 143 #define VAS_SEIDR                       PPC_BITMASK(0, 63)
 144
 145 #define VAS_FAULT_TX_WIN_OFFSET         0x050
 146 #define VAS_FAULT_TX_WIN                PPC_BITMASK(48, 63)
 147
 148 #define VAS_OSU_INTR_SRC_RA_OFFSET      0x060
 149 #define VAS_OSU_INTR_SRC_RA             PPC_BITMASK(8, 63)
 150
 151 #define VAS_HV_INTR_SRC_RA_OFFSET       0x070
 152 #define VAS_HV_INTR_SRC_RA              PPC_BITMASK(8, 63)
 153
 154 #define VAS_PSWID_OFFSET                0x078
 155 #define VAS_PSWID_EA_HANDLE             PPC_BITMASK(0, 31)
 156
 157 #define VAS_SPARE1_OFFSET               0x080
 158 #define VAS_SPARE2_OFFSET               0x088
 159 #define VAS_SPARE3_OFFSET               0x090
 160 #define VAS_SPARE4_OFFSET               0x130
 161 #define VAS_SPARE5_OFFSET               0x160
 162 #define VAS_SPARE6_OFFSET               0x188
 163
 164 #define VAS_LFIFO_BAR_OFFSET            0x0A0
 165 #define VAS_LFIFO_BAR                   PPC_BITMASK(8, 53)
 166 #define VAS_PAGE_MIGRATION_SELECT       PPC_BITMASK(54, 56)
 167
 168 #define VAS_LDATA_STAMP_CTL_OFFSET      0x0A8
 169 #define VAS_LDATA_STAMP                 PPC_BITMASK(0, 1)
 170 #define VAS_XTRA_WRITE                  PPC_BIT(2)
 171
 172 #define VAS_LDMA_CACHE_CTL_OFFSET       0x0B0
 173 #define VAS_LDMA_TYPE                   PPC_BITMASK(0, 1)
 174 #define VAS_LDMA_FIFO_DISABLE           PPC_BIT(2)
 175
 176 #define VAS_LRFIFO_PUSH_OFFSET          0x0B8
 177 #define VAS_LRFIFO_PUSH                 PPC_BITMASK(0, 15)
 178
 179 #define VAS_CURR_MSG_COUNT_OFFSET       0x0C0
 180 #define VAS_CURR_MSG_COUNT              PPC_BITMASK(0, 7)
 181
 182 #define VAS_LNOTIFY_AFTER_COUNT_OFFSET  0x0C8
 183 #define VAS_LNOTIFY_AFTER_COUNT         PPC_BITMASK(0, 7)
 184
 185 #define VAS_LRX_WCRED_OFFSET            0x0E0
 186 #define VAS_LRX_WCRED                   PPC_BITMASK(0, 15)
 187
 188 #define VAS_LRX_WCRED_ADDER_OFFSET      0x190
 189 #define VAS_LRX_WCRED_ADDER             PPC_BITMASK(0, 15)
 190
 191 #define VAS_TX_WCRED_OFFSET             0x0F0
 192 #define VAS_TX_WCRED                    PPC_BITMASK(4, 15)
 193
 194 #define VAS_TX_WCRED_ADDER_OFFSET       0x1A0
 195 #define VAS_TX_WCRED_ADDER              PPC_BITMASK(4, 15)
 196
 197 #define VAS_LFIFO_SIZE_OFFSET           0x100
 198 #define VAS_LFIFO_SIZE                  PPC_BITMASK(0, 3)
 199
 200 #define VAS_WINCTL_OFFSET               0x108
 201 #define VAS_WINCTL_OPEN                 PPC_BIT(0)
 202 #define VAS_WINCTL_REJ_NO_CREDIT        PPC_BIT(1)
 203 #define VAS_WINCTL_PIN                  PPC_BIT(2)
 204 #define VAS_WINCTL_TX_WCRED_MODE        PPC_BIT(3)
 205 #define VAS_WINCTL_RX_WCRED_MODE        PPC_BIT(4)
 206 #define VAS_WINCTL_TX_WORD_MODE         PPC_BIT(5)
 207 #define VAS_WINCTL_RX_WORD_MODE         PPC_BIT(6)
 208 #define VAS_WINCTL_RSVD_TXBUF           PPC_BIT(7)
 209 #define VAS_WINCTL_THRESH_CTL           PPC_BITMASK(8, 9)
 210 #define VAS_WINCTL_FAULT_WIN            PPC_BIT(10)
 211 #define VAS_WINCTL_NX_WIN               PPC_BIT(11)
 212
 213 #define VAS_WIN_STATUS_OFFSET           0x110
 214 #define VAS_WIN_BUSY                    PPC_BIT(1)
 215
 216 #define VAS_WIN_CTX_CACHING_CTL_OFFSET  0x118
 217 #define VAS_CASTOUT_REQ                 PPC_BIT(0)
 218 #define VAS_PUSH_TO_MEM                 PPC_BIT(1)
 219 #define VAS_WIN_CACHE_STATUS            PPC_BIT(4)
 220
 221 #define VAS_TX_RSVD_BUF_COUNT_OFFSET    0x120
 222 #define VAS_RXVD_BUF_COUNT              PPC_BITMASK(58, 63)
 223
 224 #define VAS_LRFIFO_WIN_PTR_OFFSET       0x128
 225 #define VAS_LRX_WIN_ID                  PPC_BITMASK(0, 15)
 226
 227 /*
 228  * Local Notification Control Register controls what happens in _response_
 229  * to a paste command and hence applies only to receive windows.
 230  */
 231 #define VAS_LNOTIFY_CTL_OFFSET          0x138
 232 #define VAS_NOTIFY_DISABLE              PPC_BIT(0)
 233 #define VAS_INTR_DISABLE                PPC_BIT(1)
 234 #define VAS_NOTIFY_EARLY                PPC_BIT(2)
 235 #define VAS_NOTIFY_OSU_INTR             PPC_BIT(3)
 236
 237 #define VAS_LNOTIFY_PID_OFFSET          0x140
 238 #define VAS_LNOTIFY_PID                 PPC_BITMASK(0, 19)
 239
 240 #define VAS_LNOTIFY_LPID_OFFSET         0x148
 241 #define VAS_LNOTIFY_LPID                PPC_BITMASK(0, 11)
 242
 243 #define VAS_LNOTIFY_TID_OFFSET          0x150
 244 #define VAS_LNOTIFY_TID                 PPC_BITMASK(0, 15)
 245
 246 #define VAS_LNOTIFY_SCOPE_OFFSET        0x158
 247 #define VAS_LNOTIFY_MIN_SCOPE           PPC_BITMASK(0, 1)
 248 #define VAS_LNOTIFY_MAX_SCOPE           PPC_BITMASK(2, 3)
 249
 250 #define VAS_NX_UTIL_OFFSET              0x1B0
 251 #define VAS_NX_UTIL                     PPC_BITMASK(0, 63)
 252
 253 /* SE: Side effects */
 254 #define VAS_NX_UTIL_SE_OFFSET           0x1B8
 255 #define VAS_NX_UTIL_SE                  PPC_BITMASK(0, 63)
 256
 257 #define VAS_NX_UTIL_ADDER_OFFSET        0x180
 258 #define VAS_NX_UTIL_ADDER               PPC_BITMASK(32, 63)
 259
 260 /*
 261  * Local Notify Scope Control Register. (Receive windows only).
 262  */
 263 enum vas_notify_scope {
 264         VAS_SCOPE_LOCAL,
 265         VAS_SCOPE_GROUP,
 266         VAS_SCOPE_VECTORED_GROUP,
 267         VAS_SCOPE_UNUSED,
 268 };
 269
 270 /*
 271  * Local DMA Cache Control Register (Receive windows only).
 272  */
 273 enum vas_dma_type {
 274         VAS_DMA_TYPE_INJECT,
 275         VAS_DMA_TYPE_WRITE,
 276 };
 277
 278 /*
 279  * Local Notify Scope Control Register. (Receive windows only).
 280  * Not applicable to NX receive windows.
 281  */
 282 enum vas_notify_after_count {
 283         VAS_NOTIFY_AFTER_256 = 0,
 284         VAS_NOTIFY_NONE,
 285         VAS_NOTIFY_AFTER_2
 286 };
 287
 288 /*
 289  * One per instance of VAS. Each instance will have a separate set of
 290  * receive windows, one per coprocessor type.
 291  */
 292 struct vas_instance {
 293         int vas_id;
 294         struct ida ida;
 295         struct list_head node;
 296         struct platform_device *pdev;
 297
 298         u64 hvwc_bar_start;
 299         u64 uwc_bar_start;
 300         u64 paste_base_addr;
 301         u64 paste_win_id_shift;
 302
 303         struct mutex mutex;
 304         struct vas_window *rxwin[VAS_COP_TYPE_MAX];
 305         struct vas_window *windows[VAS_WINDOWS_PER_CHIP];
 306 };
 307
 308 /*
 309  * In-kernel state a VAS window. One per window.
 310  */
 311 struct vas_window {
 312         /* Fields common to send and receive windows */
 313         struct vas_instance *vinst;
 314         int winid;
 315         bool tx_win;            /* True if send window */
 316         bool nx_win;            /* True if NX window */
 317         bool user_win;          /* True if user space window */
 318         void *hvwc_map;         /* HV window context */
 319         void *uwc_map;          /* OS/User window context */
 320         pid_t pid;              /* Linux process id of owner */
 321
 322         /* Fields applicable only to send windows */
 323         void *paste_kaddr;
 324         char *paste_addr_name;
 325         struct vas_window *rxwin;
 326
 327         /* Feilds applicable only to receive windows */
 328         enum vas_cop_type cop;
 329         atomic_t num_txwins;
 330 };
 331
 332 /*
 333  * Container for the hardware state of a window. One per-window.
 334  *
 335  * A VAS Window context is a 512-byte area in the hardware that contains
 336  * a set of 64-bit registers. Individual bit-fields in these registers
 337  * determine the configuration/operation of the hardware. struct vas_winctx
 338  * is a container for the register fields in the window context.
 339  */
 340 struct vas_winctx {
 341         void *rx_fifo;
 342         int rx_fifo_size;
 343         int wcreds_max;
 344         int rsvd_txbuf_count;
 345
 346         bool user_win;
 347         bool nx_win;
 348         bool fault_win;
 349         bool rsvd_txbuf_enable;
 350         bool pin_win;
 351         bool rej_no_credit;
 352         bool tx_wcred_mode;
 353         bool rx_wcred_mode;
 354         bool tx_word_mode;
 355         bool rx_word_mode;
 356         bool data_stamp;
 357         bool xtra_write;
 358         bool notify_disable;
 359         bool intr_disable;
 360         bool fifo_disable;
 361         bool notify_early;
 362         bool notify_os_intr_reg;
 363
 364         int lpid;
 365         int pidr;               /* value from SPRN_PID, not linux pid */
 366         int lnotify_lpid;
 367         int lnotify_pid;
 368         int lnotify_tid;
 369         u32 pswid;
 370         int rx_win_id;
 371         int fault_win_id;
 372         int tc_mode;
 373
 374         u64 irq_port;
 375
 376         enum vas_dma_type dma_type;
 377         enum vas_notify_scope min_scope;
 378         enum vas_notify_scope max_scope;
 379         enum vas_notify_after_count notify_after_count;
 380 };
 381
 382 #endif /* _VAS_H */