arch/powerpc/platforms/ps3/spu.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  *  PS3 Platform spu routines.
   4  *
   5  *  Copyright (C) 2006 Sony Computer Entertainment Inc.
   6  *  Copyright 2006 Sony Corp.
   7  */
   8
   9 #include <linux/kernel.h>
  10 #include <linux/init.h>
  11 #include <linux/slab.h>
  12 #include <linux/mmzone.h>
  13 #include <linux/export.h>
  14 #include <linux/io.h>
  15 #include <linux/mm.h>
  16
  17 #include <asm/spu.h>
  18 #include <asm/spu_priv1.h>
  19 #include <asm/lv1call.h>
  20 #include <asm/ps3.h>
  21
  22 #include "../cell/spufs/spufs.h"
  23 #include "platform.h"
  24
  25 /* spu_management_ops */
  26
  27 /**
  28  * enum spe_type - Type of spe to create.
  29  * @spe_type_logical: Standard logical spe.
  30  *
  31  * For use with lv1_construct_logical_spe().  The current HV does not support
  32  * any types other than those listed.
  33  */
  34
  35 enum spe_type {
  36         SPE_TYPE_LOGICAL = 0,
  37 };
  38
  39 /**
  40  * struct spe_shadow - logical spe shadow register area.
  41  *
  42  * Read-only shadow of spe registers.
  43  */
  44
  45 struct spe_shadow {
  46         u8 padding_0140[0x0140];
  47         u64 int_status_class0_RW;       /* 0x0140 */
  48         u64 int_status_class1_RW;       /* 0x0148 */
  49         u64 int_status_class2_RW;       /* 0x0150 */
  50         u8 padding_0158[0x0610-0x0158];
  51         u64 mfc_dsisr_RW;               /* 0x0610 */
  52         u8 padding_0618[0x0620-0x0618];
  53         u64 mfc_dar_RW;                 /* 0x0620 */
  54         u8 padding_0628[0x0800-0x0628];
  55         u64 mfc_dsipr_R;                /* 0x0800 */
  56         u8 padding_0808[0x0810-0x0808];
  57         u64 mfc_lscrr_R;                /* 0x0810 */
  58         u8 padding_0818[0x0c00-0x0818];
  59         u64 mfc_cer_R;                  /* 0x0c00 */
  60         u8 padding_0c08[0x0f00-0x0c08];
  61         u64 spe_execution_status;       /* 0x0f00 */
  62         u8 padding_0f08[0x1000-0x0f08];
  63 };
  64
  65 /**
  66  * enum spe_ex_state - Logical spe execution state.
  67  * @spe_ex_state_unexecutable: Uninitialized.
  68  * @spe_ex_state_executable: Enabled, not ready.
  69  * @spe_ex_state_executed: Ready for use.
  70  *
  71  * The execution state (status) of the logical spe as reported in
  72  * struct spe_shadow:spe_execution_status.
  73  */
  74
  75 enum spe_ex_state {
  76         SPE_EX_STATE_UNEXECUTABLE = 0,
  77         SPE_EX_STATE_EXECUTABLE = 2,
  78         SPE_EX_STATE_EXECUTED = 3,
  79 };
  80
  81 /**
  82  * struct priv1_cache - Cached values of priv1 registers.
  83  * @masks[]: Array of cached spe interrupt masks, indexed by class.
  84  * @sr1: Cached mfc_sr1 register.
  85  * @tclass_id: Cached mfc_tclass_id register.
  86  */
  87
  88 struct priv1_cache {
  89         u64 masks[3];
  90         u64 sr1;
  91         u64 tclass_id;
  92 };
  93
  94 /**
  95  * struct spu_pdata - Platform state variables.
  96  * @spe_id: HV spe id returned by lv1_construct_logical_spe().
  97  * @resource_id: HV spe resource id returned by
  98  *      ps3_repository_read_spe_resource_id().
  99  * @priv2_addr: lpar address of spe priv2 area returned by
 100  *      lv1_construct_logical_spe().
 101  * @shadow_addr: lpar address of spe register shadow area returned by
 102  *      lv1_construct_logical_spe().
 103  * @shadow: Virtual (ioremap) address of spe register shadow area.
 104  * @cache: Cached values of priv1 registers.
 105  */
 106
 107 struct spu_pdata {
 108         u64 spe_id;
 109         u64 resource_id;
 110         u64 priv2_addr;
 111         u64 shadow_addr;
 112         struct spe_shadow __iomem *shadow;
 113         struct priv1_cache cache;
 114 };
 115
 116 static struct spu_pdata *spu_pdata(struct spu *spu)
 117 {
 118         return spu->pdata;
 119 }
 120
 121 #define dump_areas(_a, _b, _c, _d, _e) \
 122         _dump_areas(_a, _b, _c, _d, _e, __func__, __LINE__)
 123 static void _dump_areas(unsigned int spe_id, unsigned long priv2,
 124         unsigned long problem, unsigned long ls, unsigned long shadow,
 125         const char* func, int line)
 126 {
 127         pr_debug("%s:%d: spe_id:  %xh (%u)\n", func, line, spe_id, spe_id);
 128         pr_debug("%s:%d: priv2:   %lxh\n", func, line, priv2);
 129         pr_debug("%s:%d: problem: %lxh\n", func, line, problem);
 130         pr_debug("%s:%d: ls:      %lxh\n", func, line, ls);
 131         pr_debug("%s:%d: shadow:  %lxh\n", func, line, shadow);
 132 }
 133
 134 u64 ps3_get_spe_id(void *arg)
 135 {
 136         return spu_pdata(arg)->spe_id;
 137 }
 138 EXPORT_SYMBOL_GPL(ps3_get_spe_id);
 139
 140 static unsigned long get_vas_id(void)
 141 {
 142         u64 id;
 143
 144         lv1_get_logical_ppe_id(&id);
 145         lv1_get_virtual_address_space_id_of_ppe(&id);
 146
 147         return id;
 148 }
 149
 150 static int __init construct_spu(struct spu *spu)
 151 {
 152         int result;
 153         u64 unused;
 154         u64 problem_phys;
 155         u64 local_store_phys;
 156
 157         result = lv1_construct_logical_spe(PAGE_SHIFT, PAGE_SHIFT, PAGE_SHIFT,
 158                 PAGE_SHIFT, PAGE_SHIFT, get_vas_id(), SPE_TYPE_LOGICAL,
 159                 &spu_pdata(spu)->priv2_addr, &problem_phys,
 160                 &local_store_phys, &unused,
 161                 &spu_pdata(spu)->shadow_addr,
 162                 &spu_pdata(spu)->spe_id);
 163         spu->problem_phys = problem_phys;
 164         spu->local_store_phys = local_store_phys;
 165
 166         if (result) {
 167                 pr_debug("%s:%d: lv1_construct_logical_spe failed: %s\n",
 168                         __func__, __LINE__, ps3_result(result));
 169                 return result;
 170         }
 171
 172         return result;
 173 }
 174
 175 static void spu_unmap(struct spu *spu)
 176 {
 177         iounmap(spu->priv2);
 178         iounmap(spu->problem);
 179         iounmap((__force u8 __iomem *)spu->local_store);
 180         iounmap(spu_pdata(spu)->shadow);
 181 }
 182
 183 /**
 184  * setup_areas - Map the spu regions into the address space.
 185  *
 186  * The current HV requires the spu shadow regs to be mapped with the
 187  * PTE page protection bits set as read-only (PP=3).  This implementation
 188  * uses the low level __ioremap() to bypass the page protection settings
 189  * inforced by ioremap_prot() to get the needed PTE bits set for the
 190  * shadow regs.
 191  */
 192
 193 static int __init setup_areas(struct spu *spu)
 194 {
 195         struct table {char* name; unsigned long addr; unsigned long size;};
 196         unsigned long shadow_flags = pgprot_val(pgprot_noncached_wc(PAGE_KERNEL_RO));
 197
 198         spu_pdata(spu)->shadow = __ioremap(spu_pdata(spu)->shadow_addr,
 199                                            sizeof(struct spe_shadow),
 200                                            shadow_flags);
 201         if (!spu_pdata(spu)->shadow) {
 202                 pr_debug("%s:%d: ioremap shadow failed\n", __func__, __LINE__);
 203                 goto fail_ioremap;
 204         }
 205
 206         spu->local_store = (__force void *)ioremap_wc(spu->local_store_phys, LS_SIZE);
 207
 208         if (!spu->local_store) {
 209                 pr_debug("%s:%d: ioremap local_store failed\n",
 210                         __func__, __LINE__);
 211                 goto fail_ioremap;
 212         }
 213
 214         spu->problem = ioremap(spu->problem_phys,
 215                 sizeof(struct spu_problem));
 216
 217         if (!spu->problem) {
 218                 pr_debug("%s:%d: ioremap problem failed\n", __func__, __LINE__);
 219                 goto fail_ioremap;
 220         }
 221
 222         spu->priv2 = ioremap(spu_pdata(spu)->priv2_addr,
 223                 sizeof(struct spu_priv2));
 224
 225         if (!spu->priv2) {
 226                 pr_debug("%s:%d: ioremap priv2 failed\n", __func__, __LINE__);
 227                 goto fail_ioremap;
 228         }
 229
 230         dump_areas(spu_pdata(spu)->spe_id, spu_pdata(spu)->priv2_addr,
 231                 spu->problem_phys, spu->local_store_phys,
 232                 spu_pdata(spu)->shadow_addr);
 233         dump_areas(spu_pdata(spu)->spe_id, (unsigned long)spu->priv2,
 234                 (unsigned long)spu->problem, (unsigned long)spu->local_store,
 235                 (unsigned long)spu_pdata(spu)->shadow);
 236
 237         return 0;
 238
 239 fail_ioremap:
 240         spu_unmap(spu);
 241
 242         return -ENOMEM;
 243 }
 244
 245 static int __init setup_interrupts(struct spu *spu)
 246 {
 247         int result;
 248
 249         result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
 250                 0, &spu->irqs[0]);
 251
 252         if (result)
 253                 goto fail_alloc_0;
 254
 255         result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
 256                 1, &spu->irqs[1]);
 257
 258         if (result)
 259                 goto fail_alloc_1;
 260
 261         result = ps3_spe_irq_setup(PS3_BINDING_CPU_ANY, spu_pdata(spu)->spe_id,
 262                 2, &spu->irqs[2]);
 263
 264         if (result)
 265                 goto fail_alloc_2;
 266
 267         return result;
 268
 269 fail_alloc_2:
 270         ps3_spe_irq_destroy(spu->irqs[1]);
 271 fail_alloc_1:
 272         ps3_spe_irq_destroy(spu->irqs[0]);
 273 fail_alloc_0:
 274         spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = 0;
 275         return result;
 276 }
 277
 278 static int __init enable_spu(struct spu *spu)
 279 {
 280         int result;
 281
 282         result = lv1_enable_logical_spe(spu_pdata(spu)->spe_id,
 283                 spu_pdata(spu)->resource_id);
 284
 285         if (result) {
 286                 pr_debug("%s:%d: lv1_enable_logical_spe failed: %s\n",
 287                         __func__, __LINE__, ps3_result(result));
 288                 goto fail_enable;
 289         }
 290
 291         result = setup_areas(spu);
 292
 293         if (result)
 294                 goto fail_areas;
 295
 296         result = setup_interrupts(spu);
 297
 298         if (result)
 299                 goto fail_interrupts;
 300
 301         return 0;
 302
 303 fail_interrupts:
 304         spu_unmap(spu);
 305 fail_areas:
 306         lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);
 307 fail_enable:
 308         return result;
 309 }
 310
 311 static int ps3_destroy_spu(struct spu *spu)
 312 {
 313         int result;
 314
 315         pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number);
 316
 317         result = lv1_disable_logical_spe(spu_pdata(spu)->spe_id, 0);
 318         BUG_ON(result);
 319
 320         ps3_spe_irq_destroy(spu->irqs[2]);
 321         ps3_spe_irq_destroy(spu->irqs[1]);
 322         ps3_spe_irq_destroy(spu->irqs[0]);
 323
 324         spu->irqs[0] = spu->irqs[1] = spu->irqs[2] = 0;
 325
 326         spu_unmap(spu);
 327
 328         result = lv1_destruct_logical_spe(spu_pdata(spu)->spe_id);
 329         BUG_ON(result);
 330
 331         kfree(spu->pdata);
 332         spu->pdata = NULL;
 333
 334         return 0;
 335 }
 336
 337 static int __init ps3_create_spu(struct spu *spu, void *data)
 338 {
 339         int result;
 340
 341         pr_debug("%s:%d spu_%d\n", __func__, __LINE__, spu->number);
 342
 343         spu->pdata = kzalloc(sizeof(struct spu_pdata),
 344                 GFP_KERNEL);
 345
 346         if (!spu->pdata) {
 347                 result = -ENOMEM;
 348                 goto fail_malloc;
 349         }
 350
 351         spu_pdata(spu)->resource_id = (unsigned long)data;
 352
 353         /* Init cached reg values to HV defaults. */
 354
 355         spu_pdata(spu)->cache.sr1 = 0x33;
 356
 357         result = construct_spu(spu);
 358
 359         if (result)
 360                 goto fail_construct;
 361
 362         /* For now, just go ahead and enable it. */
 363
 364         result = enable_spu(spu);
 365
 366         if (result)
 367                 goto fail_enable;
 368
 369         /* Make sure the spu is in SPE_EX_STATE_EXECUTED. */
 370
 371         /* need something better here!!! */
 372         while (in_be64(&spu_pdata(spu)->shadow->spe_execution_status)
 373                 != SPE_EX_STATE_EXECUTED)
 374                 (void)0;
 375
 376         return result;
 377
 378 fail_enable:
 379 fail_construct:
 380         ps3_destroy_spu(spu);
 381 fail_malloc:
 382         return result;
 383 }
 384
 385 static int __init ps3_enumerate_spus(int (*fn)(void *data))
 386 {
 387         int result;
 388         unsigned int num_resource_id;
 389         unsigned int i;
 390
 391         result = ps3_repository_read_num_spu_resource_id(&num_resource_id);
 392
 393         pr_debug("%s:%d: num_resource_id %u\n", __func__, __LINE__,
 394                 num_resource_id);
 395
 396         /*
 397          * For now, just create logical spus equal to the number
 398          * of physical spus reserved for the partition.
 399          */
 400
 401         for (i = 0; i < num_resource_id; i++) {
 402                 enum ps3_spu_resource_type resource_type;
 403                 unsigned int resource_id;
 404
 405                 result = ps3_repository_read_spu_resource_id(i,
 406                         &resource_type, &resource_id);
 407
 408                 if (result)
 409                         break;
 410
 411                 if (resource_type == PS3_SPU_RESOURCE_TYPE_EXCLUSIVE) {
 412                         result = fn((void*)(unsigned long)resource_id);
 413
 414                         if (result)
 415                                 break;
 416                 }
 417         }
 418
 419         if (result) {
 420                 printk(KERN_WARNING "%s:%d: Error initializing spus\n",
 421                         __func__, __LINE__);
 422                 return result;
 423         }
 424
 425         return num_resource_id;
 426 }
 427
 428 static int ps3_init_affinity(void)
 429 {
 430         return 0;
 431 }
 432
 433 /**
 434  * ps3_enable_spu - Enable SPU run control.
 435  *
 436  * An outstanding enhancement for the PS3 would be to add a guard to check
 437  * for incorrect access to the spu problem state when the spu context is
 438  * disabled.  This check could be implemented with a flag added to the spu
 439  * context that would inhibit mapping problem state pages, and a routine
 440  * to unmap spu problem state pages.  When the spu is enabled with
 441  * ps3_enable_spu() the flag would be set allowing pages to be mapped,
 442  * and when the spu is disabled with ps3_disable_spu() the flag would be
 443  * cleared and the mapped problem state pages would be unmapped.
 444  */
 445
 446 static void ps3_enable_spu(struct spu_context *ctx)
 447 {
 448 }
 449
 450 static void ps3_disable_spu(struct spu_context *ctx)
 451 {
 452         ctx->ops->runcntl_stop(ctx);
 453 }
 454
 455 const struct spu_management_ops spu_management_ps3_ops = {
 456         .enumerate_spus = ps3_enumerate_spus,
 457         .create_spu = ps3_create_spu,
 458         .destroy_spu = ps3_destroy_spu,
 459         .enable_spu = ps3_enable_spu,
 460         .disable_spu = ps3_disable_spu,
 461         .init_affinity = ps3_init_affinity,
 462 };
 463
 464 /* spu_priv1_ops */
 465
 466 static void int_mask_and(struct spu *spu, int class, u64 mask)
 467 {
 468         u64 old_mask;
 469
 470         /* are these serialized by caller??? */
 471         old_mask = spu_int_mask_get(spu, class);
 472         spu_int_mask_set(spu, class, old_mask & mask);
 473 }
 474
 475 static void int_mask_or(struct spu *spu, int class, u64 mask)
 476 {
 477         u64 old_mask;
 478
 479         old_mask = spu_int_mask_get(spu, class);
 480         spu_int_mask_set(spu, class, old_mask | mask);
 481 }
 482
 483 static void int_mask_set(struct spu *spu, int class, u64 mask)
 484 {
 485         spu_pdata(spu)->cache.masks[class] = mask;
 486         lv1_set_spe_interrupt_mask(spu_pdata(spu)->spe_id, class,
 487                 spu_pdata(spu)->cache.masks[class]);
 488 }
 489
 490 static u64 int_mask_get(struct spu *spu, int class)
 491 {
 492         return spu_pdata(spu)->cache.masks[class];
 493 }
 494
 495 static void int_stat_clear(struct spu *spu, int class, u64 stat)
 496 {
 497         /* Note that MFC_DSISR will be cleared when class1[MF] is set. */
 498
 499         lv1_clear_spe_interrupt_status(spu_pdata(spu)->spe_id, class,
 500                 stat, 0);
 501 }
 502
 503 static u64 int_stat_get(struct spu *spu, int class)
 504 {
 505         u64 stat;
 506
 507         lv1_get_spe_interrupt_status(spu_pdata(spu)->spe_id, class, &stat);
 508         return stat;
 509 }
 510
 511 static void cpu_affinity_set(struct spu *spu, int cpu)
 512 {
 513         /* No support. */
 514 }
 515
 516 static u64 mfc_dar_get(struct spu *spu)
 517 {
 518         return in_be64(&spu_pdata(spu)->shadow->mfc_dar_RW);
 519 }
 520
 521 static void mfc_dsisr_set(struct spu *spu, u64 dsisr)
 522 {
 523         /* Nothing to do, cleared in int_stat_clear(). */
 524 }
 525
 526 static u64 mfc_dsisr_get(struct spu *spu)
 527 {
 528         return in_be64(&spu_pdata(spu)->shadow->mfc_dsisr_RW);
 529 }
 530
 531 static void mfc_sdr_setup(struct spu *spu)
 532 {
 533         /* Nothing to do. */
 534 }
 535
 536 static void mfc_sr1_set(struct spu *spu, u64 sr1)
 537 {
 538         /* Check bits allowed by HV. */
 539
 540         static const u64 allowed = ~(MFC_STATE1_LOCAL_STORAGE_DECODE_MASK
 541                 | MFC_STATE1_PROBLEM_STATE_MASK);
 542
 543         BUG_ON((sr1 & allowed) != (spu_pdata(spu)->cache.sr1 & allowed));
 544
 545         spu_pdata(spu)->cache.sr1 = sr1;
 546         lv1_set_spe_privilege_state_area_1_register(
 547                 spu_pdata(spu)->spe_id,
 548                 offsetof(struct spu_priv1, mfc_sr1_RW),
 549                 spu_pdata(spu)->cache.sr1);
 550 }
 551
 552 static u64 mfc_sr1_get(struct spu *spu)
 553 {
 554         return spu_pdata(spu)->cache.sr1;
 555 }
 556
 557 static void mfc_tclass_id_set(struct spu *spu, u64 tclass_id)
 558 {
 559         spu_pdata(spu)->cache.tclass_id = tclass_id;
 560         lv1_set_spe_privilege_state_area_1_register(
 561                 spu_pdata(spu)->spe_id,
 562                 offsetof(struct spu_priv1, mfc_tclass_id_RW),
 563                 spu_pdata(spu)->cache.tclass_id);
 564 }
 565
 566 static u64 mfc_tclass_id_get(struct spu *spu)
 567 {
 568         return spu_pdata(spu)->cache.tclass_id;
 569 }
 570
 571 static void tlb_invalidate(struct spu *spu)
 572 {
 573         /* Nothing to do. */
 574 }
 575
 576 static void resource_allocation_groupID_set(struct spu *spu, u64 id)
 577 {
 578         /* No support. */
 579 }
 580
 581 static u64 resource_allocation_groupID_get(struct spu *spu)
 582 {
 583         return 0; /* No support. */
 584 }
 585
 586 static void resource_allocation_enable_set(struct spu *spu, u64 enable)
 587 {
 588         /* No support. */
 589 }
 590
 591 static u64 resource_allocation_enable_get(struct spu *spu)
 592 {
 593         return 0; /* No support. */
 594 }
 595
 596 const struct spu_priv1_ops spu_priv1_ps3_ops = {
 597         .int_mask_and = int_mask_and,
 598         .int_mask_or = int_mask_or,
 599         .int_mask_set = int_mask_set,
 600         .int_mask_get = int_mask_get,
 601         .int_stat_clear = int_stat_clear,
 602         .int_stat_get = int_stat_get,
 603         .cpu_affinity_set = cpu_affinity_set,
 604         .mfc_dar_get = mfc_dar_get,
 605         .mfc_dsisr_set = mfc_dsisr_set,
 606         .mfc_dsisr_get = mfc_dsisr_get,
 607         .mfc_sdr_setup = mfc_sdr_setup,
 608         .mfc_sr1_set = mfc_sr1_set,
 609         .mfc_sr1_get = mfc_sr1_get,
 610         .mfc_tclass_id_set = mfc_tclass_id_set,
 611         .mfc_tclass_id_get = mfc_tclass_id_get,
 612         .tlb_invalidate = tlb_invalidate,
 613         .resource_allocation_groupID_set = resource_allocation_groupID_set,
 614         .resource_allocation_groupID_get = resource_allocation_groupID_get,
 615         .resource_allocation_enable_set = resource_allocation_enable_set,
 616         .resource_allocation_enable_get = resource_allocation_enable_get,
 617 };
 618
 619 void ps3_spu_set_platform(void)
 620 {
 621         spu_priv1_ops = &spu_priv1_ps3_ops;
 622         spu_management_ops = &spu_management_ps3_ops;
 623 }