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1 /*
2 * Copyright (C) 2001 Dave Engebretsen, IBM Corporation
3 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
4 *
5 * pSeries specific routines for PCI.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22 #include <linux/init.h>
23 #include <linux/ioport.h>
24 #include <linux/kernel.h>
25 #include <linux/pci.h>
26 #include <linux/string.h>
27
28 #include <asm/eeh.h>
29 #include <asm/pci-bridge.h>
30 #include <asm/prom.h>
31 #include <asm/ppc-pci.h>
32
33 #if 0
34 void pcibios_name_device(struct pci_dev *dev)
35 {
36 struct device_node *dn;
37
38 /*
39 * Add IBM loc code (slot) as a prefix to the device names for service
40 */
41 dn = pci_device_to_OF_node(dev);
42 if (dn) {
43 const char *loc_code = of_get_property(dn, "ibm,loc-code",
44 NULL);
45 if (loc_code) {
46 int loc_len = strlen(loc_code);
47 if (loc_len < sizeof(dev->dev.name)) {
48 memmove(dev->dev.name+loc_len+1, dev->dev.name,
49 sizeof(dev->dev.name)-loc_len-1);
50 memcpy(dev->dev.name, loc_code, loc_len);
51 dev->dev.name[loc_len] = ' ';
52 dev->dev.name[sizeof(dev->dev.name)-1] = '\0';
53 }
54 }
55 }
56 }
57 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_name_device);
58 #endif
59
60 static void __init pSeries_request_regions(void)
61 {
62 if (!isa_io_base)
63 return;
64
65 request_region(0x20,0x20,"pic1");
66 request_region(0xa0,0x20,"pic2");
67 request_region(0x00,0x20,"dma1");
68 request_region(0x40,0x20,"timer");
69 request_region(0x80,0x10,"dma page reg");
70 request_region(0xc0,0x20,"dma2");
71 }
72
73 void __init pSeries_final_fixup(void)
74 {
75 pSeries_request_regions();
76
77 eeh_addr_cache_build();
78 }
79
80 /*
81 * Assume the winbond 82c105 is the IDE controller on a
82 * p610/p615/p630. We should probably be more careful in case
83 * someone tries to plug in a similar adapter.
84 */
85 static void fixup_winbond_82c105(struct pci_dev* dev)
86 {
87 int i;
88 unsigned int reg;
89
90 if (!machine_is(pseries))
91 return;
92
93 printk("Using INTC for W82c105 IDE controller.\n");
94 pci_read_config_dword(dev, 0x40, &reg);
95 /* Enable LEGIRQ to use INTC instead of ISA interrupts */
96 pci_write_config_dword(dev, 0x40, reg | (1<<11));
97
98 for (i = 0; i < DEVICE_COUNT_RESOURCE; ++i) {
99 /* zap the 2nd function of the winbond chip */
100 if (dev->resource[i].flags & IORESOURCE_IO
101 && dev->bus->number == 0 && dev->devfn == 0x81)
102 dev->resource[i].flags &= ~IORESOURCE_IO;
103 if (dev->resource[i].start == 0 && dev->resource[i].end) {
104 dev->resource[i].flags = 0;
105 dev->resource[i].end = 0;
106 }
107 }
108 }
109 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105,
110 fixup_winbond_82c105);
111
112 int pseries_root_bridge_prepare(struct pci_host_bridge *bridge)
113 {
114 struct device_node *dn, *pdn;
115 struct pci_bus *bus;
116 const __be32 *pcie_link_speed_stats;
117
118 bus = bridge->bus;
119
120 dn = pcibios_get_phb_of_node(bus);
121 if (!dn)
122 return 0;
123
124 for (pdn = dn; pdn != NULL; pdn = of_get_next_parent(pdn)) {
125 pcie_link_speed_stats = of_get_property(pdn,
126 "ibm,pcie-link-speed-stats", NULL);
127 if (pcie_link_speed_stats)
128 break;
129 }
130
131 of_node_put(pdn);
132
133 if (!pcie_link_speed_stats) {
134 pr_err("no ibm,pcie-link-speed-stats property\n");
135 return 0;
136 }
137
138 switch (be32_to_cpup(pcie_link_speed_stats)) {
139 case 0x01:
140 bus->max_bus_speed = PCIE_SPEED_2_5GT;
141 break;
142 case 0x02:
143 bus->max_bus_speed = PCIE_SPEED_5_0GT;
144 break;
145 default:
146 bus->max_bus_speed = PCI_SPEED_UNKNOWN;
147 break;
148 }
149
150 switch (be32_to_cpup(pcie_link_speed_stats)) {
151 case 0x01:
152 bus->cur_bus_speed = PCIE_SPEED_2_5GT;
153 break;
154 case 0x02:
155 bus->cur_bus_speed = PCIE_SPEED_5_0GT;
156 break;
157 default:
158 bus->cur_bus_speed = PCI_SPEED_UNKNOWN;
159 break;
160 }
161
162 return 0;
163 }