arch/powerpc/sysdev/commproc.c

   1 /*
   2  * General Purpose functions for the global management of the
   3  * Communication Processor Module.
   4  * Copyright (c) 1997 Dan error_act (dmalek@jlc.net)
   5  *
   6  * In addition to the individual control of the communication
   7  * channels, there are a few functions that globally affect the
   8  * communication processor.
   9  *
  10  * Buffer descriptors must be allocated from the dual ported memory
  11  * space.  The allocator for that is here.  When the communication
  12  * process is reset, we reclaim the memory available.  There is
  13  * currently no deallocator for this memory.
  14  * The amount of space available is platform dependent.  On the
  15  * MBX, the EPPC software loads additional microcode into the
  16  * communication processor, and uses some of the DP ram for this
  17  * purpose.  Current, the first 512 bytes and the last 256 bytes of
  18  * memory are used.  Right now I am conservative and only use the
  19  * memory that can never be used for microcode.  If there are
  20  * applications that require more DP ram, we can expand the boundaries
  21  * but then we have to be careful of any downloaded microcode.
  22  */
  23 #include <linux/errno.h>
  24 #include <linux/sched.h>
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/param.h>
  28 #include <linux/string.h>
  29 #include <linux/mm.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/irq.h>
  32 #include <linux/module.h>
  33 #include <asm/mpc8xx.h>
  34 #include <asm/page.h>
  35 #include <asm/pgtable.h>
  36 #include <asm/8xx_immap.h>
  37 #include <asm/commproc.h>
  38 #include <asm/io.h>
  39 #include <asm/tlbflush.h>
  40 #include <asm/rheap.h>
  41 #include <asm/prom.h>
  42 #include <asm/cpm.h>
  43
  44 #include <asm/fs_pd.h>
  45
  46 #define CPM_MAP_SIZE    (0x4000)
  47
  48 #ifndef CONFIG_PPC_CPM_NEW_BINDING
  49 static void m8xx_cpm_dpinit(void);
  50 #endif
  51 cpm8xx_t __iomem *cpmp;  /* Pointer to comm processor space */
  52 immap_t __iomem *mpc8xx_immr;
  53 static cpic8xx_t __iomem *cpic_reg;
  54
  55 static struct irq_host *cpm_pic_host;
  56
  57 static void cpm_mask_irq(unsigned int irq)
  58 {
  59         unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;
  60
  61         clrbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
  62 }
  63
  64 static void cpm_unmask_irq(unsigned int irq)
  65 {
  66         unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;
  67
  68         setbits32(&cpic_reg->cpic_cimr, (1 << cpm_vec));
  69 }
  70
  71 static void cpm_end_irq(unsigned int irq)
  72 {
  73         unsigned int cpm_vec = (unsigned int)irq_map[irq].hwirq;
  74
  75         out_be32(&cpic_reg->cpic_cisr, (1 << cpm_vec));
  76 }
  77
  78 static struct irq_chip cpm_pic = {
  79         .typename = " CPM PIC ",
  80         .mask = cpm_mask_irq,
  81         .unmask = cpm_unmask_irq,
  82         .eoi = cpm_end_irq,
  83 };
  84
  85 int cpm_get_irq(void)
  86 {
  87         int cpm_vec;
  88
  89         /* Get the vector by setting the ACK bit and then reading
  90          * the register.
  91          */
  92         out_be16(&cpic_reg->cpic_civr, 1);
  93         cpm_vec = in_be16(&cpic_reg->cpic_civr);
  94         cpm_vec >>= 11;
  95
  96         return irq_linear_revmap(cpm_pic_host, cpm_vec);
  97 }
  98
  99 static int cpm_pic_host_map(struct irq_host *h, unsigned int virq,
 100                           irq_hw_number_t hw)
 101 {
 102         pr_debug("cpm_pic_host_map(%d, 0x%lx)\n", virq, hw);
 103
 104         get_irq_desc(virq)->status |= IRQ_LEVEL;
 105         set_irq_chip_and_handler(virq, &cpm_pic, handle_fasteoi_irq);
 106         return 0;
 107 }
 108
 109 /* The CPM can generate the error interrupt when there is a race condition
 110  * between generating and masking interrupts.  All we have to do is ACK it
 111  * and return.  This is a no-op function so we don't need any special
 112  * tests in the interrupt handler.
 113  */
 114 static irqreturn_t cpm_error_interrupt(int irq, void *dev)
 115 {
 116         return IRQ_HANDLED;
 117 }
 118
 119 static struct irqaction cpm_error_irqaction = {
 120         .handler = cpm_error_interrupt,
 121         .mask = CPU_MASK_NONE,
 122         .name = "error",
 123 };
 124
 125 static struct irq_host_ops cpm_pic_host_ops = {
 126         .map = cpm_pic_host_map,
 127 };
 128
 129 unsigned int cpm_pic_init(void)
 130 {
 131         struct device_node *np = NULL;
 132         struct resource res;
 133         unsigned int sirq = NO_IRQ, hwirq, eirq;
 134         int ret;
 135
 136         pr_debug("cpm_pic_init\n");
 137
 138         np = of_find_compatible_node(NULL, NULL, "fsl,cpm1-pic");
 139         if (np == NULL)
 140                 np = of_find_compatible_node(NULL, "cpm-pic", "CPM");
 141         if (np == NULL) {
 142                 printk(KERN_ERR "CPM PIC init: can not find cpm-pic node\n");
 143                 return sirq;
 144         }
 145
 146         ret = of_address_to_resource(np, 0, &res);
 147         if (ret)
 148                 goto end;
 149
 150         cpic_reg = ioremap(res.start, res.end - res.start + 1);
 151         if (cpic_reg == NULL)
 152                 goto end;
 153
 154         sirq = irq_of_parse_and_map(np, 0);
 155         if (sirq == NO_IRQ)
 156                 goto end;
 157
 158         /* Initialize the CPM interrupt controller. */
 159         hwirq = (unsigned int)irq_map[sirq].hwirq;
 160         out_be32(&cpic_reg->cpic_cicr,
 161             (CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
 162                 ((hwirq/2) << 13) | CICR_HP_MASK);
 163
 164         out_be32(&cpic_reg->cpic_cimr, 0);
 165
 166         cpm_pic_host = irq_alloc_host(of_node_get(np), IRQ_HOST_MAP_LINEAR,
 167                                       64, &cpm_pic_host_ops, 64);
 168         if (cpm_pic_host == NULL) {
 169                 printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
 170                 sirq = NO_IRQ;
 171                 goto end;
 172         }
 173
 174         /* Install our own error handler. */
 175         np = of_find_compatible_node(NULL, NULL, "fsl,cpm1");
 176         if (np == NULL)
 177                 np = of_find_node_by_type(NULL, "cpm");
 178         if (np == NULL) {
 179                 printk(KERN_ERR "CPM PIC init: can not find cpm node\n");
 180                 goto end;
 181         }
 182
 183         eirq = irq_of_parse_and_map(np, 0);
 184         if (eirq == NO_IRQ)
 185                 goto end;
 186
 187         if (setup_irq(eirq, &cpm_error_irqaction))
 188                 printk(KERN_ERR "Could not allocate CPM error IRQ!");
 189
 190         setbits32(&cpic_reg->cpic_cicr, CICR_IEN);
 191
 192 end:
 193         of_node_put(np);
 194         return sirq;
 195 }
 196
 197 void __init cpm_reset(void)
 198 {
 199         sysconf8xx_t __iomem *siu_conf;
 200
 201         mpc8xx_immr = ioremap(get_immrbase(), 0x4000);
 202         if (!mpc8xx_immr) {
 203                 printk(KERN_CRIT "Could not map IMMR\n");
 204                 return;
 205         }
 206
 207         cpmp = &mpc8xx_immr->im_cpm;
 208
 209 #ifndef CONFIG_PPC_EARLY_DEBUG_CPM
 210         /* Perform a reset.
 211         */
 212         out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
 213
 214         /* Wait for it.
 215         */
 216         while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG);
 217 #endif
 218
 219 #ifdef CONFIG_UCODE_PATCH
 220         cpm_load_patch(cpmp);
 221 #endif
 222
 223         /* Set SDMA Bus Request priority 5.
 224          * On 860T, this also enables FEC priority 6.  I am not sure
 225          * this is what we realy want for some applications, but the
 226          * manual recommends it.
 227          * Bit 25, FAM can also be set to use FEC aggressive mode (860T).
 228          */
 229         siu_conf = immr_map(im_siu_conf);
 230         out_be32(&siu_conf->sc_sdcr, 1);
 231         immr_unmap(siu_conf);
 232
 233 #ifdef CONFIG_PPC_CPM_NEW_BINDING
 234         cpm_muram_init();
 235 #else
 236         /* Reclaim the DP memory for our use. */
 237         m8xx_cpm_dpinit();
 238 #endif
 239 }
 240
 241 static DEFINE_SPINLOCK(cmd_lock);
 242
 243 #define MAX_CR_CMD_LOOPS        10000
 244
 245 int cpm_command(u32 command, u8 opcode)
 246 {
 247         int i, ret;
 248         unsigned long flags;
 249
 250         if (command & 0xffffff0f)
 251                 return -EINVAL;
 252
 253         spin_lock_irqsave(&cmd_lock, flags);
 254
 255         ret = 0;
 256         out_be16(&cpmp->cp_cpcr, command | CPM_CR_FLG | (opcode << 8));
 257         for (i = 0; i < MAX_CR_CMD_LOOPS; i++)
 258                 if ((in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG) == 0)
 259                         goto out;
 260
 261         printk(KERN_ERR "%s(): Not able to issue CPM command\n", __FUNCTION__);
 262         ret = -EIO;
 263 out:
 264         spin_unlock_irqrestore(&cmd_lock, flags);
 265         return ret;
 266 }
 267 EXPORT_SYMBOL(cpm_command);
 268
 269 /* Set a baud rate generator.  This needs lots of work.  There are
 270  * four BRGs, any of which can be wired to any channel.
 271  * The internal baud rate clock is the system clock divided by 16.
 272  * This assumes the baudrate is 16x oversampled by the uart.
 273  */
 274 #define BRG_INT_CLK             (get_brgfreq())
 275 #define BRG_UART_CLK            (BRG_INT_CLK/16)
 276 #define BRG_UART_CLK_DIV16      (BRG_UART_CLK/16)
 277
 278 void
 279 cpm_setbrg(uint brg, uint rate)
 280 {
 281         u32 __iomem *bp;
 282
 283         /* This is good enough to get SMCs running.....
 284         */
 285         bp = &cpmp->cp_brgc1;
 286         bp += brg;
 287         /* The BRG has a 12-bit counter.  For really slow baud rates (or
 288          * really fast processors), we may have to further divide by 16.
 289          */
 290         if (((BRG_UART_CLK / rate) - 1) < 4096)
 291                 out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN);
 292         else
 293                 out_be32(bp, (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) |
 294                              CPM_BRG_EN | CPM_BRG_DIV16);
 295 }
 296
 297 #ifndef CONFIG_PPC_CPM_NEW_BINDING
 298 /*
 299  * dpalloc / dpfree bits.
 300  */
 301 static spinlock_t cpm_dpmem_lock;
 302 /*
 303  * 16 blocks should be enough to satisfy all requests
 304  * until the memory subsystem goes up...
 305  */
 306 static rh_block_t cpm_boot_dpmem_rh_block[16];
 307 static rh_info_t cpm_dpmem_info;
 308
 309 #define CPM_DPMEM_ALIGNMENT     8
 310 static u8 __iomem *dpram_vbase;
 311 static phys_addr_t dpram_pbase;
 312
 313 static void m8xx_cpm_dpinit(void)
 314 {
 315         spin_lock_init(&cpm_dpmem_lock);
 316
 317         dpram_vbase = cpmp->cp_dpmem;
 318         dpram_pbase = get_immrbase() + offsetof(immap_t, im_cpm.cp_dpmem);
 319
 320         /* Initialize the info header */
 321         rh_init(&cpm_dpmem_info, CPM_DPMEM_ALIGNMENT,
 322                         sizeof(cpm_boot_dpmem_rh_block) /
 323                         sizeof(cpm_boot_dpmem_rh_block[0]),
 324                         cpm_boot_dpmem_rh_block);
 325
 326         /*
 327          * Attach the usable dpmem area.
 328          * XXX: This is actually crap.  CPM_DATAONLY_BASE and
 329          * CPM_DATAONLY_SIZE are a subset of the available dparm.  It varies
 330          * with the processor and the microcode patches applied / activated.
 331          * But the following should be at least safe.
 332          */
 333         rh_attach_region(&cpm_dpmem_info, CPM_DATAONLY_BASE, CPM_DATAONLY_SIZE);
 334 }
 335
 336 /*
 337  * Allocate the requested size worth of DP memory.
 338  * This function returns an offset into the DPRAM area.
 339  * Use cpm_dpram_addr() to get the virtual address of the area.
 340  */
 341 unsigned long cpm_dpalloc(uint size, uint align)
 342 {
 343         unsigned long start;
 344         unsigned long flags;
 345
 346         spin_lock_irqsave(&cpm_dpmem_lock, flags);
 347         cpm_dpmem_info.alignment = align;
 348         start = rh_alloc(&cpm_dpmem_info, size, "commproc");
 349         spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
 350
 351         return (uint)start;
 352 }
 353 EXPORT_SYMBOL(cpm_dpalloc);
 354
 355 int cpm_dpfree(unsigned long offset)
 356 {
 357         int ret;
 358         unsigned long flags;
 359
 360         spin_lock_irqsave(&cpm_dpmem_lock, flags);
 361         ret = rh_free(&cpm_dpmem_info, offset);
 362         spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
 363
 364         return ret;
 365 }
 366 EXPORT_SYMBOL(cpm_dpfree);
 367
 368 unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align)
 369 {
 370         unsigned long start;
 371         unsigned long flags;
 372
 373         spin_lock_irqsave(&cpm_dpmem_lock, flags);
 374         cpm_dpmem_info.alignment = align;
 375         start = rh_alloc_fixed(&cpm_dpmem_info, offset, size, "commproc");
 376         spin_unlock_irqrestore(&cpm_dpmem_lock, flags);
 377
 378         return start;
 379 }
 380 EXPORT_SYMBOL(cpm_dpalloc_fixed);
 381
 382 void cpm_dpdump(void)
 383 {
 384         rh_dump(&cpm_dpmem_info);
 385 }
 386 EXPORT_SYMBOL(cpm_dpdump);
 387
 388 void *cpm_dpram_addr(unsigned long offset)
 389 {
 390         return (void *)(dpram_vbase + offset);
 391 }
 392 EXPORT_SYMBOL(cpm_dpram_addr);
 393
 394 uint cpm_dpram_phys(u8 *addr)
 395 {
 396         return (dpram_pbase + (uint)(addr - dpram_vbase));
 397 }
 398 EXPORT_SYMBOL(cpm_dpram_phys);
 399 #endif /* !CONFIG_PPC_CPM_NEW_BINDING */
 400
 401 struct cpm_ioport16 {
 402         __be16 dir, par, odr_sor, dat, intr;
 403         __be16 res[3];
 404 };
 405
 406 struct cpm_ioport32 {
 407         __be32 dir, par, sor;
 408 };
 409
 410 static void cpm1_set_pin32(int port, int pin, int flags)
 411 {
 412         struct cpm_ioport32 __iomem *iop;
 413         pin = 1 << (31 - pin);
 414
 415         if (port == CPM_PORTB)
 416                 iop = (struct cpm_ioport32 __iomem *)
 417                       &mpc8xx_immr->im_cpm.cp_pbdir;
 418         else
 419                 iop = (struct cpm_ioport32 __iomem *)
 420                       &mpc8xx_immr->im_cpm.cp_pedir;
 421
 422         if (flags & CPM_PIN_OUTPUT)
 423                 setbits32(&iop->dir, pin);
 424         else
 425                 clrbits32(&iop->dir, pin);
 426
 427         if (!(flags & CPM_PIN_GPIO))
 428                 setbits32(&iop->par, pin);
 429         else
 430                 clrbits32(&iop->par, pin);
 431
 432         if (port == CPM_PORTB) {
 433                 if (flags & CPM_PIN_OPENDRAIN)
 434                         setbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
 435                 else
 436                         clrbits16(&mpc8xx_immr->im_cpm.cp_pbodr, pin);
 437         }
 438
 439         if (port == CPM_PORTE) {
 440                 if (flags & CPM_PIN_SECONDARY)
 441                         setbits32(&iop->sor, pin);
 442                 else
 443                         clrbits32(&iop->sor, pin);
 444
 445                 if (flags & CPM_PIN_OPENDRAIN)
 446                         setbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
 447                 else
 448                         clrbits32(&mpc8xx_immr->im_cpm.cp_peodr, pin);
 449         }
 450 }
 451
 452 static void cpm1_set_pin16(int port, int pin, int flags)
 453 {
 454         struct cpm_ioport16 __iomem *iop =
 455                 (struct cpm_ioport16 __iomem *)&mpc8xx_immr->im_ioport;
 456
 457         pin = 1 << (15 - pin);
 458
 459         if (port != 0)
 460                 iop += port - 1;
 461
 462         if (flags & CPM_PIN_OUTPUT)
 463                 setbits16(&iop->dir, pin);
 464         else
 465                 clrbits16(&iop->dir, pin);
 466
 467         if (!(flags & CPM_PIN_GPIO))
 468                 setbits16(&iop->par, pin);
 469         else
 470                 clrbits16(&iop->par, pin);
 471
 472         if (port == CPM_PORTA) {
 473                 if (flags & CPM_PIN_OPENDRAIN)
 474                         setbits16(&iop->odr_sor, pin);
 475                 else
 476                         clrbits16(&iop->odr_sor, pin);
 477         }
 478         if (port == CPM_PORTC) {
 479                 if (flags & CPM_PIN_SECONDARY)
 480                         setbits16(&iop->odr_sor, pin);
 481                 else
 482                         clrbits16(&iop->odr_sor, pin);
 483         }
 484 }
 485
 486 void cpm1_set_pin(enum cpm_port port, int pin, int flags)
 487 {
 488         if (port == CPM_PORTB || port == CPM_PORTE)
 489                 cpm1_set_pin32(port, pin, flags);
 490         else
 491                 cpm1_set_pin16(port, pin, flags);
 492 }
 493
 494 int cpm1_clk_setup(enum cpm_clk_target target, int clock, int mode)
 495 {
 496         int shift;
 497         int i, bits = 0;
 498         u32 __iomem *reg;
 499         u32 mask = 7;
 500
 501         u8 clk_map[][3] = {
 502                 {CPM_CLK_SCC1, CPM_BRG1, 0},
 503                 {CPM_CLK_SCC1, CPM_BRG2, 1},
 504                 {CPM_CLK_SCC1, CPM_BRG3, 2},
 505                 {CPM_CLK_SCC1, CPM_BRG4, 3},
 506                 {CPM_CLK_SCC1, CPM_CLK1, 4},
 507                 {CPM_CLK_SCC1, CPM_CLK2, 5},
 508                 {CPM_CLK_SCC1, CPM_CLK3, 6},
 509                 {CPM_CLK_SCC1, CPM_CLK4, 7},
 510
 511                 {CPM_CLK_SCC2, CPM_BRG1, 0},
 512                 {CPM_CLK_SCC2, CPM_BRG2, 1},
 513                 {CPM_CLK_SCC2, CPM_BRG3, 2},
 514                 {CPM_CLK_SCC2, CPM_BRG4, 3},
 515                 {CPM_CLK_SCC2, CPM_CLK1, 4},
 516                 {CPM_CLK_SCC2, CPM_CLK2, 5},
 517                 {CPM_CLK_SCC2, CPM_CLK3, 6},
 518                 {CPM_CLK_SCC2, CPM_CLK4, 7},
 519
 520                 {CPM_CLK_SCC3, CPM_BRG1, 0},
 521                 {CPM_CLK_SCC3, CPM_BRG2, 1},
 522                 {CPM_CLK_SCC3, CPM_BRG3, 2},
 523                 {CPM_CLK_SCC3, CPM_BRG4, 3},
 524                 {CPM_CLK_SCC3, CPM_CLK5, 4},
 525                 {CPM_CLK_SCC3, CPM_CLK6, 5},
 526                 {CPM_CLK_SCC3, CPM_CLK7, 6},
 527                 {CPM_CLK_SCC3, CPM_CLK8, 7},
 528
 529                 {CPM_CLK_SCC4, CPM_BRG1, 0},
 530                 {CPM_CLK_SCC4, CPM_BRG2, 1},
 531                 {CPM_CLK_SCC4, CPM_BRG3, 2},
 532                 {CPM_CLK_SCC4, CPM_BRG4, 3},
 533                 {CPM_CLK_SCC4, CPM_CLK5, 4},
 534                 {CPM_CLK_SCC4, CPM_CLK6, 5},
 535                 {CPM_CLK_SCC4, CPM_CLK7, 6},
 536                 {CPM_CLK_SCC4, CPM_CLK8, 7},
 537
 538                 {CPM_CLK_SMC1, CPM_BRG1, 0},
 539                 {CPM_CLK_SMC1, CPM_BRG2, 1},
 540                 {CPM_CLK_SMC1, CPM_BRG3, 2},
 541                 {CPM_CLK_SMC1, CPM_BRG4, 3},
 542                 {CPM_CLK_SMC1, CPM_CLK1, 4},
 543                 {CPM_CLK_SMC1, CPM_CLK2, 5},
 544                 {CPM_CLK_SMC1, CPM_CLK3, 6},
 545                 {CPM_CLK_SMC1, CPM_CLK4, 7},
 546
 547                 {CPM_CLK_SMC2, CPM_BRG1, 0},
 548                 {CPM_CLK_SMC2, CPM_BRG2, 1},
 549                 {CPM_CLK_SMC2, CPM_BRG3, 2},
 550                 {CPM_CLK_SMC2, CPM_BRG4, 3},
 551                 {CPM_CLK_SMC2, CPM_CLK5, 4},
 552                 {CPM_CLK_SMC2, CPM_CLK6, 5},
 553                 {CPM_CLK_SMC2, CPM_CLK7, 6},
 554                 {CPM_CLK_SMC2, CPM_CLK8, 7},
 555         };
 556
 557         switch (target) {
 558         case CPM_CLK_SCC1:
 559                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 560                 shift = 0;
 561                 break;
 562
 563         case CPM_CLK_SCC2:
 564                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 565                 shift = 8;
 566                 break;
 567
 568         case CPM_CLK_SCC3:
 569                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 570                 shift = 16;
 571                 break;
 572
 573         case CPM_CLK_SCC4:
 574                 reg = &mpc8xx_immr->im_cpm.cp_sicr;
 575                 shift = 24;
 576                 break;
 577
 578         case CPM_CLK_SMC1:
 579                 reg = &mpc8xx_immr->im_cpm.cp_simode;
 580                 shift = 12;
 581                 break;
 582
 583         case CPM_CLK_SMC2:
 584                 reg = &mpc8xx_immr->im_cpm.cp_simode;
 585                 shift = 28;
 586                 break;
 587
 588         default:
 589                 printk(KERN_ERR "cpm1_clock_setup: invalid clock target\n");
 590                 return -EINVAL;
 591         }
 592
 593         if (reg == &mpc8xx_immr->im_cpm.cp_sicr && mode == CPM_CLK_RX)
 594                 shift += 3;
 595
 596         for (i = 0; i < ARRAY_SIZE(clk_map); i++) {
 597                 if (clk_map[i][0] == target && clk_map[i][1] == clock) {
 598                         bits = clk_map[i][2];
 599                         break;
 600                 }
 601         }
 602
 603         if (i == ARRAY_SIZE(clk_map)) {
 604                 printk(KERN_ERR "cpm1_clock_setup: invalid clock combination\n");
 605                 return -EINVAL;
 606         }
 607
 608         bits <<= shift;
 609         mask <<= shift;
 610         out_be32(reg, (in_be32(reg) & ~mask) | bits);
 611
 612         return 0;
 613 }