arch/powerpc/sysdev/dart_iommu.c

   1 /*
   2  * arch/powerpc/sysdev/dart_iommu.c
   3  *
   4  * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
   5  * Copyright (C) 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>,
   6  *                    IBM Corporation
   7  *
   8  * Based on pSeries_iommu.c:
   9  * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
  10  * Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
  11  *
  12  * Dynamic DMA mapping support, Apple U3, U4 & IBM CPC925 "DART" iommu.
  13  *
  14  *
  15  * This program is free software; you can redistribute it and/or modify
  16  * it under the terms of the GNU General Public License as published by
  17  * the Free Software Foundation; either version 2 of the License, or
  18  * (at your option) any later version.
  19  *
  20  * This program is distributed in the hope that it will be useful,
  21  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23  * GNU General Public License for more details.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  28  */
  29
  30 #include <linux/init.h>
  31 #include <linux/types.h>
  32 #include <linux/mm.h>
  33 #include <linux/spinlock.h>
  34 #include <linux/string.h>
  35 #include <linux/pci.h>
  36 #include <linux/dma-mapping.h>
  37 #include <linux/vmalloc.h>
  38 #include <linux/suspend.h>
  39 #include <linux/memblock.h>
  40 #include <linux/gfp.h>
  41 #include <linux/kmemleak.h>
  42 #include <asm/io.h>
  43 #include <asm/prom.h>
  44 #include <asm/iommu.h>
  45 #include <asm/pci-bridge.h>
  46 #include <asm/machdep.h>
  47 #include <asm/cacheflush.h>
  48 #include <asm/ppc-pci.h>
  49
  50 #include "dart.h"
  51
  52 /* DART table address and size */
  53 static u32 *dart_tablebase;
  54 static unsigned long dart_tablesize;
  55
  56 /* Mapped base address for the dart */
  57 static unsigned int __iomem *dart;
  58
  59 /* Dummy val that entries are set to when unused */
  60 static unsigned int dart_emptyval;
  61
  62 static struct iommu_table iommu_table_dart;
  63 static int iommu_table_dart_inited;
  64 static int dart_dirty;
  65 static int dart_is_u4;
  66
  67 #define DART_U4_BYPASS_BASE     0x8000000000ull
  68
  69 #define DBG(...)
  70
  71 static DEFINE_SPINLOCK(invalidate_lock);
  72
  73 static inline void dart_tlb_invalidate_all(void)
  74 {
  75         unsigned long l = 0;
  76         unsigned int reg, inv_bit;
  77         unsigned long limit;
  78         unsigned long flags;
  79
  80         spin_lock_irqsave(&invalidate_lock, flags);
  81
  82         DBG("dart: flush\n");
  83
  84         /* To invalidate the DART, set the DARTCNTL_FLUSHTLB bit in the
  85          * control register and wait for it to clear.
  86          *
  87          * Gotcha: Sometimes, the DART won't detect that the bit gets
  88          * set. If so, clear it and set it again.
  89          */
  90
  91         limit = 0;
  92
  93         inv_bit = dart_is_u4 ? DART_CNTL_U4_FLUSHTLB : DART_CNTL_U3_FLUSHTLB;
  94 retry:
  95         l = 0;
  96         reg = DART_IN(DART_CNTL);
  97         reg |= inv_bit;
  98         DART_OUT(DART_CNTL, reg);
  99
 100         while ((DART_IN(DART_CNTL) & inv_bit) && l < (1L << limit))
 101                 l++;
 102         if (l == (1L << limit)) {
 103                 if (limit < 4) {
 104                         limit++;
 105                         reg = DART_IN(DART_CNTL);
 106                         reg &= ~inv_bit;
 107                         DART_OUT(DART_CNTL, reg);
 108                         goto retry;
 109                 } else
 110                         panic("DART: TLB did not flush after waiting a long "
 111                               "time. Buggy U3 ?");
 112         }
 113
 114         spin_unlock_irqrestore(&invalidate_lock, flags);
 115 }
 116
 117 static inline void dart_tlb_invalidate_one(unsigned long bus_rpn)
 118 {
 119         unsigned int reg;
 120         unsigned int l, limit;
 121         unsigned long flags;
 122
 123         spin_lock_irqsave(&invalidate_lock, flags);
 124
 125         reg = DART_CNTL_U4_ENABLE | DART_CNTL_U4_IONE |
 126                 (bus_rpn & DART_CNTL_U4_IONE_MASK);
 127         DART_OUT(DART_CNTL, reg);
 128
 129         limit = 0;
 130 wait_more:
 131         l = 0;
 132         while ((DART_IN(DART_CNTL) & DART_CNTL_U4_IONE) && l < (1L << limit)) {
 133                 rmb();
 134                 l++;
 135         }
 136
 137         if (l == (1L << limit)) {
 138                 if (limit < 4) {
 139                         limit++;
 140                         goto wait_more;
 141                 } else
 142                         panic("DART: TLB did not flush after waiting a long "
 143                               "time. Buggy U4 ?");
 144         }
 145
 146         spin_unlock_irqrestore(&invalidate_lock, flags);
 147 }
 148
 149 static void dart_cache_sync(unsigned int *base, unsigned int count)
 150 {
 151         /*
 152          * We add 1 to the number of entries to flush, following a
 153          * comment in Darwin indicating that the memory controller
 154          * can prefetch unmapped memory under some circumstances.
 155          */
 156         unsigned long start = (unsigned long)base;
 157         unsigned long end = start + (count + 1) * sizeof(unsigned int);
 158         unsigned int tmp;
 159
 160         /* Perform a standard cache flush */
 161         flush_inval_dcache_range(start, end);
 162
 163         /*
 164          * Perform the sequence described in the CPC925 manual to
 165          * ensure all the data gets to a point the cache incoherent
 166          * DART hardware will see.
 167          */
 168         asm volatile(" sync;"
 169                      " isync;"
 170                      " dcbf 0,%1;"
 171                      " sync;"
 172                      " isync;"
 173                      " lwz %0,0(%1);"
 174                      " isync" : "=r" (tmp) : "r" (end) : "memory");
 175 }
 176
 177 static void dart_flush(struct iommu_table *tbl)
 178 {
 179         mb();
 180         if (dart_dirty) {
 181                 dart_tlb_invalidate_all();
 182                 dart_dirty = 0;
 183         }
 184 }
 185
 186 static int dart_build(struct iommu_table *tbl, long index,
 187                        long npages, unsigned long uaddr,
 188                        enum dma_data_direction direction,
 189                        unsigned long attrs)
 190 {
 191         unsigned int *dp, *orig_dp;
 192         unsigned int rpn;
 193         long l;
 194
 195         DBG("dart: build at: %lx, %lx, addr: %x\n", index, npages, uaddr);
 196
 197         orig_dp = dp = ((unsigned int*)tbl->it_base) + index;
 198
 199         /* On U3, all memory is contiguous, so we can move this
 200          * out of the loop.
 201          */
 202         l = npages;
 203         while (l--) {
 204                 rpn = __pa(uaddr) >> DART_PAGE_SHIFT;
 205
 206                 *(dp++) = DARTMAP_VALID | (rpn & DARTMAP_RPNMASK);
 207
 208                 uaddr += DART_PAGE_SIZE;
 209         }
 210         dart_cache_sync(orig_dp, npages);
 211
 212         if (dart_is_u4) {
 213                 rpn = index;
 214                 while (npages--)
 215                         dart_tlb_invalidate_one(rpn++);
 216         } else {
 217                 dart_dirty = 1;
 218         }
 219         return 0;
 220 }
 221
 222
 223 static void dart_free(struct iommu_table *tbl, long index, long npages)
 224 {
 225         unsigned int *dp, *orig_dp;
 226         long orig_npages = npages;
 227
 228         /* We don't worry about flushing the TLB cache. The only drawback of
 229          * not doing it is that we won't catch buggy device drivers doing
 230          * bad DMAs, but then no 32-bit architecture ever does either.
 231          */
 232
 233         DBG("dart: free at: %lx, %lx\n", index, npages);
 234
 235         orig_dp = dp  = ((unsigned int *)tbl->it_base) + index;
 236
 237         while (npages--)
 238                 *(dp++) = dart_emptyval;
 239
 240         dart_cache_sync(orig_dp, orig_npages);
 241 }
 242
 243 static void allocate_dart(void)
 244 {
 245         unsigned long tmp;
 246
 247         /* 512 pages (2MB) is max DART tablesize. */
 248         dart_tablesize = 1UL << 21;
 249
 250         /*
 251          * 16MB (1 << 24) alignment. We allocate a full 16Mb chuck since we
 252          * will blow up an entire large page anyway in the kernel mapping.
 253          */
 254         dart_tablebase = memblock_alloc_try_nid_raw(SZ_16M, SZ_16M,
 255                                         MEMBLOCK_LOW_LIMIT, SZ_2G,
 256                                         NUMA_NO_NODE);
 257         if (!dart_tablebase)
 258                 panic("Failed to allocate 16MB below 2GB for DART table\n");
 259
 260         /* There is no point scanning the DART space for leaks*/
 261         kmemleak_no_scan((void *)dart_tablebase);
 262
 263         /* Allocate a spare page to map all invalid DART pages. We need to do
 264          * that to work around what looks like a problem with the HT bridge
 265          * prefetching into invalid pages and corrupting data
 266          */
 267         tmp = memblock_phys_alloc(DART_PAGE_SIZE, DART_PAGE_SIZE);
 268         if (!tmp)
 269                 panic("DART: table allocation failed\n");
 270
 271         dart_emptyval = DARTMAP_VALID | ((tmp >> DART_PAGE_SHIFT) &
 272                                          DARTMAP_RPNMASK);
 273
 274         printk(KERN_INFO "DART table allocated at: %p\n", dart_tablebase);
 275 }
 276
 277 static int __init dart_init(struct device_node *dart_node)
 278 {
 279         unsigned int i;
 280         unsigned long base, size;
 281         struct resource r;
 282
 283         /* IOMMU disabled by the user ? bail out */
 284         if (iommu_is_off)
 285                 return -ENODEV;
 286
 287         /*
 288          * Only use the DART if the machine has more than 1GB of RAM
 289          * or if requested with iommu=on on cmdline.
 290          *
 291          * 1GB of RAM is picked as limit because some default devices
 292          * (i.e. Airport Extreme) have 30 bit address range limits.
 293          */
 294
 295         if (!iommu_force_on && memblock_end_of_DRAM() <= 0x40000000ull)
 296                 return -ENODEV;
 297
 298         /* Get DART registers */
 299         if (of_address_to_resource(dart_node, 0, &r))
 300                 panic("DART: can't get register base ! ");
 301
 302         /* Map in DART registers */
 303         dart = ioremap(r.start, resource_size(&r));
 304         if (dart == NULL)
 305                 panic("DART: Cannot map registers!");
 306
 307         /* Allocate the DART and dummy page */
 308         allocate_dart();
 309
 310         /* Fill initial table */
 311         for (i = 0; i < dart_tablesize/4; i++)
 312                 dart_tablebase[i] = dart_emptyval;
 313
 314         /* Push to memory */
 315         dart_cache_sync(dart_tablebase, dart_tablesize / sizeof(u32));
 316
 317         /* Initialize DART with table base and enable it. */
 318         base = ((unsigned long)dart_tablebase) >> DART_PAGE_SHIFT;
 319         size = dart_tablesize >> DART_PAGE_SHIFT;
 320         if (dart_is_u4) {
 321                 size &= DART_SIZE_U4_SIZE_MASK;
 322                 DART_OUT(DART_BASE_U4, base);
 323                 DART_OUT(DART_SIZE_U4, size);
 324                 DART_OUT(DART_CNTL, DART_CNTL_U4_ENABLE);
 325         } else {
 326                 size &= DART_CNTL_U3_SIZE_MASK;
 327                 DART_OUT(DART_CNTL,
 328                          DART_CNTL_U3_ENABLE |
 329                          (base << DART_CNTL_U3_BASE_SHIFT) |
 330                          (size << DART_CNTL_U3_SIZE_SHIFT));
 331         }
 332
 333         /* Invalidate DART to get rid of possible stale TLBs */
 334         dart_tlb_invalidate_all();
 335
 336         printk(KERN_INFO "DART IOMMU initialized for %s type chipset\n",
 337                dart_is_u4 ? "U4" : "U3");
 338
 339         return 0;
 340 }
 341
 342 static struct iommu_table_ops iommu_dart_ops = {
 343         .set = dart_build,
 344         .clear = dart_free,
 345         .flush = dart_flush,
 346 };
 347
 348 static void iommu_table_dart_setup(void)
 349 {
 350         iommu_table_dart.it_busno = 0;
 351         iommu_table_dart.it_offset = 0;
 352         /* it_size is in number of entries */
 353         iommu_table_dart.it_size = dart_tablesize / sizeof(u32);
 354         iommu_table_dart.it_page_shift = IOMMU_PAGE_SHIFT_4K;
 355
 356         /* Initialize the common IOMMU code */
 357         iommu_table_dart.it_base = (unsigned long)dart_tablebase;
 358         iommu_table_dart.it_index = 0;
 359         iommu_table_dart.it_blocksize = 1;
 360         iommu_table_dart.it_ops = &iommu_dart_ops;
 361         iommu_init_table(&iommu_table_dart, -1);
 362
 363         /* Reserve the last page of the DART to avoid possible prefetch
 364          * past the DART mapped area
 365          */
 366         set_bit(iommu_table_dart.it_size - 1, iommu_table_dart.it_map);
 367 }
 368
 369 static void pci_dma_bus_setup_dart(struct pci_bus *bus)
 370 {
 371         if (!iommu_table_dart_inited) {
 372                 iommu_table_dart_inited = 1;
 373                 iommu_table_dart_setup();
 374         }
 375 }
 376
 377 static bool dart_device_on_pcie(struct device *dev)
 378 {
 379         struct device_node *np = of_node_get(dev->of_node);
 380
 381         while(np) {
 382                 if (of_device_is_compatible(np, "U4-pcie") ||
 383                     of_device_is_compatible(np, "u4-pcie")) {
 384                         of_node_put(np);
 385                         return true;
 386                 }
 387                 np = of_get_next_parent(np);
 388         }
 389         return false;
 390 }
 391
 392 static void pci_dma_dev_setup_dart(struct pci_dev *dev)
 393 {
 394         if (dart_is_u4 && dart_device_on_pcie(&dev->dev))
 395                 dev->dev.archdata.dma_offset = DART_U4_BYPASS_BASE;
 396         set_iommu_table_base(&dev->dev, &iommu_table_dart);
 397 }
 398
 399 static bool iommu_bypass_supported_dart(struct pci_dev *dev, u64 mask)
 400 {
 401         return dart_is_u4 &&
 402                 dart_device_on_pcie(&dev->dev) &&
 403                 mask >= DMA_BIT_MASK(40);
 404 }
 405
 406 void __init iommu_init_early_dart(struct pci_controller_ops *controller_ops)
 407 {
 408         struct device_node *dn;
 409
 410         /* Find the DART in the device-tree */
 411         dn = of_find_compatible_node(NULL, "dart", "u3-dart");
 412         if (dn == NULL) {
 413                 dn = of_find_compatible_node(NULL, "dart", "u4-dart");
 414                 if (dn == NULL)
 415                         return; /* use default direct_dma_ops */
 416                 dart_is_u4 = 1;
 417         }
 418
 419         /* Initialize the DART HW */
 420         if (dart_init(dn) != 0)
 421                 return;
 422
 423         /*
 424          * U4 supports a DART bypass, we use it for 64-bit capable devices to
 425          * improve performance.  However, that only works for devices connected
 426          * to the U4 own PCIe interface, not bridged through hypertransport.
 427          * We need the device to support at least 40 bits of addresses.
 428          */
 429         controller_ops->dma_dev_setup = pci_dma_dev_setup_dart;
 430         controller_ops->dma_bus_setup = pci_dma_bus_setup_dart;
 431         controller_ops->iommu_bypass_supported = iommu_bypass_supported_dart;
 432
 433         /* Setup pci_dma ops */
 434         set_pci_dma_ops(&dma_iommu_ops);
 435 }
 436
 437 #ifdef CONFIG_PM
 438 static void iommu_dart_restore(void)
 439 {
 440         dart_cache_sync(dart_tablebase, dart_tablesize / sizeof(u32));
 441         dart_tlb_invalidate_all();
 442 }
 443
 444 static int __init iommu_init_late_dart(void)
 445 {
 446         if (!dart_tablebase)
 447                 return 0;
 448
 449         ppc_md.iommu_restore = iommu_dart_restore;
 450
 451         return 0;
 452 }
 453
 454 late_initcall(iommu_init_late_dart);
 455 #endif /* CONFIG_PM */