arch/powerpc/sysdev/fsl_msi.c

   1 /*
   2  * Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
   3  *
   4  * Author: Tony Li <tony.li@freescale.com>
   5  *         Jason Jin <Jason.jin@freescale.com>
   6  *
   7  * The hwirq alloc and free code reuse from sysdev/mpic_msi.c
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; version 2 of the
  12  * License.
  13  *
  14  */
  15 #include <linux/irq.h>
  16 #include <linux/msi.h>
  17 #include <linux/pci.h>
  18 #include <linux/slab.h>
  19 #include <linux/of_platform.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/seq_file.h>
  22 #include <sysdev/fsl_soc.h>
  23 #include <asm/prom.h>
  24 #include <asm/hw_irq.h>
  25 #include <asm/ppc-pci.h>
  26 #include <asm/mpic.h>
  27 #include <asm/fsl_hcalls.h>
  28
  29 #include "fsl_msi.h"
  30 #include "fsl_pci.h"
  31
  32 #define MSIIR_OFFSET_MASK       0xfffff
  33 #define MSIIR_IBS_SHIFT         0
  34 #define MSIIR_SRS_SHIFT         5
  35 #define MSIIR1_IBS_SHIFT        4
  36 #define MSIIR1_SRS_SHIFT        0
  37 #define MSI_SRS_MASK            0xf
  38 #define MSI_IBS_MASK            0x1f
  39
  40 #define msi_hwirq(msi, msir_index, intr_index) \
  41                 ((msir_index) << (msi)->srs_shift | \
  42                  ((intr_index) << (msi)->ibs_shift))
  43
  44 static LIST_HEAD(msi_head);
  45
  46 struct fsl_msi_feature {
  47         u32 fsl_pic_ip;
  48         u32 msiir_offset; /* Offset of MSIIR, relative to start of MSIR bank */
  49 };
  50
  51 struct fsl_msi_cascade_data {
  52         struct fsl_msi *msi_data;
  53         int index;
  54         int virq;
  55 };
  56
  57 static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
  58 {
  59         return in_be32(base + (reg >> 2));
  60 }
  61
  62 /*
  63  * We do not need this actually. The MSIR register has been read once
  64  * in the cascade interrupt. So, this MSI interrupt has been acked
  65 */
  66 static void fsl_msi_end_irq(struct irq_data *d)
  67 {
  68 }
  69
  70 static void fsl_msi_print_chip(struct irq_data *irqd, struct seq_file *p)
  71 {
  72         struct fsl_msi *msi_data = irqd->domain->host_data;
  73         irq_hw_number_t hwirq = irqd_to_hwirq(irqd);
  74         int cascade_virq, srs;
  75
  76         srs = (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK;
  77         cascade_virq = msi_data->cascade_array[srs]->virq;
  78
  79         seq_printf(p, " fsl-msi-%d", cascade_virq);
  80 }
  81
  82
  83 static struct irq_chip fsl_msi_chip = {
  84         .irq_mask       = pci_msi_mask_irq,
  85         .irq_unmask     = pci_msi_unmask_irq,
  86         .irq_ack        = fsl_msi_end_irq,
  87         .irq_print_chip = fsl_msi_print_chip,
  88 };
  89
  90 static int fsl_msi_host_map(struct irq_domain *h, unsigned int virq,
  91                                 irq_hw_number_t hw)
  92 {
  93         struct fsl_msi *msi_data = h->host_data;
  94         struct irq_chip *chip = &fsl_msi_chip;
  95
  96         irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING);
  97
  98         irq_set_chip_data(virq, msi_data);
  99         irq_set_chip_and_handler(virq, chip, handle_edge_irq);
 100
 101         return 0;
 102 }
 103
 104 static const struct irq_domain_ops fsl_msi_host_ops = {
 105         .map = fsl_msi_host_map,
 106 };
 107
 108 static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
 109 {
 110         int rc, hwirq;
 111
 112         rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS_MAX,
 113                               msi_data->irqhost->of_node);
 114         if (rc)
 115                 return rc;
 116
 117         /*
 118          * Reserve all the hwirqs
 119          * The available hwirqs will be released in fsl_msi_setup_hwirq()
 120          */
 121         for (hwirq = 0; hwirq < NR_MSI_IRQS_MAX; hwirq++)
 122                 msi_bitmap_reserve_hwirq(&msi_data->bitmap, hwirq);
 123
 124         return 0;
 125 }
 126
 127 static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
 128 {
 129         struct msi_desc *entry;
 130         struct fsl_msi *msi_data;
 131
 132         list_for_each_entry(entry, &pdev->msi_list, list) {
 133                 if (entry->irq == NO_IRQ)
 134                         continue;
 135                 msi_data = irq_get_chip_data(entry->irq);
 136                 irq_set_msi_desc(entry->irq, NULL);
 137                 msi_bitmap_free_hwirqs(&msi_data->bitmap,
 138                                        virq_to_hw(entry->irq), 1);
 139                 irq_dispose_mapping(entry->irq);
 140         }
 141
 142         return;
 143 }
 144
 145 static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
 146                                 struct msi_msg *msg,
 147                                 struct fsl_msi *fsl_msi_data)
 148 {
 149         struct fsl_msi *msi_data = fsl_msi_data;
 150         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
 151         u64 address; /* Physical address of the MSIIR */
 152         int len;
 153         const __be64 *reg;
 154
 155         /* If the msi-address-64 property exists, then use it */
 156         reg = of_get_property(hose->dn, "msi-address-64", &len);
 157         if (reg && (len == sizeof(u64)))
 158                 address = be64_to_cpup(reg);
 159         else
 160                 address = fsl_pci_immrbar_base(hose) + msi_data->msiir_offset;
 161
 162         msg->address_lo = lower_32_bits(address);
 163         msg->address_hi = upper_32_bits(address);
 164
 165         /*
 166          * MPIC version 2.0 has erratum PIC1. It causes
 167          * that neither MSI nor MSI-X can work fine.
 168          * This is a workaround to allow MSI-X to function
 169          * properly. It only works for MSI-X, we prevent
 170          * MSI on buggy chips in fsl_setup_msi_irqs().
 171          */
 172         if (msi_data->feature & MSI_HW_ERRATA_ENDIAN)
 173                 msg->data = __swab32(hwirq);
 174         else
 175                 msg->data = hwirq;
 176
 177         pr_debug("%s: allocated srs: %d, ibs: %d\n", __func__,
 178                  (hwirq >> msi_data->srs_shift) & MSI_SRS_MASK,
 179                  (hwirq >> msi_data->ibs_shift) & MSI_IBS_MASK);
 180 }
 181
 182 static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
 183 {
 184         struct pci_controller *hose = pci_bus_to_host(pdev->bus);
 185         struct device_node *np;
 186         phandle phandle = 0;
 187         int rc, hwirq = -ENOMEM;
 188         unsigned int virq;
 189         struct msi_desc *entry;
 190         struct msi_msg msg;
 191         struct fsl_msi *msi_data;
 192
 193         if (type == PCI_CAP_ID_MSI) {
 194                 /*
 195                  * MPIC version 2.0 has erratum PIC1. For now MSI
 196                  * could not work. So check to prevent MSI from
 197                  * being used on the board with this erratum.
 198                  */
 199                 list_for_each_entry(msi_data, &msi_head, list)
 200                         if (msi_data->feature & MSI_HW_ERRATA_ENDIAN)
 201                                 return -EINVAL;
 202         }
 203
 204         /*
 205          * If the PCI node has an fsl,msi property, then we need to use it
 206          * to find the specific MSI.
 207          */
 208         np = of_parse_phandle(hose->dn, "fsl,msi", 0);
 209         if (np) {
 210                 if (of_device_is_compatible(np, "fsl,mpic-msi") ||
 211                     of_device_is_compatible(np, "fsl,vmpic-msi") ||
 212                     of_device_is_compatible(np, "fsl,vmpic-msi-v4.3"))
 213                         phandle = np->phandle;
 214                 else {
 215                         dev_err(&pdev->dev,
 216                                 "node %s has an invalid fsl,msi phandle %u\n",
 217                                 hose->dn->full_name, np->phandle);
 218                         return -EINVAL;
 219                 }
 220         }
 221
 222         list_for_each_entry(entry, &pdev->msi_list, list) {
 223                 /*
 224                  * Loop over all the MSI devices until we find one that has an
 225                  * available interrupt.
 226                  */
 227                 list_for_each_entry(msi_data, &msi_head, list) {
 228                         /*
 229                          * If the PCI node has an fsl,msi property, then we
 230                          * restrict our search to the corresponding MSI node.
 231                          * The simplest way is to skip over MSI nodes with the
 232                          * wrong phandle. Under the Freescale hypervisor, this
 233                          * has the additional benefit of skipping over MSI
 234                          * nodes that are not mapped in the PAMU.
 235                          */
 236                         if (phandle && (phandle != msi_data->phandle))
 237                                 continue;
 238
 239                         hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
 240                         if (hwirq >= 0)
 241                                 break;
 242                 }
 243
 244                 if (hwirq < 0) {
 245                         rc = hwirq;
 246                         dev_err(&pdev->dev, "could not allocate MSI interrupt\n");
 247                         goto out_free;
 248                 }
 249
 250                 virq = irq_create_mapping(msi_data->irqhost, hwirq);
 251
 252                 if (virq == NO_IRQ) {
 253                         dev_err(&pdev->dev, "fail mapping hwirq %i\n", hwirq);
 254                         msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
 255                         rc = -ENOSPC;
 256                         goto out_free;
 257                 }
 258                 /* chip_data is msi_data via host->hostdata in host->map() */
 259                 irq_set_msi_desc(virq, entry);
 260
 261                 fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
 262                 pci_write_msi_msg(virq, &msg);
 263         }
 264         return 0;
 265
 266 out_free:
 267         /* free by the caller of this function */
 268         return rc;
 269 }
 270
 271 static irqreturn_t fsl_msi_cascade(int irq, void *data)
 272 {
 273         unsigned int cascade_irq;
 274         struct fsl_msi *msi_data;
 275         int msir_index = -1;
 276         u32 msir_value = 0;
 277         u32 intr_index;
 278         u32 have_shift = 0;
 279         struct fsl_msi_cascade_data *cascade_data = data;
 280         irqreturn_t ret = IRQ_NONE;
 281
 282         msi_data = cascade_data->msi_data;
 283
 284         msir_index = cascade_data->index;
 285
 286         if (msir_index >= NR_MSI_REG_MAX)
 287                 cascade_irq = NO_IRQ;
 288
 289         switch (msi_data->feature & FSL_PIC_IP_MASK) {
 290         case FSL_PIC_IP_MPIC:
 291                 msir_value = fsl_msi_read(msi_data->msi_regs,
 292                         msir_index * 0x10);
 293                 break;
 294         case FSL_PIC_IP_IPIC:
 295                 msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
 296                 break;
 297 #ifdef CONFIG_EPAPR_PARAVIRT
 298         case FSL_PIC_IP_VMPIC: {
 299                 unsigned int ret;
 300                 ret = fh_vmpic_get_msir(virq_to_hw(irq), &msir_value);
 301                 if (ret) {
 302                         pr_err("fsl-msi: fh_vmpic_get_msir() failed for "
 303                                "irq %u (ret=%u)\n", irq, ret);
 304                         msir_value = 0;
 305                 }
 306                 break;
 307         }
 308 #endif
 309         }
 310
 311         while (msir_value) {
 312                 intr_index = ffs(msir_value) - 1;
 313
 314                 cascade_irq = irq_linear_revmap(msi_data->irqhost,
 315                                 msi_hwirq(msi_data, msir_index,
 316                                           intr_index + have_shift));
 317                 if (cascade_irq != NO_IRQ) {
 318                         generic_handle_irq(cascade_irq);
 319                         ret = IRQ_HANDLED;
 320                 }
 321                 have_shift += intr_index + 1;
 322                 msir_value = msir_value >> (intr_index + 1);
 323         }
 324
 325         return ret;
 326 }
 327
 328 static int fsl_of_msi_remove(struct platform_device *ofdev)
 329 {
 330         struct fsl_msi *msi = platform_get_drvdata(ofdev);
 331         int virq, i;
 332
 333         if (msi->list.prev != NULL)
 334                 list_del(&msi->list);
 335         for (i = 0; i < NR_MSI_REG_MAX; i++) {
 336                 if (msi->cascade_array[i]) {
 337                         virq = msi->cascade_array[i]->virq;
 338
 339                         BUG_ON(virq == NO_IRQ);
 340
 341                         free_irq(virq, msi->cascade_array[i]);
 342                         kfree(msi->cascade_array[i]);
 343                         irq_dispose_mapping(virq);
 344                 }
 345         }
 346         if (msi->bitmap.bitmap)
 347                 msi_bitmap_free(&msi->bitmap);
 348         if ((msi->feature & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC)
 349                 iounmap(msi->msi_regs);
 350         kfree(msi);
 351
 352         return 0;
 353 }
 354
 355 static struct lock_class_key fsl_msi_irq_class;
 356
 357 static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
 358                                int offset, int irq_index)
 359 {
 360         struct fsl_msi_cascade_data *cascade_data = NULL;
 361         int virt_msir, i, ret;
 362
 363         virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index);
 364         if (virt_msir == NO_IRQ) {
 365                 dev_err(&dev->dev, "%s: Cannot translate IRQ index %d\n",
 366                         __func__, irq_index);
 367                 return 0;
 368         }
 369
 370         cascade_data = kzalloc(sizeof(struct fsl_msi_cascade_data), GFP_KERNEL);
 371         if (!cascade_data) {
 372                 dev_err(&dev->dev, "No memory for MSI cascade data\n");
 373                 return -ENOMEM;
 374         }
 375         irq_set_lockdep_class(virt_msir, &fsl_msi_irq_class);
 376         cascade_data->index = offset;
 377         cascade_data->msi_data = msi;
 378         cascade_data->virq = virt_msir;
 379         msi->cascade_array[irq_index] = cascade_data;
 380
 381         ret = request_irq(virt_msir, fsl_msi_cascade, IRQF_NO_THREAD,
 382                           "fsl-msi-cascade", cascade_data);
 383         if (ret) {
 384                 dev_err(&dev->dev, "failed to request_irq(%d), ret = %d\n",
 385                         virt_msir, ret);
 386                 return ret;
 387         }
 388
 389         /* Release the hwirqs corresponding to this MSI register */
 390         for (i = 0; i < IRQS_PER_MSI_REG; i++)
 391                 msi_bitmap_free_hwirqs(&msi->bitmap,
 392                                        msi_hwirq(msi, offset, i), 1);
 393
 394         return 0;
 395 }
 396
 397 static const struct of_device_id fsl_of_msi_ids[];
 398 static int fsl_of_msi_probe(struct platform_device *dev)
 399 {
 400         const struct of_device_id *match;
 401         struct fsl_msi *msi;
 402         struct resource res, msiir;
 403         int err, i, j, irq_index, count;
 404         const u32 *p;
 405         const struct fsl_msi_feature *features;
 406         int len;
 407         u32 offset;
 408
 409         match = of_match_device(fsl_of_msi_ids, &dev->dev);
 410         if (!match)
 411                 return -EINVAL;
 412         features = match->data;
 413
 414         printk(KERN_DEBUG "Setting up Freescale MSI support\n");
 415
 416         msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
 417         if (!msi) {
 418                 dev_err(&dev->dev, "No memory for MSI structure\n");
 419                 return -ENOMEM;
 420         }
 421         platform_set_drvdata(dev, msi);
 422
 423         msi->irqhost = irq_domain_add_linear(dev->dev.of_node,
 424                                       NR_MSI_IRQS_MAX, &fsl_msi_host_ops, msi);
 425
 426         if (msi->irqhost == NULL) {
 427                 dev_err(&dev->dev, "No memory for MSI irqhost\n");
 428                 err = -ENOMEM;
 429                 goto error_out;
 430         }
 431
 432         /*
 433          * Under the Freescale hypervisor, the msi nodes don't have a 'reg'
 434          * property.  Instead, we use hypercalls to access the MSI.
 435          */
 436         if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC) {
 437                 err = of_address_to_resource(dev->dev.of_node, 0, &res);
 438                 if (err) {
 439                         dev_err(&dev->dev, "invalid resource for node %s\n",
 440                                 dev->dev.of_node->full_name);
 441                         goto error_out;
 442                 }
 443
 444                 msi->msi_regs = ioremap(res.start, resource_size(&res));
 445                 if (!msi->msi_regs) {
 446                         err = -ENOMEM;
 447                         dev_err(&dev->dev, "could not map node %s\n",
 448                                 dev->dev.of_node->full_name);
 449                         goto error_out;
 450                 }
 451                 msi->msiir_offset =
 452                         features->msiir_offset + (res.start & 0xfffff);
 453
 454                 /*
 455                  * First read the MSIIR/MSIIR1 offset from dts
 456                  * On failure use the hardcode MSIIR offset
 457                  */
 458                 if (of_address_to_resource(dev->dev.of_node, 1, &msiir))
 459                         msi->msiir_offset = features->msiir_offset +
 460                                             (res.start & MSIIR_OFFSET_MASK);
 461                 else
 462                         msi->msiir_offset = msiir.start & MSIIR_OFFSET_MASK;
 463         }
 464
 465         msi->feature = features->fsl_pic_ip;
 466
 467         /* For erratum PIC1 on MPIC version 2.0*/
 468         if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) == FSL_PIC_IP_MPIC
 469                         && (fsl_mpic_primary_get_version() == 0x0200))
 470                 msi->feature |= MSI_HW_ERRATA_ENDIAN;
 471
 472         /*
 473          * Remember the phandle, so that we can match with any PCI nodes
 474          * that have an "fsl,msi" property.
 475          */
 476         msi->phandle = dev->dev.of_node->phandle;
 477
 478         err = fsl_msi_init_allocator(msi);
 479         if (err) {
 480                 dev_err(&dev->dev, "Error allocating MSI bitmap\n");
 481                 goto error_out;
 482         }
 483
 484         p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
 485
 486         if (of_device_is_compatible(dev->dev.of_node, "fsl,mpic-msi-v4.3") ||
 487             of_device_is_compatible(dev->dev.of_node, "fsl,vmpic-msi-v4.3")) {
 488                 msi->srs_shift = MSIIR1_SRS_SHIFT;
 489                 msi->ibs_shift = MSIIR1_IBS_SHIFT;
 490                 if (p)
 491                         dev_warn(&dev->dev, "%s: dose not support msi-available-ranges property\n",
 492                                 __func__);
 493
 494                 for (irq_index = 0; irq_index < NR_MSI_REG_MSIIR1;
 495                      irq_index++) {
 496                         err = fsl_msi_setup_hwirq(msi, dev,
 497                                                   irq_index, irq_index);
 498                         if (err)
 499                                 goto error_out;
 500                 }
 501         } else {
 502                 static const u32 all_avail[] =
 503                         { 0, NR_MSI_REG_MSIIR * IRQS_PER_MSI_REG };
 504
 505                 msi->srs_shift = MSIIR_SRS_SHIFT;
 506                 msi->ibs_shift = MSIIR_IBS_SHIFT;
 507
 508                 if (p && len % (2 * sizeof(u32)) != 0) {
 509                         dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n",
 510                                 __func__);
 511                         err = -EINVAL;
 512                         goto error_out;
 513                 }
 514
 515                 if (!p) {
 516                         p = all_avail;
 517                         len = sizeof(all_avail);
 518                 }
 519
 520                 for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) {
 521                         if (p[i * 2] % IRQS_PER_MSI_REG ||
 522                             p[i * 2 + 1] % IRQS_PER_MSI_REG) {
 523                                 pr_warn("%s: %s: msi available range of %u at %u is not IRQ-aligned\n",
 524                                        __func__, dev->dev.of_node->full_name,
 525                                        p[i * 2 + 1], p[i * 2]);
 526                                 err = -EINVAL;
 527                                 goto error_out;
 528                         }
 529
 530                         offset = p[i * 2] / IRQS_PER_MSI_REG;
 531                         count = p[i * 2 + 1] / IRQS_PER_MSI_REG;
 532
 533                         for (j = 0; j < count; j++, irq_index++) {
 534                                 err = fsl_msi_setup_hwirq(msi, dev, offset + j,
 535                                                           irq_index);
 536                                 if (err)
 537                                         goto error_out;
 538                         }
 539                 }
 540         }
 541
 542         list_add_tail(&msi->list, &msi_head);
 543
 544         /* The multiple setting ppc_md.setup_msi_irqs will not harm things */
 545         if (!ppc_md.setup_msi_irqs) {
 546                 ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
 547                 ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
 548         } else if (ppc_md.setup_msi_irqs != fsl_setup_msi_irqs) {
 549                 dev_err(&dev->dev, "Different MSI driver already installed!\n");
 550                 err = -ENODEV;
 551                 goto error_out;
 552         }
 553         return 0;
 554 error_out:
 555         fsl_of_msi_remove(dev);
 556         return err;
 557 }
 558
 559 static const struct fsl_msi_feature mpic_msi_feature = {
 560         .fsl_pic_ip = FSL_PIC_IP_MPIC,
 561         .msiir_offset = 0x140,
 562 };
 563
 564 static const struct fsl_msi_feature ipic_msi_feature = {
 565         .fsl_pic_ip = FSL_PIC_IP_IPIC,
 566         .msiir_offset = 0x38,
 567 };
 568
 569 static const struct fsl_msi_feature vmpic_msi_feature = {
 570         .fsl_pic_ip = FSL_PIC_IP_VMPIC,
 571         .msiir_offset = 0,
 572 };
 573
 574 static const struct of_device_id fsl_of_msi_ids[] = {
 575         {
 576                 .compatible = "fsl,mpic-msi",
 577                 .data = &mpic_msi_feature,
 578         },
 579         {
 580                 .compatible = "fsl,mpic-msi-v4.3",
 581                 .data = &mpic_msi_feature,
 582         },
 583         {
 584                 .compatible = "fsl,ipic-msi",
 585                 .data = &ipic_msi_feature,
 586         },
 587 #ifdef CONFIG_EPAPR_PARAVIRT
 588         {
 589                 .compatible = "fsl,vmpic-msi",
 590                 .data = &vmpic_msi_feature,
 591         },
 592         {
 593                 .compatible = "fsl,vmpic-msi-v4.3",
 594                 .data = &vmpic_msi_feature,
 595         },
 596 #endif
 597         {}
 598 };
 599
 600 static struct platform_driver fsl_of_msi_driver = {
 601         .driver = {
 602                 .name = "fsl-msi",
 603                 .of_match_table = fsl_of_msi_ids,
 604         },
 605         .probe = fsl_of_msi_probe,
 606         .remove = fsl_of_msi_remove,
 607 };
 608
 609 static __init int fsl_of_msi_init(void)
 610 {
 611         return platform_driver_register(&fsl_of_msi_driver);
 612 }
 613
 614 subsys_initcall(fsl_of_msi_init);