2 * MPC83xx/85xx/86xx PCI/PCIE support routing.
4 * Copyright 2007-2012 Freescale Semiconductor, Inc.
5 * Copyright 2008-2009 MontaVista Software, Inc.
7 * Initial author: Xianghua Xiao <x.xiao@freescale.com>
8 * Recode: ZHANG WEI <wei.zhang@freescale.com>
9 * Rewrite the routing for Frescale PCI and PCI Express
10 * Roy Zang <tie-fei.zang@freescale.com>
11 * MPC83xx PCI-Express support:
12 * Tony Li <tony.li@freescale.com>
13 * Anton Vorontsov <avorontsov@ru.mvista.com>
15 * This program is free software; you can redistribute it and/or modify it
16 * under the terms of the GNU General Public License as published by the
17 * Free Software Foundation; either version 2 of the License, or (at your
18 * option) any later version.
20 #include <linux/kernel.h>
21 #include <linux/pci.h>
22 #include <linux/delay.h>
23 #include <linux/string.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/memblock.h>
27 #include <linux/log2.h>
28 #include <linux/slab.h>
29 #include <linux/suspend.h>
30 #include <linux/syscore_ops.h>
31 #include <linux/uaccess.h>
35 #include <asm/pci-bridge.h>
36 #include <asm/ppc-pci.h>
37 #include <asm/machdep.h>
38 #include <asm/disassemble.h>
39 #include <asm/ppc-opcode.h>
40 #include <sysdev/fsl_soc.h>
41 #include <sysdev/fsl_pci.h>
43 static int fsl_pcie_bus_fixup
, is_mpc83xx_pci
;
45 static void quirk_fsl_pcie_early(struct pci_dev
*dev
)
49 /* if we aren't a PCIe don't bother */
50 if (!pci_is_pcie(dev
))
53 /* if we aren't in host mode don't bother */
54 pci_read_config_byte(dev
, PCI_HEADER_TYPE
, &hdr_type
);
55 if ((hdr_type
& 0x7f) != PCI_HEADER_TYPE_BRIDGE
)
58 dev
->class = PCI_CLASS_BRIDGE_PCI
<< 8;
59 fsl_pcie_bus_fixup
= 1;
63 static int fsl_indirect_read_config(struct pci_bus
*, unsigned int,
66 static int fsl_pcie_check_link(struct pci_controller
*hose
)
70 if (hose
->indirect_type
& PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK
) {
71 if (hose
->ops
->read
== fsl_indirect_read_config
)
72 __indirect_read_config(hose
, hose
->first_busno
, 0,
75 early_read_config_dword(hose
, 0, 0, PCIE_LTSSM
, &val
);
76 if (val
< PCIE_LTSSM_L0
)
79 struct ccsr_pci __iomem
*pci
= hose
->private_data
;
80 /* for PCIe IP rev 3.0 or greater use CSR0 for link state */
81 val
= (in_be32(&pci
->pex_csr0
) & PEX_CSR0_LTSSM_MASK
)
82 >> PEX_CSR0_LTSSM_SHIFT
;
83 if (val
!= PEX_CSR0_LTSSM_L0
)
90 static int fsl_indirect_read_config(struct pci_bus
*bus
, unsigned int devfn
,
91 int offset
, int len
, u32
*val
)
93 struct pci_controller
*hose
= pci_bus_to_host(bus
);
95 if (fsl_pcie_check_link(hose
))
96 hose
->indirect_type
|= PPC_INDIRECT_TYPE_NO_PCIE_LINK
;
98 hose
->indirect_type
&= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK
;
100 return indirect_read_config(bus
, devfn
, offset
, len
, val
);
103 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
105 static struct pci_ops fsl_indirect_pcie_ops
=
107 .read
= fsl_indirect_read_config
,
108 .write
= indirect_write_config
,
111 #define MAX_PHYS_ADDR_BITS 40
112 static u64 pci64_dma_offset
= 1ull << MAX_PHYS_ADDR_BITS
;
114 static int fsl_pci_dma_set_mask(struct device
*dev
, u64 dma_mask
)
116 if (!dev
->dma_mask
|| !dma_supported(dev
, dma_mask
))
120 * Fixup PCI devices that are able to DMA to above the physical
121 * address width of the SoC such that we can address any internal
122 * SoC address from across PCI if needed
124 if ((dev_is_pci(dev
)) &&
125 dma_mask
>= DMA_BIT_MASK(MAX_PHYS_ADDR_BITS
)) {
126 set_dma_ops(dev
, &dma_direct_ops
);
127 set_dma_offset(dev
, pci64_dma_offset
);
130 *dev
->dma_mask
= dma_mask
;
134 static int setup_one_atmu(struct ccsr_pci __iomem
*pci
,
135 unsigned int index
, const struct resource
*res
,
136 resource_size_t offset
)
138 resource_size_t pci_addr
= res
->start
- offset
;
139 resource_size_t phys_addr
= res
->start
;
140 resource_size_t size
= resource_size(res
);
141 u32 flags
= 0x80044000; /* enable & mem R/W */
144 pr_debug("PCI MEM resource start 0x%016llx, size 0x%016llx.\n",
145 (u64
)res
->start
, (u64
)size
);
147 if (res
->flags
& IORESOURCE_PREFETCH
)
148 flags
|= 0x10000000; /* enable relaxed ordering */
150 for (i
= 0; size
> 0; i
++) {
151 unsigned int bits
= min_t(u32
, ilog2(size
),
152 __ffs(pci_addr
| phys_addr
));
157 out_be32(&pci
->pow
[index
+ i
].potar
, pci_addr
>> 12);
158 out_be32(&pci
->pow
[index
+ i
].potear
, (u64
)pci_addr
>> 44);
159 out_be32(&pci
->pow
[index
+ i
].powbar
, phys_addr
>> 12);
160 out_be32(&pci
->pow
[index
+ i
].powar
, flags
| (bits
- 1));
162 pci_addr
+= (resource_size_t
)1U << bits
;
163 phys_addr
+= (resource_size_t
)1U << bits
;
164 size
-= (resource_size_t
)1U << bits
;
170 /* atmu setup for fsl pci/pcie controller */
171 static void setup_pci_atmu(struct pci_controller
*hose
)
173 struct ccsr_pci __iomem
*pci
= hose
->private_data
;
174 int i
, j
, n
, mem_log
, win_idx
= 3, start_idx
= 1, end_idx
= 4;
175 u64 mem
, sz
, paddr_hi
= 0;
176 u64 offset
= 0, paddr_lo
= ULLONG_MAX
;
177 u32 pcicsrbar
= 0, pcicsrbar_sz
;
178 u32 piwar
= PIWAR_EN
| PIWAR_PF
| PIWAR_TGI_LOCAL
|
179 PIWAR_READ_SNOOP
| PIWAR_WRITE_SNOOP
;
180 const char *name
= hose
->dn
->full_name
;
184 if (early_find_capability(hose
, 0, 0, PCI_CAP_ID_EXP
)) {
185 if (in_be32(&pci
->block_rev1
) >= PCIE_IP_REV_2_2
) {
192 /* Disable all windows (except powar0 since it's ignored) */
193 for(i
= 1; i
< 5; i
++)
194 out_be32(&pci
->pow
[i
].powar
, 0);
195 for (i
= start_idx
; i
< end_idx
; i
++)
196 out_be32(&pci
->piw
[i
].piwar
, 0);
198 /* Setup outbound MEM window */
199 for(i
= 0, j
= 1; i
< 3; i
++) {
200 if (!(hose
->mem_resources
[i
].flags
& IORESOURCE_MEM
))
203 paddr_lo
= min(paddr_lo
, (u64
)hose
->mem_resources
[i
].start
);
204 paddr_hi
= max(paddr_hi
, (u64
)hose
->mem_resources
[i
].end
);
206 /* We assume all memory resources have the same offset */
207 offset
= hose
->mem_offset
[i
];
208 n
= setup_one_atmu(pci
, j
, &hose
->mem_resources
[i
], offset
);
210 if (n
< 0 || j
>= 5) {
211 pr_err("Ran out of outbound PCI ATMUs for resource %d!\n", i
);
212 hose
->mem_resources
[i
].flags
|= IORESOURCE_DISABLED
;
217 /* Setup outbound IO window */
218 if (hose
->io_resource
.flags
& IORESOURCE_IO
) {
220 pr_err("Ran out of outbound PCI ATMUs for IO resource\n");
222 pr_debug("PCI IO resource start 0x%016llx, size 0x%016llx, "
223 "phy base 0x%016llx.\n",
224 (u64
)hose
->io_resource
.start
,
225 (u64
)resource_size(&hose
->io_resource
),
226 (u64
)hose
->io_base_phys
);
227 out_be32(&pci
->pow
[j
].potar
, (hose
->io_resource
.start
>> 12));
228 out_be32(&pci
->pow
[j
].potear
, 0);
229 out_be32(&pci
->pow
[j
].powbar
, (hose
->io_base_phys
>> 12));
231 out_be32(&pci
->pow
[j
].powar
, 0x80088000
232 | (ilog2(hose
->io_resource
.end
233 - hose
->io_resource
.start
+ 1) - 1));
237 /* convert to pci address space */
241 if (paddr_hi
== paddr_lo
) {
242 pr_err("%s: No outbound window space\n", name
);
247 pr_err("%s: No space for inbound window\n", name
);
251 /* setup PCSRBAR/PEXCSRBAR */
252 early_write_config_dword(hose
, 0, 0, PCI_BASE_ADDRESS_0
, 0xffffffff);
253 early_read_config_dword(hose
, 0, 0, PCI_BASE_ADDRESS_0
, &pcicsrbar_sz
);
254 pcicsrbar_sz
= ~pcicsrbar_sz
+ 1;
256 if (paddr_hi
< (0x100000000ull
- pcicsrbar_sz
) ||
257 (paddr_lo
> 0x100000000ull
))
258 pcicsrbar
= 0x100000000ull
- pcicsrbar_sz
;
260 pcicsrbar
= (paddr_lo
- pcicsrbar_sz
) & -pcicsrbar_sz
;
261 early_write_config_dword(hose
, 0, 0, PCI_BASE_ADDRESS_0
, pcicsrbar
);
263 paddr_lo
= min(paddr_lo
, (u64
)pcicsrbar
);
265 pr_info("%s: PCICSRBAR @ 0x%x\n", name
, pcicsrbar
);
267 /* Setup inbound mem window */
268 mem
= memblock_end_of_DRAM();
271 * The msi-address-64 property, if it exists, indicates the physical
272 * address of the MSIIR register. Normally, this register is located
273 * inside CCSR, so the ATMU that covers all of CCSR is used. But if
274 * this property exists, then we normally need to create a new ATMU
275 * for it. For now, however, we cheat. The only entity that creates
276 * this property is the Freescale hypervisor, and the address is
277 * specified in the partition configuration. Typically, the address
278 * is located in the page immediately after the end of DDR. If so, we
279 * can avoid allocating a new ATMU by extending the DDR ATMU by one
282 reg
= of_get_property(hose
->dn
, "msi-address-64", &len
);
283 if (reg
&& (len
== sizeof(u64
))) {
284 u64 address
= be64_to_cpup(reg
);
286 if ((address
>= mem
) && (address
< (mem
+ PAGE_SIZE
))) {
287 pr_info("%s: extending DDR ATMU to cover MSIIR", name
);
290 /* TODO: Create a new ATMU for MSIIR */
291 pr_warn("%s: msi-address-64 address of %llx is "
292 "unsupported\n", name
, address
);
296 sz
= min(mem
, paddr_lo
);
299 /* PCIe can overmap inbound & outbound since RX & TX are separated */
300 if (early_find_capability(hose
, 0, 0, PCI_CAP_ID_EXP
)) {
301 /* Size window to exact size if power-of-two or one size up */
302 if ((1ull << mem_log
) != mem
) {
304 if ((1ull << mem_log
) > mem
)
305 pr_info("%s: Setting PCI inbound window "
306 "greater than memory size\n", name
);
309 piwar
|= ((mem_log
- 1) & PIWAR_SZ_MASK
);
311 /* Setup inbound memory window */
312 out_be32(&pci
->piw
[win_idx
].pitar
, 0x00000000);
313 out_be32(&pci
->piw
[win_idx
].piwbar
, 0x00000000);
314 out_be32(&pci
->piw
[win_idx
].piwar
, piwar
);
317 hose
->dma_window_base_cur
= 0x00000000;
318 hose
->dma_window_size
= (resource_size_t
)sz
;
321 * if we have >4G of memory setup second PCI inbound window to
322 * let devices that are 64-bit address capable to work w/o
323 * SWIOTLB and access the full range of memory
326 mem_log
= ilog2(mem
);
328 /* Size window up if we dont fit in exact power-of-2 */
329 if ((1ull << mem_log
) != mem
)
332 piwar
= (piwar
& ~PIWAR_SZ_MASK
) | (mem_log
- 1);
334 /* Setup inbound memory window */
335 out_be32(&pci
->piw
[win_idx
].pitar
, 0x00000000);
336 out_be32(&pci
->piw
[win_idx
].piwbear
,
337 pci64_dma_offset
>> 44);
338 out_be32(&pci
->piw
[win_idx
].piwbar
,
339 pci64_dma_offset
>> 12);
340 out_be32(&pci
->piw
[win_idx
].piwar
, piwar
);
343 * install our own dma_set_mask handler to fixup dma_ops
346 ppc_md
.dma_set_mask
= fsl_pci_dma_set_mask
;
348 pr_info("%s: Setup 64-bit PCI DMA window\n", name
);
353 /* Setup inbound memory window */
354 out_be32(&pci
->piw
[win_idx
].pitar
, paddr
>> 12);
355 out_be32(&pci
->piw
[win_idx
].piwbar
, paddr
>> 12);
356 out_be32(&pci
->piw
[win_idx
].piwar
, (piwar
| (mem_log
- 1)));
359 paddr
+= 1ull << mem_log
;
360 sz
-= 1ull << mem_log
;
364 piwar
|= (mem_log
- 1);
366 out_be32(&pci
->piw
[win_idx
].pitar
, paddr
>> 12);
367 out_be32(&pci
->piw
[win_idx
].piwbar
, paddr
>> 12);
368 out_be32(&pci
->piw
[win_idx
].piwar
, piwar
);
371 paddr
+= 1ull << mem_log
;
374 hose
->dma_window_base_cur
= 0x00000000;
375 hose
->dma_window_size
= (resource_size_t
)paddr
;
378 if (hose
->dma_window_size
< mem
) {
379 #ifdef CONFIG_SWIOTLB
380 ppc_swiotlb_enable
= 1;
382 pr_err("%s: ERROR: Memory size exceeds PCI ATMU ability to "
383 "map - enable CONFIG_SWIOTLB to avoid dma errors.\n",
386 /* adjusting outbound windows could reclaim space in mem map */
387 if (paddr_hi
< 0xffffffffull
)
388 pr_warning("%s: WARNING: Outbound window cfg leaves "
389 "gaps in memory map. Adjusting the memory map "
390 "could reduce unnecessary bounce buffering.\n",
393 pr_info("%s: DMA window size is 0x%llx\n", name
,
394 (u64
)hose
->dma_window_size
);
398 static void __init
setup_pci_cmd(struct pci_controller
*hose
)
403 early_read_config_word(hose
, 0, 0, PCI_COMMAND
, &cmd
);
404 cmd
|= PCI_COMMAND_SERR
| PCI_COMMAND_MASTER
| PCI_COMMAND_MEMORY
406 early_write_config_word(hose
, 0, 0, PCI_COMMAND
, cmd
);
408 cap_x
= early_find_capability(hose
, 0, 0, PCI_CAP_ID_PCIX
);
410 int pci_x_cmd
= cap_x
+ PCI_X_CMD
;
411 cmd
= PCI_X_CMD_MAX_SPLIT
| PCI_X_CMD_MAX_READ
412 | PCI_X_CMD_ERO
| PCI_X_CMD_DPERR_E
;
413 early_write_config_word(hose
, 0, 0, pci_x_cmd
, cmd
);
415 early_write_config_byte(hose
, 0, 0, PCI_LATENCY_TIMER
, 0x80);
419 void fsl_pcibios_fixup_bus(struct pci_bus
*bus
)
421 struct pci_controller
*hose
= pci_bus_to_host(bus
);
422 int i
, is_pcie
= 0, no_link
;
424 /* The root complex bridge comes up with bogus resources,
425 * we copy the PHB ones in.
427 * With the current generic PCI code, the PHB bus no longer
428 * has bus->resource[0..4] set, so things are a bit more
432 if (fsl_pcie_bus_fixup
)
433 is_pcie
= early_find_capability(hose
, 0, 0, PCI_CAP_ID_EXP
);
434 no_link
= !!(hose
->indirect_type
& PPC_INDIRECT_TYPE_NO_PCIE_LINK
);
436 if (bus
->parent
== hose
->bus
&& (is_pcie
|| no_link
)) {
437 for (i
= 0; i
< PCI_BRIDGE_RESOURCE_NUM
; ++i
) {
438 struct resource
*res
= bus
->resource
[i
];
439 struct resource
*par
;
444 par
= &hose
->io_resource
;
446 par
= &hose
->mem_resources
[i
-1];
449 res
->start
= par
? par
->start
: 0;
450 res
->end
= par
? par
->end
: 0;
451 res
->flags
= par
? par
->flags
: 0;
456 int fsl_add_bridge(struct platform_device
*pdev
, int is_primary
)
459 struct pci_controller
*hose
;
460 struct resource rsrc
;
461 const int *bus_range
;
463 struct device_node
*dev
;
464 struct ccsr_pci __iomem
*pci
;
466 dev
= pdev
->dev
.of_node
;
468 if (!of_device_is_available(dev
)) {
469 pr_warning("%s: disabled\n", dev
->full_name
);
473 pr_debug("Adding PCI host bridge %s\n", dev
->full_name
);
475 /* Fetch host bridge registers address */
476 if (of_address_to_resource(dev
, 0, &rsrc
)) {
477 printk(KERN_WARNING
"Can't get pci register base!");
481 /* Get bus range if any */
482 bus_range
= of_get_property(dev
, "bus-range", &len
);
483 if (bus_range
== NULL
|| len
< 2 * sizeof(int))
484 printk(KERN_WARNING
"Can't get bus-range for %s, assume"
485 " bus 0\n", dev
->full_name
);
487 pci_add_flags(PCI_REASSIGN_ALL_BUS
);
488 hose
= pcibios_alloc_controller(dev
);
492 /* set platform device as the parent */
493 hose
->parent
= &pdev
->dev
;
494 hose
->first_busno
= bus_range
? bus_range
[0] : 0x0;
495 hose
->last_busno
= bus_range
? bus_range
[1] : 0xff;
497 pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
498 (u64
)rsrc
.start
, (u64
)resource_size(&rsrc
));
500 pci
= hose
->private_data
= ioremap(rsrc
.start
, resource_size(&rsrc
));
501 if (!hose
->private_data
)
504 setup_indirect_pci(hose
, rsrc
.start
, rsrc
.start
+ 0x4,
505 PPC_INDIRECT_TYPE_BIG_ENDIAN
);
507 if (in_be32(&pci
->block_rev1
) < PCIE_IP_REV_3_0
)
508 hose
->indirect_type
|= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK
;
510 if (early_find_capability(hose
, 0, 0, PCI_CAP_ID_EXP
)) {
511 /* use fsl_indirect_read_config for PCIe */
512 hose
->ops
= &fsl_indirect_pcie_ops
;
513 /* For PCIE read HEADER_TYPE to identify controler mode */
514 early_read_config_byte(hose
, 0, 0, PCI_HEADER_TYPE
, &hdr_type
);
515 if ((hdr_type
& 0x7f) != PCI_HEADER_TYPE_BRIDGE
)
519 /* For PCI read PROG to identify controller mode */
520 early_read_config_byte(hose
, 0, 0, PCI_CLASS_PROG
, &progif
);
522 !of_property_read_bool(dev
, "fsl,pci-agent-force-enum"))
528 /* check PCI express link status */
529 if (early_find_capability(hose
, 0, 0, PCI_CAP_ID_EXP
)) {
530 hose
->indirect_type
|= PPC_INDIRECT_TYPE_EXT_REG
|
531 PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS
;
532 if (fsl_pcie_check_link(hose
))
533 hose
->indirect_type
|= PPC_INDIRECT_TYPE_NO_PCIE_LINK
;
536 printk(KERN_INFO
"Found FSL PCI host bridge at 0x%016llx. "
537 "Firmware bus number: %d->%d\n",
538 (unsigned long long)rsrc
.start
, hose
->first_busno
,
541 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
542 hose
, hose
->cfg_addr
, hose
->cfg_data
);
544 /* Interpret the "ranges" property */
545 /* This also maps the I/O region and sets isa_io/mem_base */
546 pci_process_bridge_OF_ranges(hose
, dev
, is_primary
);
548 /* Setup PEX window registers */
549 setup_pci_atmu(hose
);
554 iounmap(hose
->private_data
);
555 /* unmap cfg_data & cfg_addr separately if not on same page */
556 if (((unsigned long)hose
->cfg_data
& PAGE_MASK
) !=
557 ((unsigned long)hose
->cfg_addr
& PAGE_MASK
))
558 iounmap(hose
->cfg_data
);
559 iounmap(hose
->cfg_addr
);
560 pcibios_free_controller(hose
);
563 #endif /* CONFIG_FSL_SOC_BOOKE || CONFIG_PPC_86xx */
565 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_FREESCALE
, PCI_ANY_ID
,
566 quirk_fsl_pcie_early
);
568 #if defined(CONFIG_PPC_83xx) || defined(CONFIG_PPC_MPC512x)
569 struct mpc83xx_pcie_priv
{
570 void __iomem
*cfg_type0
;
571 void __iomem
*cfg_type1
;
575 struct pex_inbound_window
{
583 * With the convention of u-boot, the PCIE outbound window 0 serves
584 * as configuration transactions outbound.
586 #define PEX_OUTWIN0_BAR 0xCA4
587 #define PEX_OUTWIN0_TAL 0xCA8
588 #define PEX_OUTWIN0_TAH 0xCAC
589 #define PEX_RC_INWIN_BASE 0xE60
590 #define PEX_RCIWARn_EN 0x1
592 static int mpc83xx_pcie_exclude_device(struct pci_bus
*bus
, unsigned int devfn
)
594 struct pci_controller
*hose
= pci_bus_to_host(bus
);
596 if (hose
->indirect_type
& PPC_INDIRECT_TYPE_NO_PCIE_LINK
)
597 return PCIBIOS_DEVICE_NOT_FOUND
;
599 * Workaround for the HW bug: for Type 0 configure transactions the
600 * PCI-E controller does not check the device number bits and just
601 * assumes that the device number bits are 0.
603 if (bus
->number
== hose
->first_busno
||
604 bus
->primary
== hose
->first_busno
) {
606 return PCIBIOS_DEVICE_NOT_FOUND
;
609 if (ppc_md
.pci_exclude_device
) {
610 if (ppc_md
.pci_exclude_device(hose
, bus
->number
, devfn
))
611 return PCIBIOS_DEVICE_NOT_FOUND
;
614 return PCIBIOS_SUCCESSFUL
;
617 static void __iomem
*mpc83xx_pcie_remap_cfg(struct pci_bus
*bus
,
618 unsigned int devfn
, int offset
)
620 struct pci_controller
*hose
= pci_bus_to_host(bus
);
621 struct mpc83xx_pcie_priv
*pcie
= hose
->dn
->data
;
622 u32 dev_base
= bus
->number
<< 24 | devfn
<< 16;
625 ret
= mpc83xx_pcie_exclude_device(bus
, devfn
);
632 if (bus
->number
== hose
->first_busno
)
633 return pcie
->cfg_type0
+ offset
;
635 if (pcie
->dev_base
== dev_base
)
638 out_le32(pcie
->cfg_type0
+ PEX_OUTWIN0_TAL
, dev_base
);
640 pcie
->dev_base
= dev_base
;
642 return pcie
->cfg_type1
+ offset
;
645 static int mpc83xx_pcie_write_config(struct pci_bus
*bus
, unsigned int devfn
,
646 int offset
, int len
, u32 val
)
648 struct pci_controller
*hose
= pci_bus_to_host(bus
);
650 /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
651 if (offset
== PCI_PRIMARY_BUS
&& bus
->number
== hose
->first_busno
)
654 return pci_generic_config_write(bus
, devfn
, offset
, len
, val
);
657 static struct pci_ops mpc83xx_pcie_ops
= {
658 .map_bus
= mpc83xx_pcie_remap_cfg
,
659 .read
= pci_generic_config_read
,
660 .write
= mpc83xx_pcie_write_config
,
663 static int __init
mpc83xx_pcie_setup(struct pci_controller
*hose
,
664 struct resource
*reg
)
666 struct mpc83xx_pcie_priv
*pcie
;
670 pcie
= zalloc_maybe_bootmem(sizeof(*pcie
), GFP_KERNEL
);
674 pcie
->cfg_type0
= ioremap(reg
->start
, resource_size(reg
));
675 if (!pcie
->cfg_type0
)
678 cfg_bar
= in_le32(pcie
->cfg_type0
+ PEX_OUTWIN0_BAR
);
680 /* PCI-E isn't configured. */
685 pcie
->cfg_type1
= ioremap(cfg_bar
, 0x1000);
686 if (!pcie
->cfg_type1
)
689 WARN_ON(hose
->dn
->data
);
690 hose
->dn
->data
= pcie
;
691 hose
->ops
= &mpc83xx_pcie_ops
;
692 hose
->indirect_type
|= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK
;
694 out_le32(pcie
->cfg_type0
+ PEX_OUTWIN0_TAH
, 0);
695 out_le32(pcie
->cfg_type0
+ PEX_OUTWIN0_TAL
, 0);
697 if (fsl_pcie_check_link(hose
))
698 hose
->indirect_type
|= PPC_INDIRECT_TYPE_NO_PCIE_LINK
;
702 iounmap(pcie
->cfg_type0
);
709 int __init
mpc83xx_add_bridge(struct device_node
*dev
)
713 struct pci_controller
*hose
;
714 struct resource rsrc_reg
;
715 struct resource rsrc_cfg
;
716 const int *bus_range
;
721 if (!of_device_is_available(dev
)) {
722 pr_warning("%s: disabled by the firmware.\n",
726 pr_debug("Adding PCI host bridge %s\n", dev
->full_name
);
728 /* Fetch host bridge registers address */
729 if (of_address_to_resource(dev
, 0, &rsrc_reg
)) {
730 printk(KERN_WARNING
"Can't get pci register base!\n");
734 memset(&rsrc_cfg
, 0, sizeof(rsrc_cfg
));
736 if (of_address_to_resource(dev
, 1, &rsrc_cfg
)) {
738 "No pci config register base in dev tree, "
741 * MPC83xx supports up to two host controllers
742 * one at 0x8500 has config space registers at 0x8300
743 * one at 0x8600 has config space registers at 0x8380
745 if ((rsrc_reg
.start
& 0xfffff) == 0x8500)
746 rsrc_cfg
.start
= (rsrc_reg
.start
& 0xfff00000) + 0x8300;
747 else if ((rsrc_reg
.start
& 0xfffff) == 0x8600)
748 rsrc_cfg
.start
= (rsrc_reg
.start
& 0xfff00000) + 0x8380;
751 * Controller at offset 0x8500 is primary
753 if ((rsrc_reg
.start
& 0xfffff) == 0x8500)
758 /* Get bus range if any */
759 bus_range
= of_get_property(dev
, "bus-range", &len
);
760 if (bus_range
== NULL
|| len
< 2 * sizeof(int)) {
761 printk(KERN_WARNING
"Can't get bus-range for %s, assume"
762 " bus 0\n", dev
->full_name
);
765 pci_add_flags(PCI_REASSIGN_ALL_BUS
);
766 hose
= pcibios_alloc_controller(dev
);
770 hose
->first_busno
= bus_range
? bus_range
[0] : 0;
771 hose
->last_busno
= bus_range
? bus_range
[1] : 0xff;
773 if (of_device_is_compatible(dev
, "fsl,mpc8314-pcie")) {
774 ret
= mpc83xx_pcie_setup(hose
, &rsrc_reg
);
778 setup_indirect_pci(hose
, rsrc_cfg
.start
,
779 rsrc_cfg
.start
+ 4, 0);
782 printk(KERN_INFO
"Found FSL PCI host bridge at 0x%016llx. "
783 "Firmware bus number: %d->%d\n",
784 (unsigned long long)rsrc_reg
.start
, hose
->first_busno
,
787 pr_debug(" ->Hose at 0x%p, cfg_addr=0x%p,cfg_data=0x%p\n",
788 hose
, hose
->cfg_addr
, hose
->cfg_data
);
790 /* Interpret the "ranges" property */
791 /* This also maps the I/O region and sets isa_io/mem_base */
792 pci_process_bridge_OF_ranges(hose
, dev
, primary
);
796 pcibios_free_controller(hose
);
799 #endif /* CONFIG_PPC_83xx */
801 u64
fsl_pci_immrbar_base(struct pci_controller
*hose
)
803 #ifdef CONFIG_PPC_83xx
804 if (is_mpc83xx_pci
) {
805 struct mpc83xx_pcie_priv
*pcie
= hose
->dn
->data
;
806 struct pex_inbound_window
*in
;
809 /* Walk the Root Complex Inbound windows to match IMMR base */
810 in
= pcie
->cfg_type0
+ PEX_RC_INWIN_BASE
;
811 for (i
= 0; i
< 4; i
++) {
812 /* not enabled, skip */
813 if (!(in_le32(&in
[i
].ar
) & PEX_RCIWARn_EN
))
816 if (get_immrbase() == in_le32(&in
[i
].tar
))
817 return (u64
)in_le32(&in
[i
].barh
) << 32 |
818 in_le32(&in
[i
].barl
);
821 printk(KERN_WARNING
"could not find PCI BAR matching IMMR\n");
825 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
826 if (!is_mpc83xx_pci
) {
829 pci_bus_read_config_dword(hose
->bus
,
830 PCI_DEVFN(0, 0), PCI_BASE_ADDRESS_0
, &base
);
833 * For PEXCSRBAR, bit 3-0 indicate prefetchable and
834 * address type. So when getting base address, these
835 * bits should be masked
837 base
&= PCI_BASE_ADDRESS_MEM_MASK
;
847 static int mcheck_handle_load(struct pt_regs
*regs
, u32 inst
)
849 unsigned int rd
, ra
, rb
, d
;
856 switch (get_op(inst
)) {
858 switch (get_xop(inst
)) {
860 case OP_31_XOP_LWBRX
:
861 regs
->gpr
[rd
] = 0xffffffff;
864 case OP_31_XOP_LWZUX
:
865 regs
->gpr
[rd
] = 0xffffffff;
866 regs
->gpr
[ra
] += regs
->gpr
[rb
];
870 regs
->gpr
[rd
] = 0xff;
873 case OP_31_XOP_LBZUX
:
874 regs
->gpr
[rd
] = 0xff;
875 regs
->gpr
[ra
] += regs
->gpr
[rb
];
879 case OP_31_XOP_LHBRX
:
880 regs
->gpr
[rd
] = 0xffff;
883 case OP_31_XOP_LHZUX
:
884 regs
->gpr
[rd
] = 0xffff;
885 regs
->gpr
[ra
] += regs
->gpr
[rb
];
889 regs
->gpr
[rd
] = ~0UL;
892 case OP_31_XOP_LHAUX
:
893 regs
->gpr
[rd
] = ~0UL;
894 regs
->gpr
[ra
] += regs
->gpr
[rb
];
903 regs
->gpr
[rd
] = 0xffffffff;
907 regs
->gpr
[rd
] = 0xffffffff;
908 regs
->gpr
[ra
] += (s16
)d
;
912 regs
->gpr
[rd
] = 0xff;
916 regs
->gpr
[rd
] = 0xff;
917 regs
->gpr
[ra
] += (s16
)d
;
921 regs
->gpr
[rd
] = 0xffff;
925 regs
->gpr
[rd
] = 0xffff;
926 regs
->gpr
[ra
] += (s16
)d
;
930 regs
->gpr
[rd
] = ~0UL;
934 regs
->gpr
[rd
] = ~0UL;
935 regs
->gpr
[ra
] += (s16
)d
;
945 static int is_in_pci_mem_space(phys_addr_t addr
)
947 struct pci_controller
*hose
;
948 struct resource
*res
;
951 list_for_each_entry(hose
, &hose_list
, list_node
) {
952 if (!(hose
->indirect_type
& PPC_INDIRECT_TYPE_EXT_REG
))
955 for (i
= 0; i
< 3; i
++) {
956 res
= &hose
->mem_resources
[i
];
957 if ((res
->flags
& IORESOURCE_MEM
) &&
958 addr
>= res
->start
&& addr
<= res
->end
)
965 int fsl_pci_mcheck_exception(struct pt_regs
*regs
)
969 phys_addr_t addr
= 0;
971 /* Let KVM/QEMU deal with the exception */
972 if (regs
->msr
& MSR_GS
)
975 #ifdef CONFIG_PHYS_64BIT
976 addr
= mfspr(SPRN_MCARU
);
979 addr
+= mfspr(SPRN_MCAR
);
981 if (is_in_pci_mem_space(addr
)) {
982 if (user_mode(regs
)) {
984 ret
= get_user(regs
->nip
, &inst
);
987 ret
= probe_kernel_address(regs
->nip
, inst
);
990 if (mcheck_handle_load(regs
, inst
)) {
1000 #if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
1001 static const struct of_device_id pci_ids
[] = {
1002 { .compatible
= "fsl,mpc8540-pci", },
1003 { .compatible
= "fsl,mpc8548-pcie", },
1004 { .compatible
= "fsl,mpc8610-pci", },
1005 { .compatible
= "fsl,mpc8641-pcie", },
1006 { .compatible
= "fsl,qoriq-pcie", },
1007 { .compatible
= "fsl,qoriq-pcie-v2.1", },
1008 { .compatible
= "fsl,qoriq-pcie-v2.2", },
1009 { .compatible
= "fsl,qoriq-pcie-v2.3", },
1010 { .compatible
= "fsl,qoriq-pcie-v2.4", },
1011 { .compatible
= "fsl,qoriq-pcie-v3.0", },
1014 * The following entries are for compatibility with older device
1017 { .compatible
= "fsl,p1022-pcie", },
1018 { .compatible
= "fsl,p4080-pcie", },
1023 struct device_node
*fsl_pci_primary
;
1025 void fsl_pci_assign_primary(void)
1027 struct device_node
*np
;
1029 /* Callers can specify the primary bus using other means. */
1030 if (fsl_pci_primary
)
1033 /* If a PCI host bridge contains an ISA node, it's primary. */
1034 np
= of_find_node_by_type(NULL
, "isa");
1035 while ((fsl_pci_primary
= of_get_parent(np
))) {
1037 np
= fsl_pci_primary
;
1039 if (of_match_node(pci_ids
, np
) && of_device_is_available(np
))
1044 * If there's no PCI host bridge with ISA, arbitrarily
1045 * designate one as primary. This can go away once
1046 * various bugs with primary-less systems are fixed.
1048 for_each_matching_node(np
, pci_ids
) {
1049 if (of_device_is_available(np
)) {
1050 fsl_pci_primary
= np
;
1057 #ifdef CONFIG_PM_SLEEP
1058 static irqreturn_t
fsl_pci_pme_handle(int irq
, void *dev_id
)
1060 struct pci_controller
*hose
= dev_id
;
1061 struct ccsr_pci __iomem
*pci
= hose
->private_data
;
1064 dr
= in_be32(&pci
->pex_pme_mes_dr
);
1068 out_be32(&pci
->pex_pme_mes_dr
, dr
);
1073 static int fsl_pci_pme_probe(struct pci_controller
*hose
)
1075 struct ccsr_pci __iomem
*pci
;
1076 struct pci_dev
*dev
;
1081 /* Get hose's pci_dev */
1082 dev
= list_first_entry(&hose
->bus
->devices
, typeof(*dev
), bus_list
);
1085 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pms
);
1086 pms
&= ~PCI_PM_CTRL_PME_ENABLE
;
1087 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pms
);
1089 pme_irq
= irq_of_parse_and_map(hose
->dn
, 0);
1091 dev_err(&dev
->dev
, "Failed to map PME interrupt.\n");
1096 res
= devm_request_irq(hose
->parent
, pme_irq
,
1101 dev_err(&dev
->dev
, "Unable to requiest irq %d for PME\n", pme_irq
);
1102 irq_dispose_mapping(pme_irq
);
1107 pci
= hose
->private_data
;
1109 /* Enable PTOD, ENL23D & EXL23D */
1110 clrbits32(&pci
->pex_pme_mes_disr
,
1111 PME_DISR_EN_PTOD
| PME_DISR_EN_ENL23D
| PME_DISR_EN_EXL23D
);
1113 out_be32(&pci
->pex_pme_mes_ier
, 0);
1114 setbits32(&pci
->pex_pme_mes_ier
,
1115 PME_DISR_EN_PTOD
| PME_DISR_EN_ENL23D
| PME_DISR_EN_EXL23D
);
1118 pci_read_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, &pms
);
1119 pms
|= PCI_PM_CTRL_PME_ENABLE
;
1120 pci_write_config_word(dev
, dev
->pm_cap
+ PCI_PM_CTRL
, pms
);
1125 static void send_pme_turnoff_message(struct pci_controller
*hose
)
1127 struct ccsr_pci __iomem
*pci
= hose
->private_data
;
1131 /* Send PME_Turn_Off Message Request */
1132 setbits32(&pci
->pex_pmcr
, PEX_PMCR_PTOMR
);
1134 /* Wait trun off done */
1135 for (i
= 0; i
< 150; i
++) {
1136 dr
= in_be32(&pci
->pex_pme_mes_dr
);
1138 out_be32(&pci
->pex_pme_mes_dr
, dr
);
1146 static void fsl_pci_syscore_do_suspend(struct pci_controller
*hose
)
1148 send_pme_turnoff_message(hose
);
1151 static int fsl_pci_syscore_suspend(void)
1153 struct pci_controller
*hose
, *tmp
;
1155 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
1156 fsl_pci_syscore_do_suspend(hose
);
1161 static void fsl_pci_syscore_do_resume(struct pci_controller
*hose
)
1163 struct ccsr_pci __iomem
*pci
= hose
->private_data
;
1167 /* Send Exit L2 State Message */
1168 setbits32(&pci
->pex_pmcr
, PEX_PMCR_EXL2S
);
1170 /* Wait exit done */
1171 for (i
= 0; i
< 150; i
++) {
1172 dr
= in_be32(&pci
->pex_pme_mes_dr
);
1174 out_be32(&pci
->pex_pme_mes_dr
, dr
);
1181 setup_pci_atmu(hose
);
1184 static void fsl_pci_syscore_resume(void)
1186 struct pci_controller
*hose
, *tmp
;
1188 list_for_each_entry_safe(hose
, tmp
, &hose_list
, list_node
)
1189 fsl_pci_syscore_do_resume(hose
);
1192 static struct syscore_ops pci_syscore_pm_ops
= {
1193 .suspend
= fsl_pci_syscore_suspend
,
1194 .resume
= fsl_pci_syscore_resume
,
1198 void fsl_pcibios_fixup_phb(struct pci_controller
*phb
)
1200 #ifdef CONFIG_PM_SLEEP
1201 fsl_pci_pme_probe(phb
);
1205 static int fsl_pci_probe(struct platform_device
*pdev
)
1207 struct device_node
*node
;
1210 node
= pdev
->dev
.of_node
;
1211 ret
= fsl_add_bridge(pdev
, fsl_pci_primary
== node
);
1213 mpc85xx_pci_err_probe(pdev
);
1218 static struct platform_driver fsl_pci_driver
= {
1221 .of_match_table
= pci_ids
,
1223 .probe
= fsl_pci_probe
,
1226 static int __init
fsl_pci_init(void)
1228 #ifdef CONFIG_PM_SLEEP
1229 register_syscore_ops(&pci_syscore_pm_ops
);
1231 return platform_driver_register(&fsl_pci_driver
);
1233 arch_initcall(fsl_pci_init
);