2 * arch/powerpc/kernel/mpic.c
4 * Driver for interrupt controllers following the OpenPIC standard, the
5 * common implementation beeing IBM's MPIC. This driver also can deal
6 * with various broken implementations of this HW.
8 * Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
10 * This file is subject to the terms and conditions of the GNU General Public
11 * License. See the file COPYING in the main directory of this archive
20 #include <linux/types.h>
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/irq.h>
24 #include <linux/smp.h>
25 #include <linux/interrupt.h>
26 #include <linux/bootmem.h>
27 #include <linux/spinlock.h>
28 #include <linux/pci.h>
29 #include <linux/slab.h>
31 #include <asm/ptrace.h>
32 #include <asm/signal.h>
34 #include <asm/pgtable.h>
36 #include <asm/machdep.h>
43 #define DBG(fmt...) printk(fmt)
48 static struct mpic
*mpics
;
49 static struct mpic
*mpic_primary
;
50 static DEFINE_RAW_SPINLOCK(mpic_lock
);
52 #ifdef CONFIG_PPC32 /* XXX for now */
53 #ifdef CONFIG_IRQ_ALL_CPUS
54 #define distribute_irqs (1)
56 #define distribute_irqs (0)
60 #ifdef CONFIG_MPIC_WEIRD
61 static u32 mpic_infos
[][MPIC_IDX_END
] = {
62 [0] = { /* Original OpenPIC compatible MPIC */
65 MPIC_GREG_GLOBAL_CONF_0
,
67 MPIC_GREG_IPI_VECTOR_PRI_0
,
74 MPIC_TIMER_CURRENT_CNT
,
76 MPIC_TIMER_VECTOR_PRI
,
77 MPIC_TIMER_DESTINATION
,
81 MPIC_CPU_IPI_DISPATCH_0
,
82 MPIC_CPU_IPI_DISPATCH_STRIDE
,
83 MPIC_CPU_CURRENT_TASK_PRI
,
92 MPIC_VECPRI_VECTOR_MASK
,
93 MPIC_VECPRI_POLARITY_POSITIVE
,
94 MPIC_VECPRI_POLARITY_NEGATIVE
,
95 MPIC_VECPRI_SENSE_LEVEL
,
96 MPIC_VECPRI_SENSE_EDGE
,
97 MPIC_VECPRI_POLARITY_MASK
,
98 MPIC_VECPRI_SENSE_MASK
,
101 [1] = { /* Tsi108/109 PIC */
103 TSI108_GREG_FEATURE_0
,
104 TSI108_GREG_GLOBAL_CONF_0
,
105 TSI108_GREG_VENDOR_ID
,
106 TSI108_GREG_IPI_VECTOR_PRI_0
,
107 TSI108_GREG_IPI_STRIDE
,
108 TSI108_GREG_SPURIOUS
,
109 TSI108_GREG_TIMER_FREQ
,
113 TSI108_TIMER_CURRENT_CNT
,
114 TSI108_TIMER_BASE_CNT
,
115 TSI108_TIMER_VECTOR_PRI
,
116 TSI108_TIMER_DESTINATION
,
120 TSI108_CPU_IPI_DISPATCH_0
,
121 TSI108_CPU_IPI_DISPATCH_STRIDE
,
122 TSI108_CPU_CURRENT_TASK_PRI
,
130 TSI108_IRQ_VECTOR_PRI
,
131 TSI108_VECPRI_VECTOR_MASK
,
132 TSI108_VECPRI_POLARITY_POSITIVE
,
133 TSI108_VECPRI_POLARITY_NEGATIVE
,
134 TSI108_VECPRI_SENSE_LEVEL
,
135 TSI108_VECPRI_SENSE_EDGE
,
136 TSI108_VECPRI_POLARITY_MASK
,
137 TSI108_VECPRI_SENSE_MASK
,
138 TSI108_IRQ_DESTINATION
142 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
144 #else /* CONFIG_MPIC_WEIRD */
146 #define MPIC_INFO(name) MPIC_##name
148 #endif /* CONFIG_MPIC_WEIRD */
151 * Register accessor functions
155 static inline u32
_mpic_read(enum mpic_reg_type type
,
156 struct mpic_reg_bank
*rb
,
160 #ifdef CONFIG_PPC_DCR
161 case mpic_access_dcr
:
162 return dcr_read(rb
->dhost
, reg
);
164 case mpic_access_mmio_be
:
165 return in_be32(rb
->base
+ (reg
>> 2));
166 case mpic_access_mmio_le
:
168 return in_le32(rb
->base
+ (reg
>> 2));
172 static inline void _mpic_write(enum mpic_reg_type type
,
173 struct mpic_reg_bank
*rb
,
174 unsigned int reg
, u32 value
)
177 #ifdef CONFIG_PPC_DCR
178 case mpic_access_dcr
:
179 dcr_write(rb
->dhost
, reg
, value
);
182 case mpic_access_mmio_be
:
183 out_be32(rb
->base
+ (reg
>> 2), value
);
185 case mpic_access_mmio_le
:
187 out_le32(rb
->base
+ (reg
>> 2), value
);
192 static inline u32
_mpic_ipi_read(struct mpic
*mpic
, unsigned int ipi
)
194 enum mpic_reg_type type
= mpic
->reg_type
;
195 unsigned int offset
= MPIC_INFO(GREG_IPI_VECTOR_PRI_0
) +
196 (ipi
* MPIC_INFO(GREG_IPI_STRIDE
));
198 if ((mpic
->flags
& MPIC_BROKEN_IPI
) && type
== mpic_access_mmio_le
)
199 type
= mpic_access_mmio_be
;
200 return _mpic_read(type
, &mpic
->gregs
, offset
);
203 static inline void _mpic_ipi_write(struct mpic
*mpic
, unsigned int ipi
, u32 value
)
205 unsigned int offset
= MPIC_INFO(GREG_IPI_VECTOR_PRI_0
) +
206 (ipi
* MPIC_INFO(GREG_IPI_STRIDE
));
208 _mpic_write(mpic
->reg_type
, &mpic
->gregs
, offset
, value
);
211 static inline u32
_mpic_cpu_read(struct mpic
*mpic
, unsigned int reg
)
213 unsigned int cpu
= 0;
215 if (mpic
->flags
& MPIC_PRIMARY
)
216 cpu
= hard_smp_processor_id();
217 return _mpic_read(mpic
->reg_type
, &mpic
->cpuregs
[cpu
], reg
);
220 static inline void _mpic_cpu_write(struct mpic
*mpic
, unsigned int reg
, u32 value
)
222 unsigned int cpu
= 0;
224 if (mpic
->flags
& MPIC_PRIMARY
)
225 cpu
= hard_smp_processor_id();
227 _mpic_write(mpic
->reg_type
, &mpic
->cpuregs
[cpu
], reg
, value
);
230 static inline u32
_mpic_irq_read(struct mpic
*mpic
, unsigned int src_no
, unsigned int reg
)
232 unsigned int isu
= src_no
>> mpic
->isu_shift
;
233 unsigned int idx
= src_no
& mpic
->isu_mask
;
236 val
= _mpic_read(mpic
->reg_type
, &mpic
->isus
[isu
],
237 reg
+ (idx
* MPIC_INFO(IRQ_STRIDE
)));
238 #ifdef CONFIG_MPIC_BROKEN_REGREAD
240 val
= (val
& (MPIC_VECPRI_MASK
| MPIC_VECPRI_ACTIVITY
)) |
241 mpic
->isu_reg0_shadow
[src_no
];
246 static inline void _mpic_irq_write(struct mpic
*mpic
, unsigned int src_no
,
247 unsigned int reg
, u32 value
)
249 unsigned int isu
= src_no
>> mpic
->isu_shift
;
250 unsigned int idx
= src_no
& mpic
->isu_mask
;
252 _mpic_write(mpic
->reg_type
, &mpic
->isus
[isu
],
253 reg
+ (idx
* MPIC_INFO(IRQ_STRIDE
)), value
);
255 #ifdef CONFIG_MPIC_BROKEN_REGREAD
257 mpic
->isu_reg0_shadow
[src_no
] =
258 value
& ~(MPIC_VECPRI_MASK
| MPIC_VECPRI_ACTIVITY
);
262 #define mpic_read(b,r) _mpic_read(mpic->reg_type,&(b),(r))
263 #define mpic_write(b,r,v) _mpic_write(mpic->reg_type,&(b),(r),(v))
264 #define mpic_ipi_read(i) _mpic_ipi_read(mpic,(i))
265 #define mpic_ipi_write(i,v) _mpic_ipi_write(mpic,(i),(v))
266 #define mpic_cpu_read(i) _mpic_cpu_read(mpic,(i))
267 #define mpic_cpu_write(i,v) _mpic_cpu_write(mpic,(i),(v))
268 #define mpic_irq_read(s,r) _mpic_irq_read(mpic,(s),(r))
269 #define mpic_irq_write(s,r,v) _mpic_irq_write(mpic,(s),(r),(v))
273 * Low level utility functions
277 static void _mpic_map_mmio(struct mpic
*mpic
, phys_addr_t phys_addr
,
278 struct mpic_reg_bank
*rb
, unsigned int offset
,
281 rb
->base
= ioremap(phys_addr
+ offset
, size
);
282 BUG_ON(rb
->base
== NULL
);
285 #ifdef CONFIG_PPC_DCR
286 static void _mpic_map_dcr(struct mpic
*mpic
, struct device_node
*node
,
287 struct mpic_reg_bank
*rb
,
288 unsigned int offset
, unsigned int size
)
292 dbasep
= of_get_property(node
, "dcr-reg", NULL
);
294 rb
->dhost
= dcr_map(node
, *dbasep
+ offset
, size
);
295 BUG_ON(!DCR_MAP_OK(rb
->dhost
));
298 static inline void mpic_map(struct mpic
*mpic
, struct device_node
*node
,
299 phys_addr_t phys_addr
, struct mpic_reg_bank
*rb
,
300 unsigned int offset
, unsigned int size
)
302 if (mpic
->flags
& MPIC_USES_DCR
)
303 _mpic_map_dcr(mpic
, node
, rb
, offset
, size
);
305 _mpic_map_mmio(mpic
, phys_addr
, rb
, offset
, size
);
307 #else /* CONFIG_PPC_DCR */
308 #define mpic_map(m,n,p,b,o,s) _mpic_map_mmio(m,p,b,o,s)
309 #endif /* !CONFIG_PPC_DCR */
313 /* Check if we have one of those nice broken MPICs with a flipped endian on
314 * reads from IPI registers
316 static void __init
mpic_test_broken_ipi(struct mpic
*mpic
)
320 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_IPI_VECTOR_PRI_0
), MPIC_VECPRI_MASK
);
321 r
= mpic_read(mpic
->gregs
, MPIC_INFO(GREG_IPI_VECTOR_PRI_0
));
323 if (r
== le32_to_cpu(MPIC_VECPRI_MASK
)) {
324 printk(KERN_INFO
"mpic: Detected reversed IPI registers\n");
325 mpic
->flags
|= MPIC_BROKEN_IPI
;
329 #ifdef CONFIG_MPIC_U3_HT_IRQS
331 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
332 * to force the edge setting on the MPIC and do the ack workaround.
334 static inline int mpic_is_ht_interrupt(struct mpic
*mpic
, unsigned int source
)
336 if (source
>= 128 || !mpic
->fixups
)
338 return mpic
->fixups
[source
].base
!= NULL
;
342 static inline void mpic_ht_end_irq(struct mpic
*mpic
, unsigned int source
)
344 struct mpic_irq_fixup
*fixup
= &mpic
->fixups
[source
];
346 if (fixup
->applebase
) {
347 unsigned int soff
= (fixup
->index
>> 3) & ~3;
348 unsigned int mask
= 1U << (fixup
->index
& 0x1f);
349 writel(mask
, fixup
->applebase
+ soff
);
351 raw_spin_lock(&mpic
->fixup_lock
);
352 writeb(0x11 + 2 * fixup
->index
, fixup
->base
+ 2);
353 writel(fixup
->data
, fixup
->base
+ 4);
354 raw_spin_unlock(&mpic
->fixup_lock
);
358 static void mpic_startup_ht_interrupt(struct mpic
*mpic
, unsigned int source
,
359 unsigned int irqflags
)
361 struct mpic_irq_fixup
*fixup
= &mpic
->fixups
[source
];
365 if (fixup
->base
== NULL
)
368 DBG("startup_ht_interrupt(0x%x, 0x%x) index: %d\n",
369 source
, irqflags
, fixup
->index
);
370 raw_spin_lock_irqsave(&mpic
->fixup_lock
, flags
);
371 /* Enable and configure */
372 writeb(0x10 + 2 * fixup
->index
, fixup
->base
+ 2);
373 tmp
= readl(fixup
->base
+ 4);
375 if (irqflags
& IRQ_LEVEL
)
377 writel(tmp
, fixup
->base
+ 4);
378 raw_spin_unlock_irqrestore(&mpic
->fixup_lock
, flags
);
381 /* use the lowest bit inverted to the actual HW,
382 * set if this fixup was enabled, clear otherwise */
383 mpic
->save_data
[source
].fixup_data
= tmp
| 1;
387 static void mpic_shutdown_ht_interrupt(struct mpic
*mpic
, unsigned int source
,
388 unsigned int irqflags
)
390 struct mpic_irq_fixup
*fixup
= &mpic
->fixups
[source
];
394 if (fixup
->base
== NULL
)
397 DBG("shutdown_ht_interrupt(0x%x, 0x%x)\n", source
, irqflags
);
400 raw_spin_lock_irqsave(&mpic
->fixup_lock
, flags
);
401 writeb(0x10 + 2 * fixup
->index
, fixup
->base
+ 2);
402 tmp
= readl(fixup
->base
+ 4);
404 writel(tmp
, fixup
->base
+ 4);
405 raw_spin_unlock_irqrestore(&mpic
->fixup_lock
, flags
);
408 /* use the lowest bit inverted to the actual HW,
409 * set if this fixup was enabled, clear otherwise */
410 mpic
->save_data
[source
].fixup_data
= tmp
& ~1;
414 #ifdef CONFIG_PCI_MSI
415 static void __init
mpic_scan_ht_msi(struct mpic
*mpic
, u8 __iomem
*devbase
,
422 for (pos
= readb(devbase
+ PCI_CAPABILITY_LIST
); pos
!= 0;
423 pos
= readb(devbase
+ pos
+ PCI_CAP_LIST_NEXT
)) {
424 u8 id
= readb(devbase
+ pos
+ PCI_CAP_LIST_ID
);
425 if (id
== PCI_CAP_ID_HT
) {
426 id
= readb(devbase
+ pos
+ 3);
427 if ((id
& HT_5BIT_CAP_MASK
) == HT_CAPTYPE_MSI_MAPPING
)
435 base
= devbase
+ pos
;
437 flags
= readb(base
+ HT_MSI_FLAGS
);
438 if (!(flags
& HT_MSI_FLAGS_FIXED
)) {
439 addr
= readl(base
+ HT_MSI_ADDR_LO
) & HT_MSI_ADDR_LO_MASK
;
440 addr
= addr
| ((u64
)readl(base
+ HT_MSI_ADDR_HI
) << 32);
443 printk(KERN_DEBUG
"mpic: - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
444 PCI_SLOT(devfn
), PCI_FUNC(devfn
),
445 flags
& HT_MSI_FLAGS_ENABLE
? "enabled" : "disabled", addr
);
447 if (!(flags
& HT_MSI_FLAGS_ENABLE
))
448 writeb(flags
| HT_MSI_FLAGS_ENABLE
, base
+ HT_MSI_FLAGS
);
451 static void __init
mpic_scan_ht_msi(struct mpic
*mpic
, u8 __iomem
*devbase
,
458 static void __init
mpic_scan_ht_pic(struct mpic
*mpic
, u8 __iomem
*devbase
,
459 unsigned int devfn
, u32 vdid
)
466 for (pos
= readb(devbase
+ PCI_CAPABILITY_LIST
); pos
!= 0;
467 pos
= readb(devbase
+ pos
+ PCI_CAP_LIST_NEXT
)) {
468 u8 id
= readb(devbase
+ pos
+ PCI_CAP_LIST_ID
);
469 if (id
== PCI_CAP_ID_HT
) {
470 id
= readb(devbase
+ pos
+ 3);
471 if ((id
& HT_5BIT_CAP_MASK
) == HT_CAPTYPE_IRQ
)
478 base
= devbase
+ pos
;
479 writeb(0x01, base
+ 2);
480 n
= (readl(base
+ 4) >> 16) & 0xff;
482 printk(KERN_INFO
"mpic: - HT:%02x.%x [0x%02x] vendor %04x device %04x"
484 devfn
>> 3, devfn
& 0x7, pos
, vdid
& 0xffff, vdid
>> 16, n
+ 1);
486 for (i
= 0; i
<= n
; i
++) {
487 writeb(0x10 + 2 * i
, base
+ 2);
488 tmp
= readl(base
+ 4);
489 irq
= (tmp
>> 16) & 0xff;
490 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i
, irq
, tmp
);
491 /* mask it , will be unmasked later */
493 writel(tmp
, base
+ 4);
494 mpic
->fixups
[irq
].index
= i
;
495 mpic
->fixups
[irq
].base
= base
;
496 /* Apple HT PIC has a non-standard way of doing EOIs */
497 if ((vdid
& 0xffff) == 0x106b)
498 mpic
->fixups
[irq
].applebase
= devbase
+ 0x60;
500 mpic
->fixups
[irq
].applebase
= NULL
;
501 writeb(0x11 + 2 * i
, base
+ 2);
502 mpic
->fixups
[irq
].data
= readl(base
+ 4) | 0x80000000;
507 static void __init
mpic_scan_ht_pics(struct mpic
*mpic
)
510 u8 __iomem
*cfgspace
;
512 printk(KERN_INFO
"mpic: Setting up HT PICs workarounds for U3/U4\n");
514 /* Allocate fixups array */
515 mpic
->fixups
= kzalloc(128 * sizeof(*mpic
->fixups
), GFP_KERNEL
);
516 BUG_ON(mpic
->fixups
== NULL
);
519 raw_spin_lock_init(&mpic
->fixup_lock
);
521 /* Map U3 config space. We assume all IO-APICs are on the primary bus
522 * so we only need to map 64kB.
524 cfgspace
= ioremap(0xf2000000, 0x10000);
525 BUG_ON(cfgspace
== NULL
);
527 /* Now we scan all slots. We do a very quick scan, we read the header
528 * type, vendor ID and device ID only, that's plenty enough
530 for (devfn
= 0; devfn
< 0x100; devfn
++) {
531 u8 __iomem
*devbase
= cfgspace
+ (devfn
<< 8);
532 u8 hdr_type
= readb(devbase
+ PCI_HEADER_TYPE
);
533 u32 l
= readl(devbase
+ PCI_VENDOR_ID
);
536 DBG("devfn %x, l: %x\n", devfn
, l
);
538 /* If no device, skip */
539 if (l
== 0xffffffff || l
== 0x00000000 ||
540 l
== 0x0000ffff || l
== 0xffff0000)
542 /* Check if is supports capability lists */
543 s
= readw(devbase
+ PCI_STATUS
);
544 if (!(s
& PCI_STATUS_CAP_LIST
))
547 mpic_scan_ht_pic(mpic
, devbase
, devfn
, l
);
548 mpic_scan_ht_msi(mpic
, devbase
, devfn
);
551 /* next device, if function 0 */
552 if (PCI_FUNC(devfn
) == 0 && (hdr_type
& 0x80) == 0)
557 #else /* CONFIG_MPIC_U3_HT_IRQS */
559 static inline int mpic_is_ht_interrupt(struct mpic
*mpic
, unsigned int source
)
564 static void __init
mpic_scan_ht_pics(struct mpic
*mpic
)
568 #endif /* CONFIG_MPIC_U3_HT_IRQS */
571 static int irq_choose_cpu(const cpumask_t
*mask
)
575 if (cpumask_equal(mask
, cpu_all_mask
)) {
576 static int irq_rover
;
577 static DEFINE_RAW_SPINLOCK(irq_rover_lock
);
580 /* Round-robin distribution... */
582 raw_spin_lock_irqsave(&irq_rover_lock
, flags
);
584 while (!cpu_online(irq_rover
)) {
585 if (++irq_rover
>= NR_CPUS
)
590 if (++irq_rover
>= NR_CPUS
)
592 } while (!cpu_online(irq_rover
));
594 raw_spin_unlock_irqrestore(&irq_rover_lock
, flags
);
596 cpuid
= cpumask_first_and(mask
, cpu_online_mask
);
597 if (cpuid
>= nr_cpu_ids
)
601 return get_hard_smp_processor_id(cpuid
);
604 static int irq_choose_cpu(const cpumask_t
*mask
)
606 return hard_smp_processor_id();
610 #define mpic_irq_to_hw(virq) ((unsigned int)irq_map[virq].hwirq)
612 /* Find an mpic associated with a given linux interrupt */
613 static struct mpic
*mpic_find(unsigned int irq
)
615 if (irq
< NUM_ISA_INTERRUPTS
)
618 return irq_to_desc(irq
)->chip_data
;
621 /* Determine if the linux irq is an IPI */
622 static unsigned int mpic_is_ipi(struct mpic
*mpic
, unsigned int irq
)
624 unsigned int src
= mpic_irq_to_hw(irq
);
626 return (src
>= mpic
->ipi_vecs
[0] && src
<= mpic
->ipi_vecs
[3]);
630 /* Convert a cpu mask from logical to physical cpu numbers. */
631 static inline u32
mpic_physmask(u32 cpumask
)
636 for (i
= 0; i
< NR_CPUS
; ++i
, cpumask
>>= 1)
637 mask
|= (cpumask
& 1) << get_hard_smp_processor_id(i
);
642 /* Get the mpic structure from the IPI number */
643 static inline struct mpic
* mpic_from_ipi(unsigned int ipi
)
645 return irq_to_desc(ipi
)->chip_data
;
649 /* Get the mpic structure from the irq number */
650 static inline struct mpic
* mpic_from_irq(unsigned int irq
)
652 return irq_to_desc(irq
)->chip_data
;
656 static inline void mpic_eoi(struct mpic
*mpic
)
658 mpic_cpu_write(MPIC_INFO(CPU_EOI
), 0);
659 (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI
));
663 * Linux descriptor level callbacks
667 void mpic_unmask_irq(unsigned int irq
)
669 unsigned int loops
= 100000;
670 struct mpic
*mpic
= mpic_from_irq(irq
);
671 unsigned int src
= mpic_irq_to_hw(irq
);
673 DBG("%p: %s: enable_irq: %d (src %d)\n", mpic
, mpic
->name
, irq
, src
);
675 mpic_irq_write(src
, MPIC_INFO(IRQ_VECTOR_PRI
),
676 mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
)) &
678 /* make sure mask gets to controller before we return to user */
681 printk(KERN_ERR
"mpic_enable_irq timeout\n");
684 } while(mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
)) & MPIC_VECPRI_MASK
);
687 void mpic_mask_irq(unsigned int irq
)
689 unsigned int loops
= 100000;
690 struct mpic
*mpic
= mpic_from_irq(irq
);
691 unsigned int src
= mpic_irq_to_hw(irq
);
693 DBG("%s: disable_irq: %d (src %d)\n", mpic
->name
, irq
, src
);
695 mpic_irq_write(src
, MPIC_INFO(IRQ_VECTOR_PRI
),
696 mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
)) |
699 /* make sure mask gets to controller before we return to user */
702 printk(KERN_ERR
"mpic_enable_irq timeout\n");
705 } while(!(mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
)) & MPIC_VECPRI_MASK
));
708 void mpic_end_irq(unsigned int irq
)
710 struct mpic
*mpic
= mpic_from_irq(irq
);
713 DBG("%s: end_irq: %d\n", mpic
->name
, irq
);
715 /* We always EOI on end_irq() even for edge interrupts since that
716 * should only lower the priority, the MPIC should have properly
717 * latched another edge interrupt coming in anyway
723 #ifdef CONFIG_MPIC_U3_HT_IRQS
725 static void mpic_unmask_ht_irq(unsigned int irq
)
727 struct mpic
*mpic
= mpic_from_irq(irq
);
728 unsigned int src
= mpic_irq_to_hw(irq
);
730 mpic_unmask_irq(irq
);
732 if (irq_to_desc(irq
)->status
& IRQ_LEVEL
)
733 mpic_ht_end_irq(mpic
, src
);
736 static unsigned int mpic_startup_ht_irq(unsigned int irq
)
738 struct mpic
*mpic
= mpic_from_irq(irq
);
739 unsigned int src
= mpic_irq_to_hw(irq
);
741 mpic_unmask_irq(irq
);
742 mpic_startup_ht_interrupt(mpic
, src
, irq_to_desc(irq
)->status
);
747 static void mpic_shutdown_ht_irq(unsigned int irq
)
749 struct mpic
*mpic
= mpic_from_irq(irq
);
750 unsigned int src
= mpic_irq_to_hw(irq
);
752 mpic_shutdown_ht_interrupt(mpic
, src
, irq_to_desc(irq
)->status
);
756 static void mpic_end_ht_irq(unsigned int irq
)
758 struct mpic
*mpic
= mpic_from_irq(irq
);
759 unsigned int src
= mpic_irq_to_hw(irq
);
762 DBG("%s: end_irq: %d\n", mpic
->name
, irq
);
764 /* We always EOI on end_irq() even for edge interrupts since that
765 * should only lower the priority, the MPIC should have properly
766 * latched another edge interrupt coming in anyway
769 if (irq_to_desc(irq
)->status
& IRQ_LEVEL
)
770 mpic_ht_end_irq(mpic
, src
);
773 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
777 static void mpic_unmask_ipi(unsigned int irq
)
779 struct mpic
*mpic
= mpic_from_ipi(irq
);
780 unsigned int src
= mpic_irq_to_hw(irq
) - mpic
->ipi_vecs
[0];
782 DBG("%s: enable_ipi: %d (ipi %d)\n", mpic
->name
, irq
, src
);
783 mpic_ipi_write(src
, mpic_ipi_read(src
) & ~MPIC_VECPRI_MASK
);
786 static void mpic_mask_ipi(unsigned int irq
)
788 /* NEVER disable an IPI... that's just plain wrong! */
791 static void mpic_end_ipi(unsigned int irq
)
793 struct mpic
*mpic
= mpic_from_ipi(irq
);
796 * IPIs are marked IRQ_PER_CPU. This has the side effect of
797 * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
798 * applying to them. We EOI them late to avoid re-entering.
799 * We mark IPI's with IRQF_DISABLED as they must run with
805 #endif /* CONFIG_SMP */
807 int mpic_set_affinity(unsigned int irq
, const struct cpumask
*cpumask
)
809 struct mpic
*mpic
= mpic_from_irq(irq
);
810 unsigned int src
= mpic_irq_to_hw(irq
);
812 if (mpic
->flags
& MPIC_SINGLE_DEST_CPU
) {
813 int cpuid
= irq_choose_cpu(cpumask
);
815 mpic_irq_write(src
, MPIC_INFO(IRQ_DESTINATION
), 1 << cpuid
);
819 cpumask_and(&tmp
, cpumask
, cpu_online_mask
);
821 mpic_irq_write(src
, MPIC_INFO(IRQ_DESTINATION
),
822 mpic_physmask(cpus_addr(tmp
)[0]));
828 static unsigned int mpic_type_to_vecpri(struct mpic
*mpic
, unsigned int type
)
830 /* Now convert sense value */
831 switch(type
& IRQ_TYPE_SENSE_MASK
) {
832 case IRQ_TYPE_EDGE_RISING
:
833 return MPIC_INFO(VECPRI_SENSE_EDGE
) |
834 MPIC_INFO(VECPRI_POLARITY_POSITIVE
);
835 case IRQ_TYPE_EDGE_FALLING
:
836 case IRQ_TYPE_EDGE_BOTH
:
837 return MPIC_INFO(VECPRI_SENSE_EDGE
) |
838 MPIC_INFO(VECPRI_POLARITY_NEGATIVE
);
839 case IRQ_TYPE_LEVEL_HIGH
:
840 return MPIC_INFO(VECPRI_SENSE_LEVEL
) |
841 MPIC_INFO(VECPRI_POLARITY_POSITIVE
);
842 case IRQ_TYPE_LEVEL_LOW
:
844 return MPIC_INFO(VECPRI_SENSE_LEVEL
) |
845 MPIC_INFO(VECPRI_POLARITY_NEGATIVE
);
849 int mpic_set_irq_type(unsigned int virq
, unsigned int flow_type
)
851 struct mpic
*mpic
= mpic_from_irq(virq
);
852 unsigned int src
= mpic_irq_to_hw(virq
);
853 struct irq_desc
*desc
= irq_to_desc(virq
);
854 unsigned int vecpri
, vold
, vnew
;
856 DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
857 mpic
, virq
, src
, flow_type
);
859 if (src
>= mpic
->irq_count
)
862 if (flow_type
== IRQ_TYPE_NONE
)
863 if (mpic
->senses
&& src
< mpic
->senses_count
)
864 flow_type
= mpic
->senses
[src
];
865 if (flow_type
== IRQ_TYPE_NONE
)
866 flow_type
= IRQ_TYPE_LEVEL_LOW
;
868 desc
->status
&= ~(IRQ_TYPE_SENSE_MASK
| IRQ_LEVEL
);
869 desc
->status
|= flow_type
& IRQ_TYPE_SENSE_MASK
;
870 if (flow_type
& (IRQ_TYPE_LEVEL_HIGH
| IRQ_TYPE_LEVEL_LOW
))
871 desc
->status
|= IRQ_LEVEL
;
873 if (mpic_is_ht_interrupt(mpic
, src
))
874 vecpri
= MPIC_VECPRI_POLARITY_POSITIVE
|
875 MPIC_VECPRI_SENSE_EDGE
;
877 vecpri
= mpic_type_to_vecpri(mpic
, flow_type
);
879 vold
= mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
));
880 vnew
= vold
& ~(MPIC_INFO(VECPRI_POLARITY_MASK
) |
881 MPIC_INFO(VECPRI_SENSE_MASK
));
884 mpic_irq_write(src
, MPIC_INFO(IRQ_VECTOR_PRI
), vnew
);
889 void mpic_set_vector(unsigned int virq
, unsigned int vector
)
891 struct mpic
*mpic
= mpic_from_irq(virq
);
892 unsigned int src
= mpic_irq_to_hw(virq
);
895 DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
896 mpic
, virq
, src
, vector
);
898 if (src
>= mpic
->irq_count
)
901 vecpri
= mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
));
902 vecpri
= vecpri
& ~MPIC_INFO(VECPRI_VECTOR_MASK
);
904 mpic_irq_write(src
, MPIC_INFO(IRQ_VECTOR_PRI
), vecpri
);
907 static struct irq_chip mpic_irq_chip
= {
908 .mask
= mpic_mask_irq
,
909 .unmask
= mpic_unmask_irq
,
911 .set_type
= mpic_set_irq_type
,
915 static struct irq_chip mpic_ipi_chip
= {
916 .mask
= mpic_mask_ipi
,
917 .unmask
= mpic_unmask_ipi
,
920 #endif /* CONFIG_SMP */
922 #ifdef CONFIG_MPIC_U3_HT_IRQS
923 static struct irq_chip mpic_irq_ht_chip
= {
924 .startup
= mpic_startup_ht_irq
,
925 .shutdown
= mpic_shutdown_ht_irq
,
926 .mask
= mpic_mask_irq
,
927 .unmask
= mpic_unmask_ht_irq
,
928 .eoi
= mpic_end_ht_irq
,
929 .set_type
= mpic_set_irq_type
,
931 #endif /* CONFIG_MPIC_U3_HT_IRQS */
934 static int mpic_host_match(struct irq_host
*h
, struct device_node
*node
)
936 /* Exact match, unless mpic node is NULL */
937 return h
->of_node
== NULL
|| h
->of_node
== node
;
940 static int mpic_host_map(struct irq_host
*h
, unsigned int virq
,
943 struct mpic
*mpic
= h
->host_data
;
944 struct irq_chip
*chip
;
946 DBG("mpic: map virq %d, hwirq 0x%lx\n", virq
, hw
);
948 if (hw
== mpic
->spurious_vec
)
950 if (mpic
->protected && test_bit(hw
, mpic
->protected))
954 else if (hw
>= mpic
->ipi_vecs
[0]) {
955 WARN_ON(!(mpic
->flags
& MPIC_PRIMARY
));
957 DBG("mpic: mapping as IPI\n");
958 set_irq_chip_data(virq
, mpic
);
959 set_irq_chip_and_handler(virq
, &mpic
->hc_ipi
,
963 #endif /* CONFIG_SMP */
965 if (hw
>= mpic
->irq_count
)
968 mpic_msi_reserve_hwirq(mpic
, hw
);
971 chip
= &mpic
->hc_irq
;
973 #ifdef CONFIG_MPIC_U3_HT_IRQS
974 /* Check for HT interrupts, override vecpri */
975 if (mpic_is_ht_interrupt(mpic
, hw
))
976 chip
= &mpic
->hc_ht_irq
;
977 #endif /* CONFIG_MPIC_U3_HT_IRQS */
979 DBG("mpic: mapping to irq chip @%p\n", chip
);
981 set_irq_chip_data(virq
, mpic
);
982 set_irq_chip_and_handler(virq
, chip
, handle_fasteoi_irq
);
984 /* Set default irq type */
985 set_irq_type(virq
, IRQ_TYPE_NONE
);
990 static int mpic_host_xlate(struct irq_host
*h
, struct device_node
*ct
,
991 const u32
*intspec
, unsigned int intsize
,
992 irq_hw_number_t
*out_hwirq
, unsigned int *out_flags
)
995 static unsigned char map_mpic_senses
[4] = {
996 IRQ_TYPE_EDGE_RISING
,
999 IRQ_TYPE_EDGE_FALLING
,
1002 *out_hwirq
= intspec
[0];
1006 /* Apple invented a new race of encoding on machines with
1007 * an HT APIC. They encode, among others, the index within
1008 * the HT APIC. We don't care about it here since thankfully,
1009 * it appears that they have the APIC already properly
1010 * configured, and thus our current fixup code that reads the
1011 * APIC config works fine. However, we still need to mask out
1012 * bits in the specifier to make sure we only get bit 0 which
1013 * is the level/edge bit (the only sense bit exposed by Apple),
1014 * as their bit 1 means something else.
1016 if (machine_is(powermac
))
1018 *out_flags
= map_mpic_senses
[intspec
[1] & mask
];
1020 *out_flags
= IRQ_TYPE_NONE
;
1022 DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1023 intsize
, intspec
[0], intspec
[1], *out_hwirq
, *out_flags
);
1028 static struct irq_host_ops mpic_host_ops
= {
1029 .match
= mpic_host_match
,
1030 .map
= mpic_host_map
,
1031 .xlate
= mpic_host_xlate
,
1035 * Exported functions
1038 struct mpic
* __init
mpic_alloc(struct device_node
*node
,
1039 phys_addr_t phys_addr
,
1041 unsigned int isu_size
,
1042 unsigned int irq_count
,
1050 u64 paddr
= phys_addr
;
1052 mpic
= kzalloc(sizeof(struct mpic
), GFP_KERNEL
);
1058 mpic
->hc_irq
= mpic_irq_chip
;
1059 mpic
->hc_irq
.name
= name
;
1060 if (flags
& MPIC_PRIMARY
)
1061 mpic
->hc_irq
.set_affinity
= mpic_set_affinity
;
1062 #ifdef CONFIG_MPIC_U3_HT_IRQS
1063 mpic
->hc_ht_irq
= mpic_irq_ht_chip
;
1064 mpic
->hc_ht_irq
.name
= name
;
1065 if (flags
& MPIC_PRIMARY
)
1066 mpic
->hc_ht_irq
.set_affinity
= mpic_set_affinity
;
1067 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1070 mpic
->hc_ipi
= mpic_ipi_chip
;
1071 mpic
->hc_ipi
.name
= name
;
1072 #endif /* CONFIG_SMP */
1074 mpic
->flags
= flags
;
1075 mpic
->isu_size
= isu_size
;
1076 mpic
->irq_count
= irq_count
;
1077 mpic
->num_sources
= 0; /* so far */
1079 if (flags
& MPIC_LARGE_VECTORS
)
1084 mpic
->timer_vecs
[0] = intvec_top
- 8;
1085 mpic
->timer_vecs
[1] = intvec_top
- 7;
1086 mpic
->timer_vecs
[2] = intvec_top
- 6;
1087 mpic
->timer_vecs
[3] = intvec_top
- 5;
1088 mpic
->ipi_vecs
[0] = intvec_top
- 4;
1089 mpic
->ipi_vecs
[1] = intvec_top
- 3;
1090 mpic
->ipi_vecs
[2] = intvec_top
- 2;
1091 mpic
->ipi_vecs
[3] = intvec_top
- 1;
1092 mpic
->spurious_vec
= intvec_top
;
1094 /* Check for "big-endian" in device-tree */
1095 if (node
&& of_get_property(node
, "big-endian", NULL
) != NULL
)
1096 mpic
->flags
|= MPIC_BIG_ENDIAN
;
1098 /* Look for protected sources */
1101 unsigned int bits
, mapsize
;
1103 of_get_property(node
, "protected-sources", &psize
);
1106 bits
= intvec_top
+ 1;
1107 mapsize
= BITS_TO_LONGS(bits
) * sizeof(unsigned long);
1108 mpic
->protected = kzalloc(mapsize
, GFP_KERNEL
);
1109 BUG_ON(mpic
->protected == NULL
);
1110 for (i
= 0; i
< psize
; i
++) {
1111 if (psrc
[i
] > intvec_top
)
1113 __set_bit(psrc
[i
], mpic
->protected);
1118 #ifdef CONFIG_MPIC_WEIRD
1119 mpic
->hw_set
= mpic_infos
[MPIC_GET_REGSET(flags
)];
1122 /* default register type */
1123 mpic
->reg_type
= (flags
& MPIC_BIG_ENDIAN
) ?
1124 mpic_access_mmio_be
: mpic_access_mmio_le
;
1126 /* If no physical address is passed in, a device-node is mandatory */
1127 BUG_ON(paddr
== 0 && node
== NULL
);
1129 /* If no physical address passed in, check if it's dcr based */
1130 if (paddr
== 0 && of_get_property(node
, "dcr-reg", NULL
) != NULL
) {
1131 #ifdef CONFIG_PPC_DCR
1132 mpic
->flags
|= MPIC_USES_DCR
;
1133 mpic
->reg_type
= mpic_access_dcr
;
1136 #endif /* CONFIG_PPC_DCR */
1139 /* If the MPIC is not DCR based, and no physical address was passed
1140 * in, try to obtain one
1142 if (paddr
== 0 && !(mpic
->flags
& MPIC_USES_DCR
)) {
1143 const u32
*reg
= of_get_property(node
, "reg", NULL
);
1144 BUG_ON(reg
== NULL
);
1145 paddr
= of_translate_address(node
, reg
);
1146 BUG_ON(paddr
== OF_BAD_ADDR
);
1149 /* Map the global registers */
1150 mpic_map(mpic
, node
, paddr
, &mpic
->gregs
, MPIC_INFO(GREG_BASE
), 0x1000);
1151 mpic_map(mpic
, node
, paddr
, &mpic
->tmregs
, MPIC_INFO(TIMER_BASE
), 0x1000);
1154 if (flags
& MPIC_WANTS_RESET
) {
1155 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
),
1156 mpic_read(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
))
1157 | MPIC_GREG_GCONF_RESET
);
1158 while( mpic_read(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
))
1159 & MPIC_GREG_GCONF_RESET
)
1164 if (flags
& MPIC_ENABLE_COREINT
)
1165 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
),
1166 mpic_read(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
))
1167 | MPIC_GREG_GCONF_COREINT
);
1169 if (flags
& MPIC_ENABLE_MCK
)
1170 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
),
1171 mpic_read(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
))
1172 | MPIC_GREG_GCONF_MCK
);
1174 /* Read feature register, calculate num CPUs and, for non-ISU
1175 * MPICs, num sources as well. On ISU MPICs, sources are counted
1178 greg_feature
= mpic_read(mpic
->gregs
, MPIC_INFO(GREG_FEATURE_0
));
1179 mpic
->num_cpus
= ((greg_feature
& MPIC_GREG_FEATURE_LAST_CPU_MASK
)
1180 >> MPIC_GREG_FEATURE_LAST_CPU_SHIFT
) + 1;
1181 if (isu_size
== 0) {
1182 if (flags
& MPIC_BROKEN_FRR_NIRQS
)
1183 mpic
->num_sources
= mpic
->irq_count
;
1186 ((greg_feature
& MPIC_GREG_FEATURE_LAST_SRC_MASK
)
1187 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT
) + 1;
1190 /* Map the per-CPU registers */
1191 for (i
= 0; i
< mpic
->num_cpus
; i
++) {
1192 mpic_map(mpic
, node
, paddr
, &mpic
->cpuregs
[i
],
1193 MPIC_INFO(CPU_BASE
) + i
* MPIC_INFO(CPU_STRIDE
),
1197 /* Initialize main ISU if none provided */
1198 if (mpic
->isu_size
== 0) {
1199 mpic
->isu_size
= mpic
->num_sources
;
1200 mpic_map(mpic
, node
, paddr
, &mpic
->isus
[0],
1201 MPIC_INFO(IRQ_BASE
), MPIC_INFO(IRQ_STRIDE
) * mpic
->isu_size
);
1203 mpic
->isu_shift
= 1 + __ilog2(mpic
->isu_size
- 1);
1204 mpic
->isu_mask
= (1 << mpic
->isu_shift
) - 1;
1206 mpic
->irqhost
= irq_alloc_host(node
, IRQ_HOST_MAP_LINEAR
,
1207 isu_size
? isu_size
: mpic
->num_sources
,
1209 flags
& MPIC_LARGE_VECTORS
? 2048 : 256);
1210 if (mpic
->irqhost
== NULL
)
1213 mpic
->irqhost
->host_data
= mpic
;
1215 /* Display version */
1216 switch (greg_feature
& MPIC_GREG_FEATURE_VERSION_MASK
) {
1230 printk(KERN_INFO
"mpic: Setting up MPIC \"%s\" version %s at %llx,"
1232 name
, vers
, (unsigned long long)paddr
, mpic
->num_cpus
);
1233 printk(KERN_INFO
"mpic: ISU size: %d, shift: %d, mask: %x\n",
1234 mpic
->isu_size
, mpic
->isu_shift
, mpic
->isu_mask
);
1239 if (flags
& MPIC_PRIMARY
) {
1240 mpic_primary
= mpic
;
1241 irq_set_default_host(mpic
->irqhost
);
1247 void __init
mpic_assign_isu(struct mpic
*mpic
, unsigned int isu_num
,
1250 unsigned int isu_first
= isu_num
* mpic
->isu_size
;
1252 BUG_ON(isu_num
>= MPIC_MAX_ISU
);
1254 mpic_map(mpic
, mpic
->irqhost
->of_node
,
1255 paddr
, &mpic
->isus
[isu_num
], 0,
1256 MPIC_INFO(IRQ_STRIDE
) * mpic
->isu_size
);
1258 if ((isu_first
+ mpic
->isu_size
) > mpic
->num_sources
)
1259 mpic
->num_sources
= isu_first
+ mpic
->isu_size
;
1262 void __init
mpic_set_default_senses(struct mpic
*mpic
, u8
*senses
, int count
)
1264 mpic
->senses
= senses
;
1265 mpic
->senses_count
= count
;
1268 void __init
mpic_init(struct mpic
*mpic
)
1273 BUG_ON(mpic
->num_sources
== 0);
1275 printk(KERN_INFO
"mpic: Initializing for %d sources\n", mpic
->num_sources
);
1277 /* Set current processor priority to max */
1278 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI
), 0xf);
1280 /* Initialize timers: just disable them all */
1281 for (i
= 0; i
< 4; i
++) {
1282 mpic_write(mpic
->tmregs
,
1283 i
* MPIC_INFO(TIMER_STRIDE
) +
1284 MPIC_INFO(TIMER_DESTINATION
), 0);
1285 mpic_write(mpic
->tmregs
,
1286 i
* MPIC_INFO(TIMER_STRIDE
) +
1287 MPIC_INFO(TIMER_VECTOR_PRI
),
1289 (mpic
->timer_vecs
[0] + i
));
1292 /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1293 mpic_test_broken_ipi(mpic
);
1294 for (i
= 0; i
< 4; i
++) {
1297 (10 << MPIC_VECPRI_PRIORITY_SHIFT
) |
1298 (mpic
->ipi_vecs
[0] + i
));
1301 /* Initialize interrupt sources */
1302 if (mpic
->irq_count
== 0)
1303 mpic
->irq_count
= mpic
->num_sources
;
1305 /* Do the HT PIC fixups on U3 broken mpic */
1306 DBG("MPIC flags: %x\n", mpic
->flags
);
1307 if ((mpic
->flags
& MPIC_U3_HT_IRQS
) && (mpic
->flags
& MPIC_PRIMARY
)) {
1308 mpic_scan_ht_pics(mpic
);
1309 mpic_u3msi_init(mpic
);
1312 mpic_pasemi_msi_init(mpic
);
1314 if (mpic
->flags
& MPIC_PRIMARY
)
1315 cpu
= hard_smp_processor_id();
1319 for (i
= 0; i
< mpic
->num_sources
; i
++) {
1320 /* start with vector = source number, and masked */
1321 u32 vecpri
= MPIC_VECPRI_MASK
| i
|
1322 (8 << MPIC_VECPRI_PRIORITY_SHIFT
);
1324 /* check if protected */
1325 if (mpic
->protected && test_bit(i
, mpic
->protected))
1328 mpic_irq_write(i
, MPIC_INFO(IRQ_VECTOR_PRI
), vecpri
);
1329 mpic_irq_write(i
, MPIC_INFO(IRQ_DESTINATION
), 1 << cpu
);
1332 /* Init spurious vector */
1333 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_SPURIOUS
), mpic
->spurious_vec
);
1335 /* Disable 8259 passthrough, if supported */
1336 if (!(mpic
->flags
& MPIC_NO_PTHROU_DIS
))
1337 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
),
1338 mpic_read(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
))
1339 | MPIC_GREG_GCONF_8259_PTHROU_DIS
);
1341 if (mpic
->flags
& MPIC_NO_BIAS
)
1342 mpic_write(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
),
1343 mpic_read(mpic
->gregs
, MPIC_INFO(GREG_GLOBAL_CONF_0
))
1344 | MPIC_GREG_GCONF_NO_BIAS
);
1346 /* Set current processor priority to 0 */
1347 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI
), 0);
1350 /* allocate memory to save mpic state */
1351 mpic
->save_data
= kmalloc(mpic
->num_sources
* sizeof(*mpic
->save_data
),
1353 BUG_ON(mpic
->save_data
== NULL
);
1357 void __init
mpic_set_clk_ratio(struct mpic
*mpic
, u32 clock_ratio
)
1361 v
= mpic_read(mpic
->gregs
, MPIC_GREG_GLOBAL_CONF_1
);
1362 v
&= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK
;
1363 v
|= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio
);
1364 mpic_write(mpic
->gregs
, MPIC_GREG_GLOBAL_CONF_1
, v
);
1367 void __init
mpic_set_serial_int(struct mpic
*mpic
, int enable
)
1369 unsigned long flags
;
1372 raw_spin_lock_irqsave(&mpic_lock
, flags
);
1373 v
= mpic_read(mpic
->gregs
, MPIC_GREG_GLOBAL_CONF_1
);
1375 v
|= MPIC_GREG_GLOBAL_CONF_1_SIE
;
1377 v
&= ~MPIC_GREG_GLOBAL_CONF_1_SIE
;
1378 mpic_write(mpic
->gregs
, MPIC_GREG_GLOBAL_CONF_1
, v
);
1379 raw_spin_unlock_irqrestore(&mpic_lock
, flags
);
1382 void mpic_irq_set_priority(unsigned int irq
, unsigned int pri
)
1384 struct mpic
*mpic
= mpic_find(irq
);
1385 unsigned int src
= mpic_irq_to_hw(irq
);
1386 unsigned long flags
;
1392 raw_spin_lock_irqsave(&mpic_lock
, flags
);
1393 if (mpic_is_ipi(mpic
, irq
)) {
1394 reg
= mpic_ipi_read(src
- mpic
->ipi_vecs
[0]) &
1395 ~MPIC_VECPRI_PRIORITY_MASK
;
1396 mpic_ipi_write(src
- mpic
->ipi_vecs
[0],
1397 reg
| (pri
<< MPIC_VECPRI_PRIORITY_SHIFT
));
1399 reg
= mpic_irq_read(src
, MPIC_INFO(IRQ_VECTOR_PRI
))
1400 & ~MPIC_VECPRI_PRIORITY_MASK
;
1401 mpic_irq_write(src
, MPIC_INFO(IRQ_VECTOR_PRI
),
1402 reg
| (pri
<< MPIC_VECPRI_PRIORITY_SHIFT
));
1404 raw_spin_unlock_irqrestore(&mpic_lock
, flags
);
1407 void mpic_setup_this_cpu(void)
1410 struct mpic
*mpic
= mpic_primary
;
1411 unsigned long flags
;
1412 u32 msk
= 1 << hard_smp_processor_id();
1415 BUG_ON(mpic
== NULL
);
1417 DBG("%s: setup_this_cpu(%d)\n", mpic
->name
, hard_smp_processor_id());
1419 raw_spin_lock_irqsave(&mpic_lock
, flags
);
1421 /* let the mpic know we want intrs. default affinity is 0xffffffff
1422 * until changed via /proc. That's how it's done on x86. If we want
1423 * it differently, then we should make sure we also change the default
1424 * values of irq_desc[].affinity in irq.c.
1426 if (distribute_irqs
) {
1427 for (i
= 0; i
< mpic
->num_sources
; i
++)
1428 mpic_irq_write(i
, MPIC_INFO(IRQ_DESTINATION
),
1429 mpic_irq_read(i
, MPIC_INFO(IRQ_DESTINATION
)) | msk
);
1432 /* Set current processor priority to 0 */
1433 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI
), 0);
1435 raw_spin_unlock_irqrestore(&mpic_lock
, flags
);
1436 #endif /* CONFIG_SMP */
1439 int mpic_cpu_get_priority(void)
1441 struct mpic
*mpic
= mpic_primary
;
1443 return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI
));
1446 void mpic_cpu_set_priority(int prio
)
1448 struct mpic
*mpic
= mpic_primary
;
1450 prio
&= MPIC_CPU_TASKPRI_MASK
;
1451 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI
), prio
);
1454 void mpic_teardown_this_cpu(int secondary
)
1456 struct mpic
*mpic
= mpic_primary
;
1457 unsigned long flags
;
1458 u32 msk
= 1 << hard_smp_processor_id();
1461 BUG_ON(mpic
== NULL
);
1463 DBG("%s: teardown_this_cpu(%d)\n", mpic
->name
, hard_smp_processor_id());
1464 raw_spin_lock_irqsave(&mpic_lock
, flags
);
1466 /* let the mpic know we don't want intrs. */
1467 for (i
= 0; i
< mpic
->num_sources
; i
++)
1468 mpic_irq_write(i
, MPIC_INFO(IRQ_DESTINATION
),
1469 mpic_irq_read(i
, MPIC_INFO(IRQ_DESTINATION
)) & ~msk
);
1471 /* Set current processor priority to max */
1472 mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI
), 0xf);
1473 /* We need to EOI the IPI since not all platforms reset the MPIC
1474 * on boot and new interrupts wouldn't get delivered otherwise.
1478 raw_spin_unlock_irqrestore(&mpic_lock
, flags
);
1482 void mpic_send_ipi(unsigned int ipi_no
, unsigned int cpu_mask
)
1484 struct mpic
*mpic
= mpic_primary
;
1486 BUG_ON(mpic
== NULL
);
1489 DBG("%s: send_ipi(ipi_no: %d)\n", mpic
->name
, ipi_no
);
1492 mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0
) +
1493 ipi_no
* MPIC_INFO(CPU_IPI_DISPATCH_STRIDE
),
1494 mpic_physmask(cpu_mask
& cpus_addr(cpu_online_map
)[0]));
1497 static unsigned int _mpic_get_one_irq(struct mpic
*mpic
, int reg
)
1501 src
= mpic_cpu_read(reg
) & MPIC_INFO(VECPRI_VECTOR_MASK
);
1503 DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic
->name
, reg
, src
);
1505 if (unlikely(src
== mpic
->spurious_vec
)) {
1506 if (mpic
->flags
& MPIC_SPV_EOI
)
1510 if (unlikely(mpic
->protected && test_bit(src
, mpic
->protected))) {
1511 if (printk_ratelimit())
1512 printk(KERN_WARNING
"%s: Got protected source %d !\n",
1513 mpic
->name
, (int)src
);
1518 return irq_linear_revmap(mpic
->irqhost
, src
);
1521 unsigned int mpic_get_one_irq(struct mpic
*mpic
)
1523 return _mpic_get_one_irq(mpic
, MPIC_INFO(CPU_INTACK
));
1526 unsigned int mpic_get_irq(void)
1528 struct mpic
*mpic
= mpic_primary
;
1530 BUG_ON(mpic
== NULL
);
1532 return mpic_get_one_irq(mpic
);
1535 unsigned int mpic_get_coreint_irq(void)
1538 struct mpic
*mpic
= mpic_primary
;
1541 BUG_ON(mpic
== NULL
);
1543 src
= mfspr(SPRN_EPR
);
1545 if (unlikely(src
== mpic
->spurious_vec
)) {
1546 if (mpic
->flags
& MPIC_SPV_EOI
)
1550 if (unlikely(mpic
->protected && test_bit(src
, mpic
->protected))) {
1551 if (printk_ratelimit())
1552 printk(KERN_WARNING
"%s: Got protected source %d !\n",
1553 mpic
->name
, (int)src
);
1557 return irq_linear_revmap(mpic
->irqhost
, src
);
1563 unsigned int mpic_get_mcirq(void)
1565 struct mpic
*mpic
= mpic_primary
;
1567 BUG_ON(mpic
== NULL
);
1569 return _mpic_get_one_irq(mpic
, MPIC_INFO(CPU_MCACK
));
1573 void mpic_request_ipis(void)
1575 struct mpic
*mpic
= mpic_primary
;
1577 BUG_ON(mpic
== NULL
);
1579 printk(KERN_INFO
"mpic: requesting IPIs...\n");
1581 for (i
= 0; i
< 4; i
++) {
1582 unsigned int vipi
= irq_create_mapping(mpic
->irqhost
,
1583 mpic
->ipi_vecs
[0] + i
);
1584 if (vipi
== NO_IRQ
) {
1585 printk(KERN_ERR
"Failed to map %s\n", smp_ipi_name
[i
]);
1588 smp_request_message_ipi(vipi
, i
);
1592 void smp_mpic_message_pass(int target
, int msg
)
1594 /* make sure we're sending something that translates to an IPI */
1595 if ((unsigned int)msg
> 3) {
1596 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1597 smp_processor_id(), msg
);
1602 mpic_send_ipi(msg
, 0xffffffff);
1604 case MSG_ALL_BUT_SELF
:
1605 mpic_send_ipi(msg
, 0xffffffff & ~(1 << smp_processor_id()));
1608 mpic_send_ipi(msg
, 1 << target
);
1613 int __init
smp_mpic_probe(void)
1617 DBG("smp_mpic_probe()...\n");
1619 nr_cpus
= cpus_weight(cpu_possible_map
);
1621 DBG("nr_cpus: %d\n", nr_cpus
);
1624 mpic_request_ipis();
1629 void __devinit
smp_mpic_setup_cpu(int cpu
)
1631 mpic_setup_this_cpu();
1633 #endif /* CONFIG_SMP */
1636 static int mpic_suspend(struct sys_device
*dev
, pm_message_t state
)
1638 struct mpic
*mpic
= container_of(dev
, struct mpic
, sysdev
);
1641 for (i
= 0; i
< mpic
->num_sources
; i
++) {
1642 mpic
->save_data
[i
].vecprio
=
1643 mpic_irq_read(i
, MPIC_INFO(IRQ_VECTOR_PRI
));
1644 mpic
->save_data
[i
].dest
=
1645 mpic_irq_read(i
, MPIC_INFO(IRQ_DESTINATION
));
1651 static int mpic_resume(struct sys_device
*dev
)
1653 struct mpic
*mpic
= container_of(dev
, struct mpic
, sysdev
);
1656 for (i
= 0; i
< mpic
->num_sources
; i
++) {
1657 mpic_irq_write(i
, MPIC_INFO(IRQ_VECTOR_PRI
),
1658 mpic
->save_data
[i
].vecprio
);
1659 mpic_irq_write(i
, MPIC_INFO(IRQ_DESTINATION
),
1660 mpic
->save_data
[i
].dest
);
1662 #ifdef CONFIG_MPIC_U3_HT_IRQS
1664 struct mpic_irq_fixup
*fixup
= &mpic
->fixups
[i
];
1667 /* we use the lowest bit in an inverted meaning */
1668 if ((mpic
->save_data
[i
].fixup_data
& 1) == 0)
1671 /* Enable and configure */
1672 writeb(0x10 + 2 * fixup
->index
, fixup
->base
+ 2);
1674 writel(mpic
->save_data
[i
].fixup_data
& ~1,
1679 } /* end for loop */
1685 static struct sysdev_class mpic_sysclass
= {
1687 .resume
= mpic_resume
,
1688 .suspend
= mpic_suspend
,
1693 static int mpic_init_sys(void)
1695 struct mpic
*mpic
= mpics
;
1698 error
= sysdev_class_register(&mpic_sysclass
);
1700 while (mpic
&& !error
) {
1701 mpic
->sysdev
.cls
= &mpic_sysclass
;
1702 mpic
->sysdev
.id
= id
++;
1703 error
= sysdev_register(&mpic
->sysdev
);
1709 device_initcall(mpic_init_sys
);