arch/powerpc/sysdev/qe_lib/qe.c

   1 /*
   2  * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
   3  *
   4  * Authors:     Shlomi Gridish <gridish@freescale.com>
   5  *              Li Yang <leoli@freescale.com>
   6  * Based on cpm2_common.c from Dan Malek (dmalek@jlc.net)
   7  *
   8  * Description:
   9  * General Purpose functions for the global management of the
  10  * QUICC Engine (QE).
  11  *
  12  * This program is free software; you can redistribute  it and/or modify it
  13  * under  the terms of  the GNU General  Public License as published by the
  14  * Free Software Foundation;  either version 2 of the  License, or (at your
  15  * option) any later version.
  16  */
  17 #include <linux/errno.h>
  18 #include <linux/sched.h>
  19 #include <linux/kernel.h>
  20 #include <linux/param.h>
  21 #include <linux/string.h>
  22 #include <linux/mm.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/bootmem.h>
  25 #include <linux/module.h>
  26 #include <linux/delay.h>
  27 #include <linux/ioport.h>
  28 #include <linux/crc32.h>
  29 #include <asm/irq.h>
  30 #include <asm/page.h>
  31 #include <asm/pgtable.h>
  32 #include <asm/immap_qe.h>
  33 #include <asm/qe.h>
  34 #include <asm/prom.h>
  35 #include <asm/rheap.h>
  36
  37 static void qe_snums_init(void);
  38 static int qe_sdma_init(void);
  39
  40 static DEFINE_SPINLOCK(qe_lock);
  41
  42 /* QE snum state */
  43 enum qe_snum_state {
  44         QE_SNUM_STATE_USED,
  45         QE_SNUM_STATE_FREE
  46 };
  47
  48 /* QE snum */
  49 struct qe_snum {
  50         u8 num;
  51         enum qe_snum_state state;
  52 };
  53
  54 /* We allocate this here because it is used almost exclusively for
  55  * the communication processor devices.
  56  */
  57 struct qe_immap __iomem *qe_immr;
  58 EXPORT_SYMBOL(qe_immr);
  59
  60 static struct qe_snum snums[QE_NUM_OF_SNUM];    /* Dynamically allocated SNUMs */
  61
  62 static phys_addr_t qebase = -1;
  63
  64 phys_addr_t get_qe_base(void)
  65 {
  66         struct device_node *qe;
  67         unsigned int size;
  68         const u32 *prop;
  69
  70         if (qebase != -1)
  71                 return qebase;
  72
  73         qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
  74         if (!qe) {
  75                 qe = of_find_node_by_type(NULL, "qe");
  76                 if (!qe)
  77                         return qebase;
  78         }
  79
  80         prop = of_get_property(qe, "reg", &size);
  81         if (prop && size >= sizeof(*prop))
  82                 qebase = of_translate_address(qe, prop);
  83         of_node_put(qe);
  84
  85         return qebase;
  86 }
  87
  88 EXPORT_SYMBOL(get_qe_base);
  89
  90 void __init qe_reset(void)
  91 {
  92         if (qe_immr == NULL)
  93                 qe_immr = ioremap(get_qe_base(), QE_IMMAP_SIZE);
  94
  95         qe_snums_init();
  96
  97         qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
  98                      QE_CR_PROTOCOL_UNSPECIFIED, 0);
  99
 100         /* Reclaim the MURAM memory for our use. */
 101         qe_muram_init();
 102
 103         if (qe_sdma_init())
 104                 panic("sdma init failed!");
 105 }
 106
 107 int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
 108 {
 109         unsigned long flags;
 110         u8 mcn_shift = 0, dev_shift = 0;
 111
 112         spin_lock_irqsave(&qe_lock, flags);
 113         if (cmd == QE_RESET) {
 114                 out_be32(&qe_immr->cp.cecr, (u32) (cmd | QE_CR_FLG));
 115         } else {
 116                 if (cmd == QE_ASSIGN_PAGE) {
 117                         /* Here device is the SNUM, not sub-block */
 118                         dev_shift = QE_CR_SNUM_SHIFT;
 119                 } else if (cmd == QE_ASSIGN_RISC) {
 120                         /* Here device is the SNUM, and mcnProtocol is
 121                          * e_QeCmdRiscAssignment value */
 122                         dev_shift = QE_CR_SNUM_SHIFT;
 123                         mcn_shift = QE_CR_MCN_RISC_ASSIGN_SHIFT;
 124                 } else {
 125                         if (device == QE_CR_SUBBLOCK_USB)
 126                                 mcn_shift = QE_CR_MCN_USB_SHIFT;
 127                         else
 128                                 mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
 129                 }
 130
 131                 out_be32(&qe_immr->cp.cecdr, cmd_input);
 132                 out_be32(&qe_immr->cp.cecr,
 133                          (cmd | QE_CR_FLG | ((u32) device << dev_shift) | (u32)
 134                           mcn_protocol << mcn_shift));
 135         }
 136
 137         /* wait for the QE_CR_FLG to clear */
 138         while(in_be32(&qe_immr->cp.cecr) & QE_CR_FLG)
 139                 cpu_relax();
 140         spin_unlock_irqrestore(&qe_lock, flags);
 141
 142         return 0;
 143 }
 144 EXPORT_SYMBOL(qe_issue_cmd);
 145
 146 /* Set a baud rate generator. This needs lots of work. There are
 147  * 16 BRGs, which can be connected to the QE channels or output
 148  * as clocks. The BRGs are in two different block of internal
 149  * memory mapped space.
 150  * The BRG clock is the QE clock divided by 2.
 151  * It was set up long ago during the initial boot phase and is
 152  * is given to us.
 153  * Baud rate clocks are zero-based in the driver code (as that maps
 154  * to port numbers). Documentation uses 1-based numbering.
 155  */
 156 static unsigned int brg_clk = 0;
 157
 158 unsigned int qe_get_brg_clk(void)
 159 {
 160         struct device_node *qe;
 161         unsigned int size;
 162         const u32 *prop;
 163
 164         if (brg_clk)
 165                 return brg_clk;
 166
 167         qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
 168         if (!qe) {
 169                 qe = of_find_node_by_type(NULL, "qe");
 170                 if (!qe)
 171                         return brg_clk;
 172         }
 173
 174         prop = of_get_property(qe, "brg-frequency", &size);
 175         if (prop && size == sizeof(*prop))
 176                 brg_clk = *prop;
 177
 178         of_node_put(qe);
 179
 180         return brg_clk;
 181 }
 182 EXPORT_SYMBOL(qe_get_brg_clk);
 183
 184 /* Program the BRG to the given sampling rate and multiplier
 185  *
 186  * @brg: the BRG, QE_BRG1 - QE_BRG16
 187  * @rate: the desired sampling rate
 188  * @multiplier: corresponds to the value programmed in GUMR_L[RDCR] or
 189  * GUMR_L[TDCR].  E.g., if this BRG is the RX clock, and GUMR_L[RDCR]=01,
 190  * then 'multiplier' should be 8.
 191  */
 192 int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
 193 {
 194         u32 divisor, tempval;
 195         u32 div16 = 0;
 196
 197         if ((brg < QE_BRG1) || (brg > QE_BRG16))
 198                 return -EINVAL;
 199
 200         divisor = qe_get_brg_clk() / (rate * multiplier);
 201
 202         if (divisor > QE_BRGC_DIVISOR_MAX + 1) {
 203                 div16 = QE_BRGC_DIV16;
 204                 divisor /= 16;
 205         }
 206
 207         /* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
 208            that the BRG divisor must be even if you're not using divide-by-16
 209            mode. */
 210         if (!div16 && (divisor & 1))
 211                 divisor++;
 212
 213         tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
 214                 QE_BRGC_ENABLE | div16;
 215
 216         out_be32(&qe_immr->brg.brgc[brg - QE_BRG1], tempval);
 217
 218         return 0;
 219 }
 220 EXPORT_SYMBOL(qe_setbrg);
 221
 222 /* Convert a string to a QE clock source enum
 223  *
 224  * This function takes a string, typically from a property in the device
 225  * tree, and returns the corresponding "enum qe_clock" value.
 226 */
 227 enum qe_clock qe_clock_source(const char *source)
 228 {
 229         unsigned int i;
 230
 231         if (strcasecmp(source, "none") == 0)
 232                 return QE_CLK_NONE;
 233
 234         if (strncasecmp(source, "brg", 3) == 0) {
 235                 i = simple_strtoul(source + 3, NULL, 10);
 236                 if ((i >= 1) && (i <= 16))
 237                         return (QE_BRG1 - 1) + i;
 238                 else
 239                         return QE_CLK_DUMMY;
 240         }
 241
 242         if (strncasecmp(source, "clk", 3) == 0) {
 243                 i = simple_strtoul(source + 3, NULL, 10);
 244                 if ((i >= 1) && (i <= 24))
 245                         return (QE_CLK1 - 1) + i;
 246                 else
 247                         return QE_CLK_DUMMY;
 248         }
 249
 250         return QE_CLK_DUMMY;
 251 }
 252 EXPORT_SYMBOL(qe_clock_source);
 253
 254 /* Initialize SNUMs (thread serial numbers) according to
 255  * QE Module Control chapter, SNUM table
 256  */
 257 static void qe_snums_init(void)
 258 {
 259         int i;
 260         static const u8 snum_init[] = {
 261                 0x04, 0x05, 0x0C, 0x0D, 0x14, 0x15, 0x1C, 0x1D,
 262                 0x24, 0x25, 0x2C, 0x2D, 0x34, 0x35, 0x88, 0x89,
 263                 0x98, 0x99, 0xA8, 0xA9, 0xB8, 0xB9, 0xC8, 0xC9,
 264                 0xD8, 0xD9, 0xE8, 0xE9,
 265         };
 266
 267         for (i = 0; i < QE_NUM_OF_SNUM; i++) {
 268                 snums[i].num = snum_init[i];
 269                 snums[i].state = QE_SNUM_STATE_FREE;
 270         }
 271 }
 272
 273 int qe_get_snum(void)
 274 {
 275         unsigned long flags;
 276         int snum = -EBUSY;
 277         int i;
 278
 279         spin_lock_irqsave(&qe_lock, flags);
 280         for (i = 0; i < QE_NUM_OF_SNUM; i++) {
 281                 if (snums[i].state == QE_SNUM_STATE_FREE) {
 282                         snums[i].state = QE_SNUM_STATE_USED;
 283                         snum = snums[i].num;
 284                         break;
 285                 }
 286         }
 287         spin_unlock_irqrestore(&qe_lock, flags);
 288
 289         return snum;
 290 }
 291 EXPORT_SYMBOL(qe_get_snum);
 292
 293 void qe_put_snum(u8 snum)
 294 {
 295         int i;
 296
 297         for (i = 0; i < QE_NUM_OF_SNUM; i++) {
 298                 if (snums[i].num == snum) {
 299                         snums[i].state = QE_SNUM_STATE_FREE;
 300                         break;
 301                 }
 302         }
 303 }
 304 EXPORT_SYMBOL(qe_put_snum);
 305
 306 static int qe_sdma_init(void)
 307 {
 308         struct sdma *sdma = &qe_immr->sdma;
 309         unsigned long sdma_buf_offset;
 310
 311         if (!sdma)
 312                 return -ENODEV;
 313
 314         /* allocate 2 internal temporary buffers (512 bytes size each) for
 315          * the SDMA */
 316         sdma_buf_offset = qe_muram_alloc(512 * 2, 4096);
 317         if (IS_ERR_VALUE(sdma_buf_offset))
 318                 return -ENOMEM;
 319
 320         out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);
 321         out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
 322                                         (0x1 << QE_SDMR_CEN_SHIFT)));
 323
 324         return 0;
 325 }
 326
 327 /* The maximum number of RISCs we support */
 328 #define MAX_QE_RISC     2
 329
 330 /* Firmware information stored here for qe_get_firmware_info() */
 331 static struct qe_firmware_info qe_firmware_info;
 332
 333 /*
 334  * Set to 1 if QE firmware has been uploaded, and therefore
 335  * qe_firmware_info contains valid data.
 336  */
 337 static int qe_firmware_uploaded;
 338
 339 /*
 340  * Upload a QE microcode
 341  *
 342  * This function is a worker function for qe_upload_firmware().  It does
 343  * the actual uploading of the microcode.
 344  */
 345 static void qe_upload_microcode(const void *base,
 346         const struct qe_microcode *ucode)
 347 {
 348         const __be32 *code = base + be32_to_cpu(ucode->code_offset);
 349         unsigned int i;
 350
 351         if (ucode->major || ucode->minor || ucode->revision)
 352                 printk(KERN_INFO "qe-firmware: "
 353                         "uploading microcode '%s' version %u.%u.%u\n",
 354                         ucode->id, ucode->major, ucode->minor, ucode->revision);
 355         else
 356                 printk(KERN_INFO "qe-firmware: "
 357                         "uploading microcode '%s'\n", ucode->id);
 358
 359         /* Use auto-increment */
 360         out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
 361                 QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
 362
 363         for (i = 0; i < be32_to_cpu(ucode->count); i++)
 364                 out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
 365 }
 366
 367 /*
 368  * Upload a microcode to the I-RAM at a specific address.
 369  *
 370  * See Documentation/powerpc/qe-firmware.txt for information on QE microcode
 371  * uploading.
 372  *
 373  * Currently, only version 1 is supported, so the 'version' field must be
 374  * set to 1.
 375  *
 376  * The SOC model and revision are not validated, they are only displayed for
 377  * informational purposes.
 378  *
 379  * 'calc_size' is the calculated size, in bytes, of the firmware structure and
 380  * all of the microcode structures, minus the CRC.
 381  *
 382  * 'length' is the size that the structure says it is, including the CRC.
 383  */
 384 int qe_upload_firmware(const struct qe_firmware *firmware)
 385 {
 386         unsigned int i;
 387         unsigned int j;
 388         u32 crc;
 389         size_t calc_size = sizeof(struct qe_firmware);
 390         size_t length;
 391         const struct qe_header *hdr;
 392
 393         if (!firmware) {
 394                 printk(KERN_ERR "qe-firmware: invalid pointer\n");
 395                 return -EINVAL;
 396         }
 397
 398         hdr = &firmware->header;
 399         length = be32_to_cpu(hdr->length);
 400
 401         /* Check the magic */
 402         if ((hdr->magic[0] != 'Q') || (hdr->magic[1] != 'E') ||
 403             (hdr->magic[2] != 'F')) {
 404                 printk(KERN_ERR "qe-firmware: not a microcode\n");
 405                 return -EPERM;
 406         }
 407
 408         /* Check the version */
 409         if (hdr->version != 1) {
 410                 printk(KERN_ERR "qe-firmware: unsupported version\n");
 411                 return -EPERM;
 412         }
 413
 414         /* Validate some of the fields */
 415         if ((firmware->count < 1) || (firmware->count > MAX_QE_RISC)) {
 416                 printk(KERN_ERR "qe-firmware: invalid data\n");
 417                 return -EINVAL;
 418         }
 419
 420         /* Validate the length and check if there's a CRC */
 421         calc_size += (firmware->count - 1) * sizeof(struct qe_microcode);
 422
 423         for (i = 0; i < firmware->count; i++)
 424                 /*
 425                  * For situations where the second RISC uses the same microcode
 426                  * as the first, the 'code_offset' and 'count' fields will be
 427                  * zero, so it's okay to add those.
 428                  */
 429                 calc_size += sizeof(__be32) *
 430                         be32_to_cpu(firmware->microcode[i].count);
 431
 432         /* Validate the length */
 433         if (length != calc_size + sizeof(__be32)) {
 434                 printk(KERN_ERR "qe-firmware: invalid length\n");
 435                 return -EPERM;
 436         }
 437
 438         /* Validate the CRC */
 439         crc = be32_to_cpu(*(__be32 *)((void *)firmware + calc_size));
 440         if (crc != crc32(0, firmware, calc_size)) {
 441                 printk(KERN_ERR "qe-firmware: firmware CRC is invalid\n");
 442                 return -EIO;
 443         }
 444
 445         /*
 446          * If the microcode calls for it, split the I-RAM.
 447          */
 448         if (!firmware->split)
 449                 setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
 450
 451         if (firmware->soc.model)
 452                 printk(KERN_INFO
 453                         "qe-firmware: firmware '%s' for %u V%u.%u\n",
 454                         firmware->id, be16_to_cpu(firmware->soc.model),
 455                         firmware->soc.major, firmware->soc.minor);
 456         else
 457                 printk(KERN_INFO "qe-firmware: firmware '%s'\n",
 458                         firmware->id);
 459
 460         /*
 461          * The QE only supports one microcode per RISC, so clear out all the
 462          * saved microcode information and put in the new.
 463          */
 464         memset(&qe_firmware_info, 0, sizeof(qe_firmware_info));
 465         strcpy(qe_firmware_info.id, firmware->id);
 466         qe_firmware_info.extended_modes = firmware->extended_modes;
 467         memcpy(qe_firmware_info.vtraps, firmware->vtraps,
 468                 sizeof(firmware->vtraps));
 469
 470         /* Loop through each microcode. */
 471         for (i = 0; i < firmware->count; i++) {
 472                 const struct qe_microcode *ucode = &firmware->microcode[i];
 473
 474                 /* Upload a microcode if it's present */
 475                 if (ucode->code_offset)
 476                         qe_upload_microcode(firmware, ucode);
 477
 478                 /* Program the traps for this processor */
 479                 for (j = 0; j < 16; j++) {
 480                         u32 trap = be32_to_cpu(ucode->traps[j]);
 481
 482                         if (trap)
 483                                 out_be32(&qe_immr->rsp[i].tibcr[j], trap);
 484                 }
 485
 486                 /* Enable traps */
 487                 out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
 488         }
 489
 490         qe_firmware_uploaded = 1;
 491
 492         return 0;
 493 }
 494 EXPORT_SYMBOL(qe_upload_firmware);
 495
 496 /*
 497  * Get info on the currently-loaded firmware
 498  *
 499  * This function also checks the device tree to see if the boot loader has
 500  * uploaded a firmware already.
 501  */
 502 struct qe_firmware_info *qe_get_firmware_info(void)
 503 {
 504         static int initialized;
 505         struct property *prop;
 506         struct device_node *qe;
 507         struct device_node *fw = NULL;
 508         const char *sprop;
 509         unsigned int i;
 510
 511         /*
 512          * If we haven't checked yet, and a driver hasn't uploaded a firmware
 513          * yet, then check the device tree for information.
 514          */
 515         if (qe_firmware_uploaded)
 516                 return &qe_firmware_info;
 517
 518         if (initialized)
 519                 return NULL;
 520
 521         initialized = 1;
 522
 523         /*
 524          * Newer device trees have an "fsl,qe" compatible property for the QE
 525          * node, but we still need to support older device trees.
 526         */
 527         qe = of_find_compatible_node(NULL, NULL, "fsl,qe");
 528         if (!qe) {
 529                 qe = of_find_node_by_type(NULL, "qe");
 530                 if (!qe)
 531                         return NULL;
 532         }
 533
 534         /* Find the 'firmware' child node */
 535         for_each_child_of_node(qe, fw) {
 536                 if (strcmp(fw->name, "firmware") == 0)
 537                         break;
 538         }
 539
 540         of_node_put(qe);
 541
 542         /* Did we find the 'firmware' node? */
 543         if (!fw)
 544                 return NULL;
 545
 546         qe_firmware_uploaded = 1;
 547
 548         /* Copy the data into qe_firmware_info*/
 549         sprop = of_get_property(fw, "id", NULL);
 550         if (sprop)
 551                 strncpy(qe_firmware_info.id, sprop,
 552                         sizeof(qe_firmware_info.id) - 1);
 553
 554         prop = of_find_property(fw, "extended-modes", NULL);
 555         if (prop && (prop->length == sizeof(u64))) {
 556                 const u64 *iprop = prop->value;
 557
 558                 qe_firmware_info.extended_modes = *iprop;
 559         }
 560
 561         prop = of_find_property(fw, "virtual-traps", NULL);
 562         if (prop && (prop->length == 32)) {
 563                 const u32 *iprop = prop->value;
 564
 565                 for (i = 0; i < ARRAY_SIZE(qe_firmware_info.vtraps); i++)
 566                         qe_firmware_info.vtraps[i] = iprop[i];
 567         }
 568
 569         of_node_put(fw);
 570
 571         return &qe_firmware_info;
 572 }
 573 EXPORT_SYMBOL(qe_get_firmware_info);
 574