2 * arch/powerpc/sysdev/uic.c
4 * IBM PowerPC 4xx Universal Interrupt Controller
6 * Copyright 2007 David Gibson <dwg@au1.ibm.com>, IBM Corporation.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 #include <linux/kernel.h>
14 #include <linux/init.h>
15 #include <linux/errno.h>
16 #include <linux/reboot.h>
17 #include <linux/slab.h>
18 #include <linux/stddef.h>
19 #include <linux/sched.h>
20 #include <linux/signal.h>
21 #include <linux/sysdev.h>
22 #include <linux/device.h>
23 #include <linux/bootmem.h>
24 #include <linux/spinlock.h>
25 #include <linux/irq.h>
26 #include <linux/interrupt.h>
27 #include <linux/kernel_stat.h>
33 #define NR_UIC_INTS 32
44 #define uic_irq_to_hw(virq) (irq_map[virq].hwirq)
46 struct uic
*primary_uic
;
54 /* The remapper for this UIC */
55 struct irq_host
*irqhost
;
58 static void uic_unmask_irq(struct irq_data
*d
)
60 struct uic
*uic
= irq_data_get_irq_chip_data(d
);
61 unsigned int src
= uic_irq_to_hw(d
->irq
);
66 spin_lock_irqsave(&uic
->lock
, flags
);
67 /* ack level-triggered interrupts here */
68 if (irqd_is_level_type(d
))
69 mtdcr(uic
->dcrbase
+ UIC_SR
, sr
);
70 er
= mfdcr(uic
->dcrbase
+ UIC_ER
);
72 mtdcr(uic
->dcrbase
+ UIC_ER
, er
);
73 spin_unlock_irqrestore(&uic
->lock
, flags
);
76 static void uic_mask_irq(struct irq_data
*d
)
78 struct uic
*uic
= irq_data_get_irq_chip_data(d
);
79 unsigned int src
= uic_irq_to_hw(d
->irq
);
83 spin_lock_irqsave(&uic
->lock
, flags
);
84 er
= mfdcr(uic
->dcrbase
+ UIC_ER
);
85 er
&= ~(1 << (31 - src
));
86 mtdcr(uic
->dcrbase
+ UIC_ER
, er
);
87 spin_unlock_irqrestore(&uic
->lock
, flags
);
90 static void uic_ack_irq(struct irq_data
*d
)
92 struct uic
*uic
= irq_data_get_irq_chip_data(d
);
93 unsigned int src
= uic_irq_to_hw(d
->irq
);
96 spin_lock_irqsave(&uic
->lock
, flags
);
97 mtdcr(uic
->dcrbase
+ UIC_SR
, 1 << (31-src
));
98 spin_unlock_irqrestore(&uic
->lock
, flags
);
101 static void uic_mask_ack_irq(struct irq_data
*d
)
103 struct uic
*uic
= irq_data_get_irq_chip_data(d
);
104 unsigned int src
= uic_irq_to_hw(d
->irq
);
109 spin_lock_irqsave(&uic
->lock
, flags
);
110 er
= mfdcr(uic
->dcrbase
+ UIC_ER
);
112 mtdcr(uic
->dcrbase
+ UIC_ER
, er
);
113 /* On the UIC, acking (i.e. clearing the SR bit)
114 * a level irq will have no effect if the interrupt
115 * is still asserted by the device, even if
116 * the interrupt is already masked. Therefore
117 * we only ack the egde interrupts here, while
118 * level interrupts are ack'ed after the actual
119 * isr call in the uic_unmask_irq()
121 if (!irqd_is_level_type(d
))
122 mtdcr(uic
->dcrbase
+ UIC_SR
, sr
);
123 spin_unlock_irqrestore(&uic
->lock
, flags
);
126 static int uic_set_irq_type(struct irq_data
*d
, unsigned int flow_type
)
128 struct uic
*uic
= irq_data_get_irq_chip_data(d
);
129 unsigned int src
= uic_irq_to_hw(d
->irq
);
131 int trigger
, polarity
;
134 switch (flow_type
& IRQ_TYPE_SENSE_MASK
) {
139 case IRQ_TYPE_EDGE_RISING
:
140 trigger
= 1; polarity
= 1;
142 case IRQ_TYPE_EDGE_FALLING
:
143 trigger
= 1; polarity
= 0;
145 case IRQ_TYPE_LEVEL_HIGH
:
146 trigger
= 0; polarity
= 1;
148 case IRQ_TYPE_LEVEL_LOW
:
149 trigger
= 0; polarity
= 0;
155 mask
= ~(1 << (31 - src
));
157 spin_lock_irqsave(&uic
->lock
, flags
);
158 tr
= mfdcr(uic
->dcrbase
+ UIC_TR
);
159 pr
= mfdcr(uic
->dcrbase
+ UIC_PR
);
160 tr
= (tr
& mask
) | (trigger
<< (31-src
));
161 pr
= (pr
& mask
) | (polarity
<< (31-src
));
163 mtdcr(uic
->dcrbase
+ UIC_PR
, pr
);
164 mtdcr(uic
->dcrbase
+ UIC_TR
, tr
);
166 spin_unlock_irqrestore(&uic
->lock
, flags
);
171 static struct irq_chip uic_irq_chip
= {
173 .irq_unmask
= uic_unmask_irq
,
174 .irq_mask
= uic_mask_irq
,
175 .irq_mask_ack
= uic_mask_ack_irq
,
176 .irq_ack
= uic_ack_irq
,
177 .irq_set_type
= uic_set_irq_type
,
180 static int uic_host_map(struct irq_host
*h
, unsigned int virq
,
183 struct uic
*uic
= h
->host_data
;
185 irq_set_chip_data(virq
, uic
);
186 /* Despite the name, handle_level_irq() works for both level
187 * and edge irqs on UIC. FIXME: check this is correct */
188 irq_set_chip_and_handler(virq
, &uic_irq_chip
, handle_level_irq
);
190 /* Set default irq type */
191 irq_set_irq_type(virq
, IRQ_TYPE_NONE
);
196 static int uic_host_xlate(struct irq_host
*h
, struct device_node
*ct
,
197 const u32
*intspec
, unsigned int intsize
,
198 irq_hw_number_t
*out_hwirq
, unsigned int *out_type
)
201 /* UIC intspecs must have 2 cells */
202 BUG_ON(intsize
!= 2);
203 *out_hwirq
= intspec
[0];
204 *out_type
= intspec
[1];
208 static struct irq_host_ops uic_host_ops
= {
210 .xlate
= uic_host_xlate
,
213 void uic_irq_cascade(unsigned int virq
, struct irq_desc
*desc
)
215 struct irq_chip
*chip
= irq_desc_get_chip(desc
);
216 struct irq_data
*idata
= irq_desc_get_irq_data(desc
);
217 struct uic
*uic
= irq_get_handler_data(virq
);
222 raw_spin_lock(&desc
->lock
);
223 if (irqd_is_level_type(idata
))
224 chip
->irq_mask(idata
);
226 chip
->irq_mask_ack(idata
);
227 raw_spin_unlock(&desc
->lock
);
229 msr
= mfdcr(uic
->dcrbase
+ UIC_MSR
);
230 if (!msr
) /* spurious interrupt */
235 subvirq
= irq_linear_revmap(uic
->irqhost
, src
);
236 generic_handle_irq(subvirq
);
239 raw_spin_lock(&desc
->lock
);
240 if (irqd_is_level_type(idata
))
241 chip
->irq_ack(idata
);
242 if (!irqd_irq_disabled(idata
) && chip
->irq_unmask
)
243 chip
->irq_unmask(idata
);
244 raw_spin_unlock(&desc
->lock
);
247 static struct uic
* __init
uic_init_one(struct device_node
*node
)
250 const u32
*indexp
, *dcrreg
;
253 BUG_ON(! of_device_is_compatible(node
, "ibm,uic"));
255 uic
= kzalloc(sizeof(*uic
), GFP_KERNEL
);
257 return NULL
; /* FIXME: panic? */
259 spin_lock_init(&uic
->lock
);
260 indexp
= of_get_property(node
, "cell-index", &len
);
261 if (!indexp
|| (len
!= sizeof(u32
))) {
262 printk(KERN_ERR
"uic: Device node %s has missing or invalid "
263 "cell-index property\n", node
->full_name
);
266 uic
->index
= *indexp
;
268 dcrreg
= of_get_property(node
, "dcr-reg", &len
);
269 if (!dcrreg
|| (len
!= 2*sizeof(u32
))) {
270 printk(KERN_ERR
"uic: Device node %s has missing or invalid "
271 "dcr-reg property\n", node
->full_name
);
274 uic
->dcrbase
= *dcrreg
;
276 uic
->irqhost
= irq_alloc_host(node
, IRQ_HOST_MAP_LINEAR
,
277 NR_UIC_INTS
, &uic_host_ops
, -1);
279 return NULL
; /* FIXME: panic? */
281 uic
->irqhost
->host_data
= uic
;
283 /* Start with all interrupts disabled, level and non-critical */
284 mtdcr(uic
->dcrbase
+ UIC_ER
, 0);
285 mtdcr(uic
->dcrbase
+ UIC_CR
, 0);
286 mtdcr(uic
->dcrbase
+ UIC_TR
, 0);
287 /* Clear any pending interrupts, in case the firmware left some */
288 mtdcr(uic
->dcrbase
+ UIC_SR
, 0xffffffff);
290 printk ("UIC%d (%d IRQ sources) at DCR 0x%x\n", uic
->index
,
291 NR_UIC_INTS
, uic
->dcrbase
);
296 void __init
uic_init_tree(void)
298 struct device_node
*np
;
300 const u32
*interrupts
;
302 /* First locate and initialize the top-level UIC */
303 for_each_compatible_node(np
, NULL
, "ibm,uic") {
304 interrupts
= of_get_property(np
, "interrupts", NULL
);
309 BUG_ON(!np
); /* uic_init_tree() assumes there's a UIC as the
310 * top-level interrupt controller */
311 primary_uic
= uic_init_one(np
);
313 panic("Unable to initialize primary UIC %s\n", np
->full_name
);
315 irq_set_default_host(primary_uic
->irqhost
);
318 /* The scan again for cascaded UICs */
319 for_each_compatible_node(np
, NULL
, "ibm,uic") {
320 interrupts
= of_get_property(np
, "interrupts", NULL
);
325 uic
= uic_init_one(np
);
327 panic("Unable to initialize a secondary UIC %s\n",
330 cascade_virq
= irq_of_parse_and_map(np
, 0);
332 irq_set_handler_data(cascade_virq
, uic
);
333 irq_set_chained_handler(cascade_virq
, uic_irq_cascade
);
335 /* FIXME: setup critical cascade?? */
340 /* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
341 unsigned int uic_get_irq(void)
346 BUG_ON(! primary_uic
);
348 msr
= mfdcr(primary_uic
->dcrbase
+ UIC_MSR
);
351 return irq_linear_revmap(primary_uic
->irqhost
, src
);