arch/powerpc/sysdev/xics/icp-opal.c

   1 /*
   2  * Copyright 2016 IBM Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version
   7  * 2 of the License, or (at your option) any later version.
   8  */
   9 #include <linux/types.h>
  10 #include <linux/kernel.h>
  11 #include <linux/irq.h>
  12 #include <linux/smp.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/cpu.h>
  15 #include <linux/of.h>
  16
  17 #include <asm/smp.h>
  18 #include <asm/irq.h>
  19 #include <asm/errno.h>
  20 #include <asm/xics.h>
  21 #include <asm/io.h>
  22 #include <asm/opal.h>
  23 #include <asm/kvm_ppc.h>
  24
  25 static void icp_opal_teardown_cpu(void)
  26 {
  27         int hw_cpu = hard_smp_processor_id();
  28
  29         /* Clear any pending IPI */
  30         opal_int_set_mfrr(hw_cpu, 0xff);
  31 }
  32
  33 static void icp_opal_flush_ipi(void)
  34 {
  35         /*
  36          * We take the ipi irq but and never return so we need to EOI the IPI,
  37          * but want to leave our priority 0.
  38          *
  39          * Should we check all the other interrupts too?
  40          * Should we be flagging idle loop instead?
  41          * Or creating some task to be scheduled?
  42          */
  43         if (opal_int_eoi((0x00 << 24) | XICS_IPI) > 0)
  44                 force_external_irq_replay();
  45 }
  46
  47 static unsigned int icp_opal_get_xirr(void)
  48 {
  49         unsigned int kvm_xirr;
  50         __be32 hw_xirr;
  51         int64_t rc;
  52
  53         /* Handle an interrupt latched by KVM first */
  54         kvm_xirr = kvmppc_get_xics_latch();
  55         if (kvm_xirr)
  56                 return kvm_xirr;
  57
  58         /* Then ask OPAL */
  59         rc = opal_int_get_xirr(&hw_xirr, false);
  60         if (rc < 0)
  61                 return 0;
  62         return be32_to_cpu(hw_xirr);
  63 }
  64
  65 static unsigned int icp_opal_get_irq(void)
  66 {
  67         unsigned int xirr;
  68         unsigned int vec;
  69         unsigned int irq;
  70
  71         xirr = icp_opal_get_xirr();
  72         vec = xirr & 0x00ffffff;
  73         if (vec == XICS_IRQ_SPURIOUS)
  74                 return 0;
  75
  76         irq = irq_find_mapping(xics_host, vec);
  77         if (likely(irq)) {
  78                 xics_push_cppr(vec);
  79                 return irq;
  80         }
  81
  82         /* We don't have a linux mapping, so have rtas mask it. */
  83         xics_mask_unknown_vec(vec);
  84
  85         /* We might learn about it later, so EOI it */
  86         if (opal_int_eoi(xirr) > 0)
  87                 force_external_irq_replay();
  88
  89         return 0;
  90 }
  91
  92 static void icp_opal_set_cpu_priority(unsigned char cppr)
  93 {
  94         xics_set_base_cppr(cppr);
  95         opal_int_set_cppr(cppr);
  96         iosync();
  97 }
  98
  99 static void icp_opal_eoi(struct irq_data *d)
 100 {
 101         unsigned int hw_irq = (unsigned int)irqd_to_hwirq(d);
 102         int64_t rc;
 103
 104         iosync();
 105         rc = opal_int_eoi((xics_pop_cppr() << 24) | hw_irq);
 106
 107         /*
 108          * EOI tells us whether there are more interrupts to fetch.
 109          *
 110          * Some HW implementations might not be able to send us another
 111          * external interrupt in that case, so we force a replay.
 112          */
 113         if (rc > 0)
 114                 force_external_irq_replay();
 115 }
 116
 117 #ifdef CONFIG_SMP
 118
 119 static void icp_opal_cause_ipi(int cpu, unsigned long data)
 120 {
 121         int hw_cpu = get_hard_smp_processor_id(cpu);
 122
 123         kvmppc_set_host_ipi(cpu, 1);
 124         opal_int_set_mfrr(hw_cpu, IPI_PRIORITY);
 125 }
 126
 127 static irqreturn_t icp_opal_ipi_action(int irq, void *dev_id)
 128 {
 129         int cpu = smp_processor_id();
 130
 131         kvmppc_set_host_ipi(cpu, 0);
 132         opal_int_set_mfrr(get_hard_smp_processor_id(cpu), 0xff);
 133
 134         return smp_ipi_demux();
 135 }
 136
 137 /*
 138  * Called when an interrupt is received on an off-line CPU to
 139  * clear the interrupt, so that the CPU can go back to nap mode.
 140  */
 141 void icp_opal_flush_interrupt(void)
 142 {
 143         unsigned int xirr;
 144         unsigned int vec;
 145
 146         do {
 147                 xirr = icp_opal_get_xirr();
 148                 vec = xirr & 0x00ffffff;
 149                 if (vec == XICS_IRQ_SPURIOUS)
 150                         break;
 151                 if (vec == XICS_IPI) {
 152                         /* Clear pending IPI */
 153                         int cpu = smp_processor_id();
 154                         kvmppc_set_host_ipi(cpu, 0);
 155                         opal_int_set_mfrr(get_hard_smp_processor_id(cpu), 0xff);
 156                 } else {
 157                         pr_err("XICS: hw interrupt 0x%x to offline cpu, "
 158                                "disabling\n", vec);
 159                         xics_mask_unknown_vec(vec);
 160                 }
 161
 162                 /* EOI the interrupt */
 163         } while (opal_int_eoi(xirr) > 0);
 164 }
 165
 166 #endif /* CONFIG_SMP */
 167
 168 static const struct icp_ops icp_opal_ops = {
 169         .get_irq        = icp_opal_get_irq,
 170         .eoi            = icp_opal_eoi,
 171         .set_priority   = icp_opal_set_cpu_priority,
 172         .teardown_cpu   = icp_opal_teardown_cpu,
 173         .flush_ipi      = icp_opal_flush_ipi,
 174 #ifdef CONFIG_SMP
 175         .ipi_action     = icp_opal_ipi_action,
 176         .cause_ipi      = icp_opal_cause_ipi,
 177 #endif
 178 };
 179
 180 int icp_opal_init(void)
 181 {
 182         struct device_node *np;
 183
 184         np = of_find_compatible_node(NULL, NULL, "ibm,opal-intc");
 185         if (!np)
 186                 return -ENODEV;
 187
 188         icp_ops = &icp_opal_ops;
 189
 190         printk("XICS: Using OPAL ICP fallbacks\n");
 191
 192         return 0;
 193 }
 194