arch/ppc/kernel/head.S

   1 /*
   2  *  PowerPC version
   3  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   4  *
   5  *  Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
   6  *    Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
   7  *  Adapted for Power Macintosh by Paul Mackerras.
   8  *  Low-level exception handlers and MMU support
   9  *  rewritten by Paul Mackerras.
  10  *    Copyright (C) 1996 Paul Mackerras.
  11  *  MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
  12  *  Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
  13  *
  14  *  This file contains the low-level support and setup for the
  15  *  PowerPC platform, including trap and interrupt dispatch.
  16  *  (The PPC 8xx embedded CPUs use head_8xx.S instead.)
  17  *
  18  *  This program is free software; you can redistribute it and/or
  19  *  modify it under the terms of the GNU General Public License
  20  *  as published by the Free Software Foundation; either version
  21  *  2 of the License, or (at your option) any later version.
  22  *
  23  */
  24
  25 #include <asm/processor.h>
  26 #include <asm/page.h>
  27 #include <asm/mmu.h>
  28 #include <asm/pgtable.h>
  29 #include <asm/cputable.h>
  30 #include <asm/cache.h>
  31 #include <asm/thread_info.h>
  32 #include <asm/ppc_asm.h>
  33 #include <asm/asm-offsets.h>
  34
  35 /* 601 only have IBAT; cr0.eq is set on 601 when using this macro */
  36 #define LOAD_BAT(n, reg, RA, RB)        \
  37         /* see the comment for clear_bats() -- Cort */ \
  38         li      RA,0;                   \
  39         mtspr   SPRN_IBAT##n##U,RA;     \
  40         mtspr   SPRN_DBAT##n##U,RA;     \
  41         lwz     RA,(n*16)+0(reg);       \
  42         lwz     RB,(n*16)+4(reg);       \
  43         mtspr   SPRN_IBAT##n##U,RA;     \
  44         mtspr   SPRN_IBAT##n##L,RB;     \
  45         beq     1f;                     \
  46         lwz     RA,(n*16)+8(reg);       \
  47         lwz     RB,(n*16)+12(reg);      \
  48         mtspr   SPRN_DBAT##n##U,RA;     \
  49         mtspr   SPRN_DBAT##n##L,RB;     \
  50 1:
  51
  52         .text
  53         .stabs  "arch/ppc/kernel/",N_SO,0,0,0f
  54         .stabs  "head.S",N_SO,0,0,0f
  55 0:
  56         .globl  _stext
  57 _stext:
  58
  59 /*
  60  * _start is defined this way because the XCOFF loader in the OpenFirmware
  61  * on the powermac expects the entry point to be a procedure descriptor.
  62  */
  63         .text
  64         .globl  _start
  65 _start:
  66         /*
  67          * These are here for legacy reasons, the kernel used to
  68          * need to look like a coff function entry for the pmac
  69          * but we're always started by some kind of bootloader now.
  70          *  -- Cort
  71          */
  72         nop     /* used by __secondary_hold on prep (mtx) and chrp smp */
  73         nop     /* used by __secondary_hold on prep (mtx) and chrp smp */
  74         nop
  75
  76 /* PMAC
  77  * Enter here with the kernel text, data and bss loaded starting at
  78  * 0, running with virtual == physical mapping.
  79  * r5 points to the prom entry point (the client interface handler
  80  * address).  Address translation is turned on, with the prom
  81  * managing the hash table.  Interrupts are disabled.  The stack
  82  * pointer (r1) points to just below the end of the half-meg region
  83  * from 0x380000 - 0x400000, which is mapped in already.
  84  *
  85  * If we are booted from MacOS via BootX, we enter with the kernel
  86  * image loaded somewhere, and the following values in registers:
  87  *  r3: 'BooX' (0x426f6f58)
  88  *  r4: virtual address of boot_infos_t
  89  *  r5: 0
  90  *
  91  * APUS
  92  *   r3: 'APUS'
  93  *   r4: physical address of memory base
  94  *   Linux/m68k style BootInfo structure at &_end.
  95  *
  96  * PREP
  97  * This is jumped to on prep systems right after the kernel is relocated
  98  * to its proper place in memory by the boot loader.  The expected layout
  99  * of the regs is:
 100  *   r3: ptr to residual data
 101  *   r4: initrd_start or if no initrd then 0
 102  *   r5: initrd_end - unused if r4 is 0
 103  *   r6: Start of command line string
 104  *   r7: End of command line string
 105  *
 106  * This just gets a minimal mmu environment setup so we can call
 107  * start_here() to do the real work.
 108  * -- Cort
 109  */
 110
 111         .globl  __start
 112 __start:
 113         mr      r31,r3                  /* save parameters */
 114         mr      r30,r4
 115         mr      r29,r5
 116         mr      r28,r6
 117         mr      r27,r7
 118         li      r24,0                   /* cpu # */
 119
 120 /*
 121  * early_init() does the early machine identification and does
 122  * the necessary low-level setup and clears the BSS
 123  *  -- Cort <cort@fsmlabs.com>
 124  */
 125         bl      early_init
 126
 127 /* Switch MMU off, clear BATs and flush TLB. At this point, r3 contains
 128  * the physical address we are running at, returned by early_init()
 129  */
 130         bl      mmu_off
 131 __after_mmu_off:
 132         bl      clear_bats
 133         bl      flush_tlbs
 134
 135         bl      initial_bats
 136 #ifdef CONFIG_BOOTX_TEXT
 137         bl      setup_disp_bat
 138 #endif
 139
 140 /*
 141  * Call setup_cpu for CPU 0 and initialize 6xx Idle
 142  */
 143         bl      reloc_offset
 144         li      r24,0                   /* cpu# */
 145         bl      call_setup_cpu          /* Call setup_cpu for this CPU */
 146 #ifdef CONFIG_6xx
 147         bl      reloc_offset
 148         bl      init_idle_6xx
 149 #endif /* CONFIG_6xx */
 150
 151
 152 /*
 153  * We need to run with _start at physical address 0.
 154  * If the MMU is already turned on, we copy stuff to KERNELBASE,
 155  * otherwise we copy it to 0.
 156  */
 157         bl      reloc_offset
 158         mr      r26,r3
 159         addis   r4,r3,KERNELBASE@h      /* current address of _start */
 160         cmpwi   0,r4,0                  /* are we already running at 0? */
 161         bne     relocate_kernel
 162
 163 /*
 164  * we now have the 1st 16M of ram mapped with the bats.
 165  * prep needs the mmu to be turned on here, but pmac already has it on.
 166  * this shouldn't bother the pmac since it just gets turned on again
 167  * as we jump to our code at KERNELBASE. -- Cort
 168  * Actually no, pmac doesn't have it on any more. BootX enters with MMU
 169  * off, and in other cases, we now turn it off before changing BATs above.
 170  */
 171 turn_on_mmu:
 172         mfmsr   r0
 173         ori     r0,r0,MSR_DR|MSR_IR
 174         mtspr   SPRN_SRR1,r0
 175         lis     r0,start_here@h
 176         ori     r0,r0,start_here@l
 177         mtspr   SPRN_SRR0,r0
 178         SYNC
 179         RFI                             /* enables MMU */
 180
 181 /*
 182  * We need __secondary_hold as a place to hold the other cpus on
 183  * an SMP machine, even when we are running a UP kernel.
 184  */
 185         . = 0xc0                        /* for prep bootloader */
 186         li      r3,1                    /* MTX only has 1 cpu */
 187         .globl  __secondary_hold
 188 __secondary_hold:
 189         /* tell the master we're here */
 190         stw     r3,4(0)
 191 #ifdef CONFIG_SMP
 192 100:    lwz     r4,0(0)
 193         /* wait until we're told to start */
 194         cmpw    0,r4,r3
 195         bne     100b
 196         /* our cpu # was at addr 0 - go */
 197         mr      r24,r3                  /* cpu # */
 198         b       __secondary_start
 199 #else
 200         b       .
 201 #endif /* CONFIG_SMP */
 202
 203 /*
 204  * Exception entry code.  This code runs with address translation
 205  * turned off, i.e. using physical addresses.
 206  * We assume sprg3 has the physical address of the current
 207  * task's thread_struct.
 208  */
 209 #define EXCEPTION_PROLOG        \
 210         mtspr   SPRN_SPRG0,r10; \
 211         mtspr   SPRN_SPRG1,r11; \
 212         mfcr    r10;            \
 213         EXCEPTION_PROLOG_1;     \
 214         EXCEPTION_PROLOG_2
 215
 216 #define EXCEPTION_PROLOG_1      \
 217         mfspr   r11,SPRN_SRR1;          /* check whether user or kernel */ \
 218         andi.   r11,r11,MSR_PR; \
 219         tophys(r11,r1);                 /* use tophys(r1) if kernel */ \
 220         beq     1f;             \
 221         mfspr   r11,SPRN_SPRG3; \
 222         lwz     r11,THREAD_INFO-THREAD(r11);    \
 223         addi    r11,r11,THREAD_SIZE;    \
 224         tophys(r11,r11);        \
 225 1:      subi    r11,r11,INT_FRAME_SIZE  /* alloc exc. frame */
 226
 227
 228 #define EXCEPTION_PROLOG_2      \
 229         CLR_TOP32(r11);         \
 230         stw     r10,_CCR(r11);          /* save registers */ \
 231         stw     r12,GPR12(r11); \
 232         stw     r9,GPR9(r11);   \
 233         mfspr   r10,SPRN_SPRG0; \
 234         stw     r10,GPR10(r11); \
 235         mfspr   r12,SPRN_SPRG1; \
 236         stw     r12,GPR11(r11); \
 237         mflr    r10;            \
 238         stw     r10,_LINK(r11); \
 239         mfspr   r12,SPRN_SRR0;  \
 240         mfspr   r9,SPRN_SRR1;   \
 241         stw     r1,GPR1(r11);   \
 242         stw     r1,0(r11);      \
 243         tovirt(r1,r11);                 /* set new kernel sp */ \
 244         li      r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
 245         MTMSRD(r10);                    /* (except for mach check in rtas) */ \
 246         stw     r0,GPR0(r11);   \
 247         SAVE_4GPRS(3, r11);     \
 248         SAVE_2GPRS(7, r11)
 249
 250 /*
 251  * Note: code which follows this uses cr0.eq (set if from kernel),
 252  * r11, r12 (SRR0), and r9 (SRR1).
 253  *
 254  * Note2: once we have set r1 we are in a position to take exceptions
 255  * again, and we could thus set MSR:RI at that point.
 256  */
 257
 258 /*
 259  * Exception vectors.
 260  */
 261 #define EXCEPTION(n, label, hdlr, xfer)         \
 262         . = n;                                  \
 263 label:                                          \
 264         EXCEPTION_PROLOG;                       \
 265         addi    r3,r1,STACK_FRAME_OVERHEAD;     \
 266         xfer(n, hdlr)
 267
 268 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret)     \
 269         li      r10,trap;                                       \
 270         stw     r10,TRAP(r11);                                  \
 271         li      r10,MSR_KERNEL;                                 \
 272         copyee(r10, r9);                                        \
 273         bl      tfer;                                           \
 274 i##n:                                                           \
 275         .long   hdlr;                                           \
 276         .long   ret
 277
 278 #define COPY_EE(d, s)           rlwimi d,s,0,16,16
 279 #define NOCOPY(d, s)
 280
 281 #define EXC_XFER_STD(n, hdlr)           \
 282         EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
 283                           ret_from_except_full)
 284
 285 #define EXC_XFER_LITE(n, hdlr)          \
 286         EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
 287                           ret_from_except)
 288
 289 #define EXC_XFER_EE(n, hdlr)            \
 290         EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
 291                           ret_from_except_full)
 292
 293 #define EXC_XFER_EE_LITE(n, hdlr)       \
 294         EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
 295                           ret_from_except)
 296
 297 /* System reset */
 298 /* core99 pmac starts the seconary here by changing the vector, and
 299    putting it back to what it was (unknown_exception) when done.  */
 300         EXCEPTION(0x100, Reset, unknown_exception, EXC_XFER_STD)
 301
 302 /* Machine check */
 303         . = 0x200
 304         mtspr   SPRN_SPRG0,r10
 305         mtspr   SPRN_SPRG1,r11
 306         mfcr    r10
 307         EXCEPTION_PROLOG_1
 308 7:      EXCEPTION_PROLOG_2
 309         addi    r3,r1,STACK_FRAME_OVERHEAD
 310         EXC_XFER_STD(0x200, machine_check_exception)
 311
 312 /* Data access exception. */
 313         . = 0x300
 314 DataAccess:
 315         EXCEPTION_PROLOG
 316         mfspr   r10,SPRN_DSISR
 317         andis.  r0,r10,0xa470           /* weird error? */
 318         bne     1f                      /* if not, try to put a PTE */
 319         mfspr   r4,SPRN_DAR             /* into the hash table */
 320         rlwinm  r3,r10,32-15,21,21      /* DSISR_STORE -> _PAGE_RW */
 321         bl      hash_page
 322 1:      stw     r10,_DSISR(r11)
 323         mr      r5,r10
 324         mfspr   r4,SPRN_DAR
 325         EXC_XFER_EE_LITE(0x300, handle_page_fault)
 326
 327 /* Instruction access exception. */
 328         . = 0x400
 329 InstructionAccess:
 330         EXCEPTION_PROLOG
 331         andis.  r0,r9,0x4000            /* no pte found? */
 332         beq     1f                      /* if so, try to put a PTE */
 333         li      r3,0                    /* into the hash table */
 334         mr      r4,r12                  /* SRR0 is fault address */
 335         bl      hash_page
 336 1:      mr      r4,r12
 337         mr      r5,r9
 338         EXC_XFER_EE_LITE(0x400, handle_page_fault)
 339
 340 /* External interrupt */
 341         EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
 342
 343 /* Alignment exception */
 344         . = 0x600
 345 Alignment:
 346         EXCEPTION_PROLOG
 347         mfspr   r4,SPRN_DAR
 348         stw     r4,_DAR(r11)
 349         mfspr   r5,SPRN_DSISR
 350         stw     r5,_DSISR(r11)
 351         addi    r3,r1,STACK_FRAME_OVERHEAD
 352         EXC_XFER_EE(0x600, alignment_exception)
 353
 354 /* Program check exception */
 355         EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
 356
 357 /* Floating-point unavailable */
 358         . = 0x800
 359 FPUnavailable:
 360         EXCEPTION_PROLOG
 361         bne     load_up_fpu             /* if from user, just load it up */
 362         addi    r3,r1,STACK_FRAME_OVERHEAD
 363         EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)
 364
 365 /* Decrementer */
 366         EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
 367
 368         EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
 369         EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
 370
 371 /* System call */
 372         . = 0xc00
 373 SystemCall:
 374         EXCEPTION_PROLOG
 375         EXC_XFER_EE_LITE(0xc00, DoSyscall)
 376
 377 /* Single step - not used on 601 */
 378         EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
 379         EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
 380
 381 /*
 382  * The Altivec unavailable trap is at 0x0f20.  Foo.
 383  * We effectively remap it to 0x3000.
 384  * We include an altivec unavailable exception vector even if
 385  * not configured for Altivec, so that you can't panic a
 386  * non-altivec kernel running on a machine with altivec just
 387  * by executing an altivec instruction.
 388  */
 389         . = 0xf00
 390         b       Trap_0f
 391
 392         . = 0xf20
 393         b       AltiVecUnavailable
 394
 395 Trap_0f:
 396         EXCEPTION_PROLOG
 397         addi    r3,r1,STACK_FRAME_OVERHEAD
 398         EXC_XFER_EE(0xf00, unknown_exception)
 399
 400 /*
 401  * Handle TLB miss for instruction on 603/603e.
 402  * Note: we get an alternate set of r0 - r3 to use automatically.
 403  */
 404         . = 0x1000
 405 InstructionTLBMiss:
 406 /*
 407  * r0:  stored ctr
 408  * r1:  linux style pte ( later becomes ppc hardware pte )
 409  * r2:  ptr to linux-style pte
 410  * r3:  scratch
 411  */
 412         mfctr   r0
 413         /* Get PTE (linux-style) and check access */
 414         mfspr   r3,SPRN_IMISS
 415         lis     r1,KERNELBASE@h         /* check if kernel address */
 416         cmplw   0,r3,r1
 417         mfspr   r2,SPRN_SPRG3
 418         li      r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
 419         lwz     r2,PGDIR(r2)
 420         blt+    112f
 421         lis     r2,swapper_pg_dir@ha    /* if kernel address, use */
 422         addi    r2,r2,swapper_pg_dir@l  /* kernel page table */
 423         mfspr   r1,SPRN_SRR1            /* and MSR_PR bit from SRR1 */
 424         rlwinm  r1,r1,32-12,29,29       /* shift MSR_PR to _PAGE_USER posn */
 425 112:    tophys(r2,r2)
 426         rlwimi  r2,r3,12,20,29          /* insert top 10 bits of address */
 427         lwz     r2,0(r2)                /* get pmd entry */
 428         rlwinm. r2,r2,0,0,19            /* extract address of pte page */
 429         beq-    InstructionAddressInvalid       /* return if no mapping */
 430         rlwimi  r2,r3,22,20,29          /* insert next 10 bits of address */
 431         lwz     r3,0(r2)                /* get linux-style pte */
 432         andc.   r1,r1,r3                /* check access & ~permission */
 433         bne-    InstructionAddressInvalid /* return if access not permitted */
 434         ori     r3,r3,_PAGE_ACCESSED    /* set _PAGE_ACCESSED in pte */
 435         /*
 436          * NOTE! We are assuming this is not an SMP system, otherwise
 437          * we would need to update the pte atomically with lwarx/stwcx.
 438          */
 439         stw     r3,0(r2)                /* update PTE (accessed bit) */
 440         /* Convert linux-style PTE to low word of PPC-style PTE */
 441         rlwinm  r1,r3,32-10,31,31       /* _PAGE_RW -> PP lsb */
 442         rlwinm  r2,r3,32-7,31,31        /* _PAGE_DIRTY -> PP lsb */
 443         and     r1,r1,r2                /* writable if _RW and _DIRTY */
 444         rlwimi  r3,r3,32-1,30,30        /* _PAGE_USER -> PP msb */
 445         rlwimi  r3,r3,32-1,31,31        /* _PAGE_USER -> PP lsb */
 446         ori     r1,r1,0xe14             /* clear out reserved bits and M */
 447         andc    r1,r3,r1                /* PP = user? (rw&dirty? 2: 3): 0 */
 448         mtspr   SPRN_RPA,r1
 449         mfspr   r3,SPRN_IMISS
 450         tlbli   r3
 451         mfspr   r3,SPRN_SRR1            /* Need to restore CR0 */
 452         mtcrf   0x80,r3
 453         rfi
 454 InstructionAddressInvalid:
 455         mfspr   r3,SPRN_SRR1
 456         rlwinm  r1,r3,9,6,6     /* Get load/store bit */
 457
 458         addis   r1,r1,0x2000
 459         mtspr   SPRN_DSISR,r1   /* (shouldn't be needed) */
 460         mtctr   r0              /* Restore CTR */
 461         andi.   r2,r3,0xFFFF    /* Clear upper bits of SRR1 */
 462         or      r2,r2,r1
 463         mtspr   SPRN_SRR1,r2
 464         mfspr   r1,SPRN_IMISS   /* Get failing address */
 465         rlwinm. r2,r2,0,31,31   /* Check for little endian access */
 466         rlwimi  r2,r2,1,30,30   /* change 1 -> 3 */
 467         xor     r1,r1,r2
 468         mtspr   SPRN_DAR,r1     /* Set fault address */
 469         mfmsr   r0              /* Restore "normal" registers */
 470         xoris   r0,r0,MSR_TGPR>>16
 471         mtcrf   0x80,r3         /* Restore CR0 */
 472         mtmsr   r0
 473         b       InstructionAccess
 474
 475 /*
 476  * Handle TLB miss for DATA Load operation on 603/603e
 477  */
 478         . = 0x1100
 479 DataLoadTLBMiss:
 480 /*
 481  * r0:  stored ctr
 482  * r1:  linux style pte ( later becomes ppc hardware pte )
 483  * r2:  ptr to linux-style pte
 484  * r3:  scratch
 485  */
 486         mfctr   r0
 487         /* Get PTE (linux-style) and check access */
 488         mfspr   r3,SPRN_DMISS
 489         lis     r1,KERNELBASE@h         /* check if kernel address */
 490         cmplw   0,r3,r1
 491         mfspr   r2,SPRN_SPRG3
 492         li      r1,_PAGE_USER|_PAGE_PRESENT /* low addresses tested as user */
 493         lwz     r2,PGDIR(r2)
 494         blt+    112f
 495         lis     r2,swapper_pg_dir@ha    /* if kernel address, use */
 496         addi    r2,r2,swapper_pg_dir@l  /* kernel page table */
 497         mfspr   r1,SPRN_SRR1            /* and MSR_PR bit from SRR1 */
 498         rlwinm  r1,r1,32-12,29,29       /* shift MSR_PR to _PAGE_USER posn */
 499 112:    tophys(r2,r2)
 500         rlwimi  r2,r3,12,20,29          /* insert top 10 bits of address */
 501         lwz     r2,0(r2)                /* get pmd entry */
 502         rlwinm. r2,r2,0,0,19            /* extract address of pte page */
 503         beq-    DataAddressInvalid      /* return if no mapping */
 504         rlwimi  r2,r3,22,20,29          /* insert next 10 bits of address */
 505         lwz     r3,0(r2)                /* get linux-style pte */
 506         andc.   r1,r1,r3                /* check access & ~permission */
 507         bne-    DataAddressInvalid      /* return if access not permitted */
 508         ori     r3,r3,_PAGE_ACCESSED    /* set _PAGE_ACCESSED in pte */
 509         /*
 510          * NOTE! We are assuming this is not an SMP system, otherwise
 511          * we would need to update the pte atomically with lwarx/stwcx.
 512          */
 513         stw     r3,0(r2)                /* update PTE (accessed bit) */
 514         /* Convert linux-style PTE to low word of PPC-style PTE */
 515         rlwinm  r1,r3,32-10,31,31       /* _PAGE_RW -> PP lsb */
 516         rlwinm  r2,r3,32-7,31,31        /* _PAGE_DIRTY -> PP lsb */
 517         and     r1,r1,r2                /* writable if _RW and _DIRTY */
 518         rlwimi  r3,r3,32-1,30,30        /* _PAGE_USER -> PP msb */
 519         rlwimi  r3,r3,32-1,31,31        /* _PAGE_USER -> PP lsb */
 520         ori     r1,r1,0xe14             /* clear out reserved bits and M */
 521         andc    r1,r3,r1                /* PP = user? (rw&dirty? 2: 3): 0 */
 522         mtspr   SPRN_RPA,r1
 523         mfspr   r3,SPRN_DMISS
 524         tlbld   r3
 525         mfspr   r3,SPRN_SRR1            /* Need to restore CR0 */
 526         mtcrf   0x80,r3
 527         rfi
 528 DataAddressInvalid:
 529         mfspr   r3,SPRN_SRR1
 530         rlwinm  r1,r3,9,6,6     /* Get load/store bit */
 531         addis   r1,r1,0x2000
 532         mtspr   SPRN_DSISR,r1
 533         mtctr   r0              /* Restore CTR */
 534         andi.   r2,r3,0xFFFF    /* Clear upper bits of SRR1 */
 535         mtspr   SPRN_SRR1,r2
 536         mfspr   r1,SPRN_DMISS   /* Get failing address */
 537         rlwinm. r2,r2,0,31,31   /* Check for little endian access */
 538         beq     20f             /* Jump if big endian */
 539         xori    r1,r1,3
 540 20:     mtspr   SPRN_DAR,r1     /* Set fault address */
 541         mfmsr   r0              /* Restore "normal" registers */
 542         xoris   r0,r0,MSR_TGPR>>16
 543         mtcrf   0x80,r3         /* Restore CR0 */
 544         mtmsr   r0
 545         b       DataAccess
 546
 547 /*
 548  * Handle TLB miss for DATA Store on 603/603e
 549  */
 550         . = 0x1200
 551 DataStoreTLBMiss:
 552 /*
 553  * r0:  stored ctr
 554  * r1:  linux style pte ( later becomes ppc hardware pte )
 555  * r2:  ptr to linux-style pte
 556  * r3:  scratch
 557  */
 558         mfctr   r0
 559         /* Get PTE (linux-style) and check access */
 560         mfspr   r3,SPRN_DMISS
 561         lis     r1,KERNELBASE@h         /* check if kernel address */
 562         cmplw   0,r3,r1
 563         mfspr   r2,SPRN_SPRG3
 564         li      r1,_PAGE_RW|_PAGE_USER|_PAGE_PRESENT /* access flags */
 565         lwz     r2,PGDIR(r2)
 566         blt+    112f
 567         lis     r2,swapper_pg_dir@ha    /* if kernel address, use */
 568         addi    r2,r2,swapper_pg_dir@l  /* kernel page table */
 569         mfspr   r1,SPRN_SRR1            /* and MSR_PR bit from SRR1 */
 570         rlwinm  r1,r1,32-12,29,29       /* shift MSR_PR to _PAGE_USER posn */
 571 112:    tophys(r2,r2)
 572         rlwimi  r2,r3,12,20,29          /* insert top 10 bits of address */
 573         lwz     r2,0(r2)                /* get pmd entry */
 574         rlwinm. r2,r2,0,0,19            /* extract address of pte page */
 575         beq-    DataAddressInvalid      /* return if no mapping */
 576         rlwimi  r2,r3,22,20,29          /* insert next 10 bits of address */
 577         lwz     r3,0(r2)                /* get linux-style pte */
 578         andc.   r1,r1,r3                /* check access & ~permission */
 579         bne-    DataAddressInvalid      /* return if access not permitted */
 580         ori     r3,r3,_PAGE_ACCESSED|_PAGE_DIRTY
 581         /*
 582          * NOTE! We are assuming this is not an SMP system, otherwise
 583          * we would need to update the pte atomically with lwarx/stwcx.
 584          */
 585         stw     r3,0(r2)                /* update PTE (accessed/dirty bits) */
 586         /* Convert linux-style PTE to low word of PPC-style PTE */
 587         rlwimi  r3,r3,32-1,30,30        /* _PAGE_USER -> PP msb */
 588         li      r1,0xe15                /* clear out reserved bits and M */
 589         andc    r1,r3,r1                /* PP = user? 2: 0 */
 590         mtspr   SPRN_RPA,r1
 591         mfspr   r3,SPRN_DMISS
 592         tlbld   r3
 593         mfspr   r3,SPRN_SRR1            /* Need to restore CR0 */
 594         mtcrf   0x80,r3
 595         rfi
 596
 597 #ifndef CONFIG_ALTIVEC
 598 #define altivec_assist_exception        unknown_exception
 599 #endif
 600
 601         EXCEPTION(0x1300, Trap_13, instruction_breakpoint_exception, EXC_XFER_EE)
 602         EXCEPTION(0x1400, SMI, SMIException, EXC_XFER_EE)
 603         EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
 604         EXCEPTION(0x1600, Trap_16, altivec_assist_exception, EXC_XFER_EE)
 605         EXCEPTION(0x1700, Trap_17, TAUException, EXC_XFER_STD)
 606         EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
 607         EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
 608         EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
 609         EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
 610         EXCEPTION(0x1c00, Trap_1c, unknown_exception, EXC_XFER_EE)
 611         EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
 612         EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
 613         EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
 614         EXCEPTION(0x2000, RunMode, RunModeException, EXC_XFER_EE)
 615         EXCEPTION(0x2100, Trap_21, unknown_exception, EXC_XFER_EE)
 616         EXCEPTION(0x2200, Trap_22, unknown_exception, EXC_XFER_EE)
 617         EXCEPTION(0x2300, Trap_23, unknown_exception, EXC_XFER_EE)
 618         EXCEPTION(0x2400, Trap_24, unknown_exception, EXC_XFER_EE)
 619         EXCEPTION(0x2500, Trap_25, unknown_exception, EXC_XFER_EE)
 620         EXCEPTION(0x2600, Trap_26, unknown_exception, EXC_XFER_EE)
 621         EXCEPTION(0x2700, Trap_27, unknown_exception, EXC_XFER_EE)
 622         EXCEPTION(0x2800, Trap_28, unknown_exception, EXC_XFER_EE)
 623         EXCEPTION(0x2900, Trap_29, unknown_exception, EXC_XFER_EE)
 624         EXCEPTION(0x2a00, Trap_2a, unknown_exception, EXC_XFER_EE)
 625         EXCEPTION(0x2b00, Trap_2b, unknown_exception, EXC_XFER_EE)
 626         EXCEPTION(0x2c00, Trap_2c, unknown_exception, EXC_XFER_EE)
 627         EXCEPTION(0x2d00, Trap_2d, unknown_exception, EXC_XFER_EE)
 628         EXCEPTION(0x2e00, Trap_2e, unknown_exception, EXC_XFER_EE)
 629         EXCEPTION(0x2f00, MOLTrampoline, unknown_exception, EXC_XFER_EE_LITE)
 630
 631         .globl mol_trampoline
 632         .set mol_trampoline, i0x2f00
 633
 634         . = 0x3000
 635
 636 AltiVecUnavailable:
 637         EXCEPTION_PROLOG
 638 #ifdef CONFIG_ALTIVEC
 639         bne     load_up_altivec         /* if from user, just load it up */
 640 #endif /* CONFIG_ALTIVEC */
 641         addi    r3,r1,STACK_FRAME_OVERHEAD
 642         EXC_XFER_EE_LITE(0xf20, altivec_unavailable_exception)
 643
 644 #ifdef CONFIG_ALTIVEC
 645 /* Note that the AltiVec support is closely modeled after the FP
 646  * support.  Changes to one are likely to be applicable to the
 647  * other!  */
 648 load_up_altivec:
 649 /*
 650  * Disable AltiVec for the task which had AltiVec previously,
 651  * and save its AltiVec registers in its thread_struct.
 652  * Enables AltiVec for use in the kernel on return.
 653  * On SMP we know the AltiVec units are free, since we give it up every
 654  * switch.  -- Kumar
 655  */
 656         mfmsr   r5
 657         oris    r5,r5,MSR_VEC@h
 658         MTMSRD(r5)                      /* enable use of AltiVec now */
 659         isync
 660 /*
 661  * For SMP, we don't do lazy AltiVec switching because it just gets too
 662  * horrendously complex, especially when a task switches from one CPU
 663  * to another.  Instead we call giveup_altivec in switch_to.
 664  */
 665 #ifndef CONFIG_SMP
 666         tophys(r6,0)
 667         addis   r3,r6,last_task_used_altivec@ha
 668         lwz     r4,last_task_used_altivec@l(r3)
 669         cmpwi   0,r4,0
 670         beq     1f
 671         add     r4,r4,r6
 672         addi    r4,r4,THREAD    /* want THREAD of last_task_used_altivec */
 673         SAVE_32VRS(0,r10,r4)
 674         mfvscr  vr0
 675         li      r10,THREAD_VSCR
 676         stvx    vr0,r10,r4
 677         lwz     r5,PT_REGS(r4)
 678         add     r5,r5,r6
 679         lwz     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 680         lis     r10,MSR_VEC@h
 681         andc    r4,r4,r10       /* disable altivec for previous task */
 682         stw     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 683 1:
 684 #endif /* CONFIG_SMP */
 685         /* enable use of AltiVec after return */
 686         oris    r9,r9,MSR_VEC@h
 687         mfspr   r5,SPRN_SPRG3           /* current task's THREAD (phys) */
 688         li      r4,1
 689         li      r10,THREAD_VSCR
 690         stw     r4,THREAD_USED_VR(r5)
 691         lvx     vr0,r10,r5
 692         mtvscr  vr0
 693         REST_32VRS(0,r10,r5)
 694 #ifndef CONFIG_SMP
 695         subi    r4,r5,THREAD
 696         sub     r4,r4,r6
 697         stw     r4,last_task_used_altivec@l(r3)
 698 #endif /* CONFIG_SMP */
 699         /* restore registers and return */
 700         /* we haven't used ctr or xer or lr */
 701         b       fast_exception_return
 702
 703 /*
 704  * AltiVec unavailable trap from kernel - print a message, but let
 705  * the task use AltiVec in the kernel until it returns to user mode.
 706  */
 707 KernelAltiVec:
 708         lwz     r3,_MSR(r1)
 709         oris    r3,r3,MSR_VEC@h
 710         stw     r3,_MSR(r1)     /* enable use of AltiVec after return */
 711         lis     r3,87f@h
 712         ori     r3,r3,87f@l
 713         mr      r4,r2           /* current */
 714         lwz     r5,_NIP(r1)
 715         bl      printk
 716         b       ret_from_except
 717 87:     .string "AltiVec used in kernel  (task=%p, pc=%x)  \n"
 718         .align  4,0
 719
 720 /*
 721  * giveup_altivec(tsk)
 722  * Disable AltiVec for the task given as the argument,
 723  * and save the AltiVec registers in its thread_struct.
 724  * Enables AltiVec for use in the kernel on return.
 725  */
 726
 727         .globl  giveup_altivec
 728 giveup_altivec:
 729         mfmsr   r5
 730         oris    r5,r5,MSR_VEC@h
 731         SYNC
 732         MTMSRD(r5)                      /* enable use of AltiVec now */
 733         isync
 734         cmpwi   0,r3,0
 735         beqlr-                          /* if no previous owner, done */
 736         addi    r3,r3,THREAD            /* want THREAD of task */
 737         lwz     r5,PT_REGS(r3)
 738         cmpwi   0,r5,0
 739         SAVE_32VRS(0, r4, r3)
 740         mfvscr  vr0
 741         li      r4,THREAD_VSCR
 742         stvx    vr0,r4,r3
 743         beq     1f
 744         lwz     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 745         lis     r3,MSR_VEC@h
 746         andc    r4,r4,r3                /* disable AltiVec for previous task */
 747         stw     r4,_MSR-STACK_FRAME_OVERHEAD(r5)
 748 1:
 749 #ifndef CONFIG_SMP
 750         li      r5,0
 751         lis     r4,last_task_used_altivec@ha
 752         stw     r5,last_task_used_altivec@l(r4)
 753 #endif /* CONFIG_SMP */
 754         blr
 755 #endif /* CONFIG_ALTIVEC */
 756
 757 /*
 758  * This code is jumped to from the startup code to copy
 759  * the kernel image to physical address 0.
 760  */
 761 relocate_kernel:
 762         addis   r9,r26,klimit@ha        /* fetch klimit */
 763         lwz     r25,klimit@l(r9)
 764         addis   r25,r25,-KERNELBASE@h
 765         li      r3,0                    /* Destination base address */
 766         li      r6,0                    /* Destination offset */
 767         li      r5,0x4000               /* # bytes of memory to copy */
 768         bl      copy_and_flush          /* copy the first 0x4000 bytes */
 769         addi    r0,r3,4f@l              /* jump to the address of 4f */
 770         mtctr   r0                      /* in copy and do the rest. */
 771         bctr                            /* jump to the copy */
 772 4:      mr      r5,r25
 773         bl      copy_and_flush          /* copy the rest */
 774         b       turn_on_mmu
 775
 776 /*
 777  * Copy routine used to copy the kernel to start at physical address 0
 778  * and flush and invalidate the caches as needed.
 779  * r3 = dest addr, r4 = source addr, r5 = copy limit, r6 = start offset
 780  * on exit, r3, r4, r5 are unchanged, r6 is updated to be >= r5.
 781  */
 782 copy_and_flush:
 783         addi    r5,r5,-4
 784         addi    r6,r6,-4
 785 4:      li      r0,L1_CACHE_BYTES/4
 786         mtctr   r0
 787 3:      addi    r6,r6,4                 /* copy a cache line */
 788         lwzx    r0,r6,r4
 789         stwx    r0,r6,r3
 790         bdnz    3b
 791         dcbst   r6,r3                   /* write it to memory */
 792         sync
 793         icbi    r6,r3                   /* flush the icache line */
 794         cmplw   0,r6,r5
 795         blt     4b
 796         sync                            /* additional sync needed on g4 */
 797         isync
 798         addi    r5,r5,4
 799         addi    r6,r6,4
 800         blr
 801
 802 #ifdef CONFIG_SMP
 803         .globl  __secondary_start_pmac_0
 804 __secondary_start_pmac_0:
 805         /* NB the entries for cpus 0, 1, 2 must each occupy 8 bytes. */
 806         li      r24,0
 807         b       1f
 808         li      r24,1
 809         b       1f
 810         li      r24,2
 811         b       1f
 812         li      r24,3
 813 1:
 814         /* on powersurge, we come in here with IR=0 and DR=1, and DBAT 0
 815            set to map the 0xf0000000 - 0xffffffff region */
 816         mfmsr   r0
 817         rlwinm  r0,r0,0,28,26           /* clear DR (0x10) */
 818         SYNC
 819         mtmsr   r0
 820         isync
 821
 822         .globl  __secondary_start
 823 __secondary_start:
 824         /* Copy some CPU settings from CPU 0 */
 825         bl      __restore_cpu_setup
 826
 827         lis     r3,-KERNELBASE@h
 828         mr      r4,r24
 829         bl      call_setup_cpu          /* Call setup_cpu for this CPU */
 830 #ifdef CONFIG_6xx
 831         lis     r3,-KERNELBASE@h
 832         bl      init_idle_6xx
 833 #endif /* CONFIG_6xx */
 834
 835         /* get current_thread_info and current */
 836         lis     r1,secondary_ti@ha
 837         tophys(r1,r1)
 838         lwz     r1,secondary_ti@l(r1)
 839         tophys(r2,r1)
 840         lwz     r2,TI_TASK(r2)
 841
 842         /* stack */
 843         addi    r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
 844         li      r0,0
 845         tophys(r3,r1)
 846         stw     r0,0(r3)
 847
 848         /* load up the MMU */
 849         bl      load_up_mmu
 850
 851         /* ptr to phys current thread */
 852         tophys(r4,r2)
 853         addi    r4,r4,THREAD    /* phys address of our thread_struct */
 854         CLR_TOP32(r4)
 855         mtspr   SPRN_SPRG3,r4
 856         li      r3,0
 857         mtspr   SPRN_SPRG2,r3   /* 0 => not in RTAS */
 858
 859         /* enable MMU and jump to start_secondary */
 860         li      r4,MSR_KERNEL
 861         FIX_SRR1(r4,r5)
 862         lis     r3,start_secondary@h
 863         ori     r3,r3,start_secondary@l
 864         mtspr   SPRN_SRR0,r3
 865         mtspr   SPRN_SRR1,r4
 866         SYNC
 867         RFI
 868 #endif /* CONFIG_SMP */
 869
 870 /*
 871  * Those generic dummy functions are kept for CPUs not
 872  * included in CONFIG_6xx
 873  */
 874 #if !defined(CONFIG_6xx)
 875 _GLOBAL(__save_cpu_setup)
 876         blr
 877 _GLOBAL(__restore_cpu_setup)
 878         blr
 879 #endif /* !defined(CONFIG_6xx) */
 880
 881
 882 /*
 883  * Load stuff into the MMU.  Intended to be called with
 884  * IR=0 and DR=0.
 885  */
 886 load_up_mmu:
 887         sync                    /* Force all PTE updates to finish */
 888         isync
 889         tlbia                   /* Clear all TLB entries */
 890         sync                    /* wait for tlbia/tlbie to finish */
 891         TLBSYNC                 /* ... on all CPUs */
 892         /* Load the SDR1 register (hash table base & size) */
 893         lis     r6,_SDR1@ha
 894         tophys(r6,r6)
 895         lwz     r6,_SDR1@l(r6)
 896         mtspr   SPRN_SDR1,r6
 897         li      r0,16           /* load up segment register values */
 898         mtctr   r0              /* for context 0 */
 899         lis     r3,0x2000       /* Ku = 1, VSID = 0 */
 900         li      r4,0
 901 3:      mtsrin  r3,r4
 902         addi    r3,r3,0x111     /* increment VSID */
 903         addis   r4,r4,0x1000    /* address of next segment */
 904         bdnz    3b
 905
 906 /* Load the BAT registers with the values set up by MMU_init.
 907    MMU_init takes care of whether we're on a 601 or not. */
 908         mfpvr   r3
 909         srwi    r3,r3,16
 910         cmpwi   r3,1
 911         lis     r3,BATS@ha
 912         addi    r3,r3,BATS@l
 913         tophys(r3,r3)
 914         LOAD_BAT(0,r3,r4,r5)
 915         LOAD_BAT(1,r3,r4,r5)
 916         LOAD_BAT(2,r3,r4,r5)
 917         LOAD_BAT(3,r3,r4,r5)
 918
 919         blr
 920
 921 /*
 922  * This is where the main kernel code starts.
 923  */
 924 start_here:
 925         /* ptr to current */
 926         lis     r2,init_task@h
 927         ori     r2,r2,init_task@l
 928         /* Set up for using our exception vectors */
 929         /* ptr to phys current thread */
 930         tophys(r4,r2)
 931         addi    r4,r4,THREAD    /* init task's THREAD */
 932         CLR_TOP32(r4)
 933         mtspr   SPRN_SPRG3,r4
 934         li      r3,0
 935         mtspr   SPRN_SPRG2,r3   /* 0 => not in RTAS */
 936
 937         /* stack */
 938         lis     r1,init_thread_union@ha
 939         addi    r1,r1,init_thread_union@l
 940         li      r0,0
 941         stwu    r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
 942 /*
 943  * Do early bootinfo parsing, platform-specific initialization,
 944  * and set up the MMU.
 945  */
 946         mr      r3,r31
 947         mr      r4,r30
 948         mr      r5,r29
 949         mr      r6,r28
 950         mr      r7,r27
 951         bl      machine_init
 952         bl      MMU_init
 953
 954 /*
 955  * Go back to running unmapped so we can load up new values
 956  * for SDR1 (hash table pointer) and the segment registers
 957  * and change to using our exception vectors.
 958  */
 959         lis     r4,2f@h
 960         ori     r4,r4,2f@l
 961         tophys(r4,r4)
 962         li      r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
 963         FIX_SRR1(r3,r5)
 964         mtspr   SPRN_SRR0,r4
 965         mtspr   SPRN_SRR1,r3
 966         SYNC
 967         RFI
 968 /* Load up the kernel context */
 969 2:      bl      load_up_mmu
 970
 971 #ifdef CONFIG_BDI_SWITCH
 972         /* Add helper information for the Abatron bdiGDB debugger.
 973          * We do this here because we know the mmu is disabled, and
 974          * will be enabled for real in just a few instructions.
 975          */
 976         lis     r5, abatron_pteptrs@h
 977         ori     r5, r5, abatron_pteptrs@l
 978         stw     r5, 0xf0(r0)    /* This much match your Abatron config */
 979         lis     r6, swapper_pg_dir@h
 980         ori     r6, r6, swapper_pg_dir@l
 981         tophys(r5, r5)
 982         stw     r6, 0(r5)
 983 #endif /* CONFIG_BDI_SWITCH */
 984
 985 /* Now turn on the MMU for real! */
 986         li      r4,MSR_KERNEL
 987         FIX_SRR1(r4,r5)
 988         lis     r3,start_kernel@h
 989         ori     r3,r3,start_kernel@l
 990         mtspr   SPRN_SRR0,r3
 991         mtspr   SPRN_SRR1,r4
 992         SYNC
 993         RFI
 994
 995 /*
 996  * Set up the segment registers for a new context.
 997  */
 998 _GLOBAL(set_context)
 999         mulli   r3,r3,897       /* multiply context by skew factor */
1000         rlwinm  r3,r3,4,8,27    /* VSID = (context & 0xfffff) << 4 */
1001         addis   r3,r3,0x6000    /* Set Ks, Ku bits */
1002         li      r0,NUM_USER_SEGMENTS
1003         mtctr   r0
1004
1005 #ifdef CONFIG_BDI_SWITCH
1006         /* Context switch the PTE pointer for the Abatron BDI2000.
1007          * The PGDIR is passed as second argument.
1008          */
1009         lis     r5, KERNELBASE@h
1010         lwz     r5, 0xf0(r5)
1011         stw     r4, 0x4(r5)
1012 #endif
1013         li      r4,0
1014         isync
1015 3:
1016         mtsrin  r3,r4
1017         addi    r3,r3,0x111     /* next VSID */
1018         rlwinm  r3,r3,0,8,3     /* clear out any overflow from VSID field */
1019         addis   r4,r4,0x1000    /* address of next segment */
1020         bdnz    3b
1021         sync
1022         isync
1023         blr
1024
1025 /*
1026  * An undocumented "feature" of 604e requires that the v bit
1027  * be cleared before changing BAT values.
1028  *
1029  * Also, newer IBM firmware does not clear bat3 and 4 so
1030  * this makes sure it's done.
1031  *  -- Cort
1032  */
1033 clear_bats:
1034         li      r10,0
1035         mfspr   r9,SPRN_PVR
1036         rlwinm  r9,r9,16,16,31          /* r9 = 1 for 601, 4 for 604 */
1037         cmpwi   r9, 1
1038         beq     1f
1039
1040         mtspr   SPRN_DBAT0U,r10
1041         mtspr   SPRN_DBAT0L,r10
1042         mtspr   SPRN_DBAT1U,r10
1043         mtspr   SPRN_DBAT1L,r10
1044         mtspr   SPRN_DBAT2U,r10
1045         mtspr   SPRN_DBAT2L,r10
1046         mtspr   SPRN_DBAT3U,r10
1047         mtspr   SPRN_DBAT3L,r10
1048 1:
1049         mtspr   SPRN_IBAT0U,r10
1050         mtspr   SPRN_IBAT0L,r10
1051         mtspr   SPRN_IBAT1U,r10
1052         mtspr   SPRN_IBAT1L,r10
1053         mtspr   SPRN_IBAT2U,r10
1054         mtspr   SPRN_IBAT2L,r10
1055         mtspr   SPRN_IBAT3U,r10
1056         mtspr   SPRN_IBAT3L,r10
1057 BEGIN_FTR_SECTION
1058         /* Here's a tweak: at this point, CPU setup have
1059          * not been called yet, so HIGH_BAT_EN may not be
1060          * set in HID0 for the 745x processors. However, it
1061          * seems that doesn't affect our ability to actually
1062          * write to these SPRs.
1063          */
1064         mtspr   SPRN_DBAT4U,r10
1065         mtspr   SPRN_DBAT4L,r10
1066         mtspr   SPRN_DBAT5U,r10
1067         mtspr   SPRN_DBAT5L,r10
1068         mtspr   SPRN_DBAT6U,r10
1069         mtspr   SPRN_DBAT6L,r10
1070         mtspr   SPRN_DBAT7U,r10
1071         mtspr   SPRN_DBAT7L,r10
1072         mtspr   SPRN_IBAT4U,r10
1073         mtspr   SPRN_IBAT4L,r10
1074         mtspr   SPRN_IBAT5U,r10
1075         mtspr   SPRN_IBAT5L,r10
1076         mtspr   SPRN_IBAT6U,r10
1077         mtspr   SPRN_IBAT6L,r10
1078         mtspr   SPRN_IBAT7U,r10
1079         mtspr   SPRN_IBAT7L,r10
1080 END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS)
1081         blr
1082
1083 flush_tlbs:
1084         lis     r10, 0x40
1085 1:      addic.  r10, r10, -0x1000
1086         tlbie   r10
1087         blt     1b
1088         sync
1089         blr
1090
1091 mmu_off:
1092         addi    r4, r3, __after_mmu_off - _start
1093         mfmsr   r3
1094         andi.   r0,r3,MSR_DR|MSR_IR             /* MMU enabled? */
1095         beqlr
1096         andc    r3,r3,r0
1097         mtspr   SPRN_SRR0,r4
1098         mtspr   SPRN_SRR1,r3
1099         sync
1100         RFI
1101
1102 /*
1103  * Use the first pair of BAT registers to map the 1st 16MB
1104  * of RAM to KERNELBASE.  From this point on we can't safely
1105  * call OF any more.
1106  */
1107 initial_bats:
1108         lis     r11,KERNELBASE@h
1109         mfspr   r9,SPRN_PVR
1110         rlwinm  r9,r9,16,16,31          /* r9 = 1 for 601, 4 for 604 */
1111         cmpwi   0,r9,1
1112         bne     4f
1113         ori     r11,r11,4               /* set up BAT registers for 601 */
1114         li      r8,0x7f                 /* valid, block length = 8MB */
1115         oris    r9,r11,0x800000@h       /* set up BAT reg for 2nd 8M */
1116         oris    r10,r8,0x800000@h       /* set up BAT reg for 2nd 8M */
1117         mtspr   SPRN_IBAT0U,r11         /* N.B. 601 has valid bit in */
1118         mtspr   SPRN_IBAT0L,r8          /* lower BAT register */
1119         mtspr   SPRN_IBAT1U,r9
1120         mtspr   SPRN_IBAT1L,r10
1121         isync
1122         blr
1123
1124 4:      tophys(r8,r11)
1125 #ifdef CONFIG_SMP
1126         ori     r8,r8,0x12              /* R/W access, M=1 */
1127 #else
1128         ori     r8,r8,2                 /* R/W access */
1129 #endif /* CONFIG_SMP */
1130         ori     r11,r11,BL_256M<<2|0x2  /* set up BAT registers for 604 */
1131
1132         mtspr   SPRN_DBAT0L,r8          /* N.B. 6xx (not 601) have valid */
1133         mtspr   SPRN_DBAT0U,r11         /* bit in upper BAT register */
1134         mtspr   SPRN_IBAT0L,r8
1135         mtspr   SPRN_IBAT0U,r11
1136         isync
1137         blr
1138
1139 #ifdef CONFIG_BOOTX_TEXT
1140 setup_disp_bat:
1141         /*
1142          * setup the display bat prepared for us in prom.c
1143          */
1144         mflr    r8
1145         bl      reloc_offset
1146         mtlr    r8
1147         addis   r8,r3,disp_BAT@ha
1148         addi    r8,r8,disp_BAT@l
1149         lwz     r11,0(r8)
1150         lwz     r8,4(r8)
1151         mfspr   r9,SPRN_PVR
1152         rlwinm  r9,r9,16,16,31          /* r9 = 1 for 601, 4 for 604 */
1153         cmpwi   0,r9,1
1154         beq     1f
1155         mtspr   SPRN_DBAT3L,r8
1156         mtspr   SPRN_DBAT3U,r11
1157         blr
1158 1:      mtspr   SPRN_IBAT3L,r8
1159         mtspr   SPRN_IBAT3U,r11
1160         blr
1161
1162 #endif /* defined(CONFIG_BOOTX_TEXT) */
1163
1164 #ifdef CONFIG_8260
1165 /* Jump into the system reset for the rom.
1166  * We first disable the MMU, and then jump to the ROM reset address.
1167  *
1168  * r3 is the board info structure, r4 is the location for starting.
1169  * I use this for building a small kernel that can load other kernels,
1170  * rather than trying to write or rely on a rom monitor that can tftp load.
1171  */
1172        .globl  m8260_gorom
1173 m8260_gorom:
1174         mfmsr   r0
1175         rlwinm  r0,r0,0,17,15   /* clear MSR_EE in r0 */
1176         sync
1177         mtmsr   r0
1178         sync
1179         mfspr   r11, SPRN_HID0
1180         lis     r10, 0
1181         ori     r10,r10,HID0_ICE|HID0_DCE
1182         andc    r11, r11, r10
1183         mtspr   SPRN_HID0, r11
1184         isync
1185         li      r5, MSR_ME|MSR_RI
1186         lis     r6,2f@h
1187         addis   r6,r6,-KERNELBASE@h
1188         ori     r6,r6,2f@l
1189         mtspr   SPRN_SRR0,r6
1190         mtspr   SPRN_SRR1,r5
1191         isync
1192         sync
1193         rfi
1194 2:
1195         mtlr    r4
1196         blr
1197 #endif
1198
1199
1200 /*
1201  * We put a few things here that have to be page-aligned.
1202  * This stuff goes at the beginning of the data segment,
1203  * which is page-aligned.
1204  */
1205         .data
1206         .globl  sdata
1207 sdata:
1208         .globl  empty_zero_page
1209 empty_zero_page:
1210         .space  4096
1211
1212         .globl  swapper_pg_dir
1213 swapper_pg_dir:
1214         .space  4096
1215
1216 /*
1217  * This space gets a copy of optional info passed to us by the bootstrap
1218  * Used to pass parameters into the kernel like root=/dev/sda1, etc.
1219  */
1220         .globl  cmd_line
1221 cmd_line:
1222         .space  512
1223
1224         .globl intercept_table
1225 intercept_table:
1226         .long 0, 0, i0x200, i0x300, i0x400, 0, i0x600, i0x700
1227         .long i0x800, 0, 0, 0, 0, i0xd00, 0, 0
1228         .long 0, 0, 0, i0x1300, 0, 0, 0, 0
1229         .long 0, 0, 0, 0, 0, 0, 0, 0
1230         .long 0, 0, 0, 0, 0, 0, 0, 0
1231         .long 0, 0, 0, 0, 0, 0, 0, 0
1232
1233 /* Room for two PTE pointers, usually the kernel and current user pointers
1234  * to their respective root page table.
1235  */
1236 abatron_pteptrs:
1237         .space  8