arch/ppc/kernel/head_4xx.S

   1 /*
   2  *    Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
   3  *      Initial PowerPC version.
   4  *    Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
   5  *      Rewritten for PReP
   6  *    Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
   7  *      Low-level exception handers, MMU support, and rewrite.
   8  *    Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
   9  *      PowerPC 8xx modifications.
  10  *    Copyright (c) 1998-1999 TiVo, Inc.
  11  *      PowerPC 403GCX modifications.
  12  *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
  13  *      PowerPC 403GCX/405GP modifications.
  14  *    Copyright 2000 MontaVista Software Inc.
  15  *      PPC405 modifications
  16  *      PowerPC 403GCX/405GP modifications.
  17  *      Author: MontaVista Software, Inc.
  18  *              frank_rowand@mvista.com or source@mvista.com
  19  *              debbie_chu@mvista.com
  20  *
  21  *
  22  *    Module name: head_4xx.S
  23  *
  24  *    Description:
  25  *      Kernel execution entry point code.
  26  *
  27  *    This program is free software; you can redistribute it and/or
  28  *    modify it under the terms of the GNU General Public License
  29  *    as published by the Free Software Foundation; either version
  30  *    2 of the License, or (at your option) any later version.
  31  *
  32  */
  33
  34 #include <linux/config.h>
  35 #include <asm/processor.h>
  36 #include <asm/page.h>
  37 #include <asm/mmu.h>
  38 #include <asm/pgtable.h>
  39 #include <asm/ibm4xx.h>
  40 #include <asm/cputable.h>
  41 #include <asm/thread_info.h>
  42 #include <asm/ppc_asm.h>
  43 #include <asm/offsets.h>
  44
  45 /* As with the other PowerPC ports, it is expected that when code
  46  * execution begins here, the following registers contain valid, yet
  47  * optional, information:
  48  *
  49  *   r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
  50  *   r4 - Starting address of the init RAM disk
  51  *   r5 - Ending address of the init RAM disk
  52  *   r6 - Start of kernel command line string (e.g. "mem=96m")
  53  *   r7 - End of kernel command line string
  54  *
  55  * This is all going to change RSN when we add bi_recs.......  -- Dan
  56  */
  57         .text
  58 _GLOBAL(_stext)
  59 _GLOBAL(_start)
  60
  61         /* Save parameters we are passed.
  62         */
  63         mr      r31,r3
  64         mr      r30,r4
  65         mr      r29,r5
  66         mr      r28,r6
  67         mr      r27,r7
  68
  69         /* We have to turn on the MMU right away so we get cache modes
  70          * set correctly.
  71          */
  72         bl      initial_mmu
  73
  74 /* We now have the lower 16 Meg mapped into TLB entries, and the caches
  75  * ready to work.
  76  */
  77 turn_on_mmu:
  78         lis     r0,MSR_KERNEL@h
  79         ori     r0,r0,MSR_KERNEL@l
  80         mtspr   SPRN_SRR1,r0
  81         lis     r0,start_here@h
  82         ori     r0,r0,start_here@l
  83         mtspr   SPRN_SRR0,r0
  84         SYNC
  85         rfi                             /* enables MMU */
  86         b       .                       /* prevent prefetch past rfi */
  87
  88 /*
  89  * This area is used for temporarily saving registers during the
  90  * critical exception prolog.
  91  */
  92         . = 0xc0
  93 crit_save:
  94 _GLOBAL(crit_r10)
  95         .space  4
  96 _GLOBAL(crit_r11)
  97         .space  4
  98
  99 /*
 100  * Exception vector entry code. This code runs with address translation
 101  * turned off (i.e. using physical addresses). We assume SPRG3 has the
 102  * physical address of the current task thread_struct.
 103  * Note that we have to have decremented r1 before we write to any fields
 104  * of the exception frame, since a critical interrupt could occur at any
 105  * time, and it will write to the area immediately below the current r1.
 106  */
 107 #define NORMAL_EXCEPTION_PROLOG                                              \
 108         mtspr   SPRN_SPRG0,r10;         /* save two registers to work with */\
 109         mtspr   SPRN_SPRG1,r11;                                              \
 110         mtspr   SPRN_SPRG2,r1;                                               \
 111         mfcr    r10;                    /* save CR in r10 for now          */\
 112         mfspr   r11,SPRN_SRR1;          /* check whether user or kernel    */\
 113         andi.   r11,r11,MSR_PR;                                              \
 114         beq     1f;                                                          \
 115         mfspr   r1,SPRN_SPRG3;          /* if from user, start at top of   */\
 116         lwz     r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack   */\
 117         addi    r1,r1,THREAD_SIZE;                                           \
 118 1:      subi    r1,r1,INT_FRAME_SIZE;   /* Allocate an exception frame     */\
 119         tophys(r11,r1);                                                      \
 120         stw     r10,_CCR(r11);          /* save various registers          */\
 121         stw     r12,GPR12(r11);                                              \
 122         stw     r9,GPR9(r11);                                                \
 123         mfspr   r10,SPRN_SPRG0;                                              \
 124         stw     r10,GPR10(r11);                                              \
 125         mfspr   r12,SPRN_SPRG1;                                              \
 126         stw     r12,GPR11(r11);                                              \
 127         mflr    r10;                                                         \
 128         stw     r10,_LINK(r11);                                              \
 129         mfspr   r10,SPRN_SPRG2;                                              \
 130         mfspr   r12,SPRN_SRR0;                                               \
 131         stw     r10,GPR1(r11);                                               \
 132         mfspr   r9,SPRN_SRR1;                                                \
 133         stw     r10,0(r11);                                                  \
 134         rlwinm  r9,r9,0,14,12;          /* clear MSR_WE (necessary?)       */\
 135         stw     r0,GPR0(r11);                                                \
 136         SAVE_4GPRS(3, r11);                                                  \
 137         SAVE_2GPRS(7, r11)
 138
 139 /*
 140  * Exception prolog for critical exceptions.  This is a little different
 141  * from the normal exception prolog above since a critical exception
 142  * can potentially occur at any point during normal exception processing.
 143  * Thus we cannot use the same SPRG registers as the normal prolog above.
 144  * Instead we use a couple of words of memory at low physical addresses.
 145  * This is OK since we don't support SMP on these processors.
 146  */
 147 #define CRITICAL_EXCEPTION_PROLOG                                            \
 148         stw     r10,crit_r10@l(0);      /* save two registers to work with */\
 149         stw     r11,crit_r11@l(0);                                           \
 150         mfcr    r10;                    /* save CR in r10 for now          */\
 151         mfspr   r11,SPRN_SRR3;          /* check whether user or kernel    */\
 152         andi.   r11,r11,MSR_PR;                                              \
 153         lis     r11,critical_stack_top@h;                                    \
 154         ori     r11,r11,critical_stack_top@l;                                \
 155         beq     1f;                                                          \
 156         /* COMING FROM USER MODE */                                          \
 157         mfspr   r11,SPRN_SPRG3;         /* if from user, start at top of   */\
 158         lwz     r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
 159         addi    r11,r11,THREAD_SIZE;                                         \
 160 1:      subi    r11,r11,INT_FRAME_SIZE; /* Allocate an exception frame     */\
 161         tophys(r11,r11);                                                     \
 162         stw     r10,_CCR(r11);          /* save various registers          */\
 163         stw     r12,GPR12(r11);                                              \
 164         stw     r9,GPR9(r11);                                                \
 165         mflr    r10;                                                         \
 166         stw     r10,_LINK(r11);                                              \
 167         mfspr   r12,SPRN_DEAR;          /* save DEAR and ESR in the frame  */\
 168         stw     r12,_DEAR(r11);         /* since they may have had stuff   */\
 169         mfspr   r9,SPRN_ESR;            /* in them at the point where the  */\
 170         stw     r9,_ESR(r11);           /* exception was taken             */\
 171         mfspr   r12,SPRN_SRR2;                                               \
 172         stw     r1,GPR1(r11);                                                \
 173         mfspr   r9,SPRN_SRR3;                                                \
 174         stw     r1,0(r11);                                                   \
 175         tovirt(r1,r11);                                                      \
 176         rlwinm  r9,r9,0,14,12;          /* clear MSR_WE (necessary?)       */\
 177         stw     r0,GPR0(r11);                                                \
 178         SAVE_4GPRS(3, r11);                                                  \
 179         SAVE_2GPRS(7, r11)
 180
 181         /*
 182          * State at this point:
 183          * r9 saved in stack frame, now saved SRR3 & ~MSR_WE
 184          * r10 saved in crit_r10 and in stack frame, trashed
 185          * r11 saved in crit_r11 and in stack frame,
 186          *      now phys stack/exception frame pointer
 187          * r12 saved in stack frame, now saved SRR2
 188          * CR saved in stack frame, CR0.EQ = !SRR3.PR
 189          * LR, DEAR, ESR in stack frame
 190          * r1 saved in stack frame, now virt stack/excframe pointer
 191          * r0, r3-r8 saved in stack frame
 192          */
 193
 194 /*
 195  * Exception vectors.
 196  */
 197 #define START_EXCEPTION(n, label)                                            \
 198         . = n;                                                               \
 199 label:
 200
 201 #define EXCEPTION(n, label, hdlr, xfer)                         \
 202         START_EXCEPTION(n, label);                              \
 203         NORMAL_EXCEPTION_PROLOG;                                \
 204         addi    r3,r1,STACK_FRAME_OVERHEAD;                     \
 205         xfer(n, hdlr)
 206
 207 #define CRITICAL_EXCEPTION(n, label, hdlr)                      \
 208         START_EXCEPTION(n, label);                              \
 209         CRITICAL_EXCEPTION_PROLOG;                              \
 210         addi    r3,r1,STACK_FRAME_OVERHEAD;                     \
 211         EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
 212                           NOCOPY, crit_transfer_to_handler,     \
 213                           ret_from_crit_exc)
 214
 215 #define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret)   \
 216         li      r10,trap;                                       \
 217         stw     r10,TRAP(r11);                                  \
 218         lis     r10,msr@h;                                      \
 219         ori     r10,r10,msr@l;                                  \
 220         copyee(r10, r9);                                        \
 221         bl      tfer;                                           \
 222         .long   hdlr;                                           \
 223         .long   ret
 224
 225 #define COPY_EE(d, s)           rlwimi d,s,0,16,16
 226 #define NOCOPY(d, s)
 227
 228 #define EXC_XFER_STD(n, hdlr)           \
 229         EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \
 230                           ret_from_except_full)
 231
 232 #define EXC_XFER_LITE(n, hdlr)          \
 233         EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \
 234                           ret_from_except)
 235
 236 #define EXC_XFER_EE(n, hdlr)            \
 237         EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \
 238                           ret_from_except_full)
 239
 240 #define EXC_XFER_EE_LITE(n, hdlr)       \
 241         EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \
 242                           ret_from_except)
 243
 244
 245 /*
 246  * 0x0100 - Critical Interrupt Exception
 247  */
 248         CRITICAL_EXCEPTION(0x0100, CriticalInterrupt, UnknownException)
 249
 250 /*
 251  * 0x0200 - Machine Check Exception
 252  */
 253         CRITICAL_EXCEPTION(0x0200, MachineCheck, MachineCheckException)
 254
 255 /*
 256  * 0x0300 - Data Storage Exception
 257  * This happens for just a few reasons.  U0 set (but we don't do that),
 258  * or zone protection fault (user violation, write to protected page).
 259  * If this is just an update of modified status, we do that quickly
 260  * and exit.  Otherwise, we call heavywight functions to do the work.
 261  */
 262         START_EXCEPTION(0x0300, DataStorage)
 263         mtspr   SPRN_SPRG0, r10         /* Save some working registers */
 264         mtspr   SPRN_SPRG1, r11
 265 #ifdef CONFIG_403GCX
 266         stw     r12, 0(r0)
 267         stw     r9, 4(r0)
 268         mfcr    r11
 269         mfspr   r12, SPRN_PID
 270         stw     r11, 8(r0)
 271         stw     r12, 12(r0)
 272 #else
 273         mtspr   SPRN_SPRG4, r12
 274         mtspr   SPRN_SPRG5, r9
 275         mfcr    r11
 276         mfspr   r12, SPRN_PID
 277         mtspr   SPRN_SPRG7, r11
 278         mtspr   SPRN_SPRG6, r12
 279 #endif
 280
 281         /* First, check if it was a zone fault (which means a user
 282         * tried to access a kernel or read-protected page - always
 283         * a SEGV).  All other faults here must be stores, so no
 284         * need to check ESR_DST as well. */
 285         mfspr   r10, SPRN_ESR
 286         andis.  r10, r10, ESR_DIZ@h
 287         bne     2f
 288
 289         mfspr   r10, SPRN_DEAR          /* Get faulting address */
 290
 291         /* If we are faulting a kernel address, we have to use the
 292          * kernel page tables.
 293          */
 294         andis.  r11, r10, 0x8000
 295         beq     3f
 296         lis     r11, swapper_pg_dir@h
 297         ori     r11, r11, swapper_pg_dir@l
 298         li      r9, 0
 299         mtspr   SPRN_PID, r9            /* TLB will have 0 TID */
 300         b       4f
 301
 302         /* Get the PGD for the current thread.
 303          */
 304 3:
 305         mfspr   r11,SPRN_SPRG3
 306         lwz     r11,PGDIR(r11)
 307 4:
 308         tophys(r11, r11)
 309         rlwimi  r11, r10, 12, 20, 29    /* Create L1 (pgdir/pmd) address */
 310         lwz     r11, 0(r11)             /* Get L1 entry */
 311         rlwinm. r12, r11, 0, 0, 19      /* Extract L2 (pte) base address */
 312         beq     2f                      /* Bail if no table */
 313
 314         rlwimi  r12, r10, 22, 20, 29    /* Compute PTE address */
 315         lwz     r11, 0(r12)             /* Get Linux PTE */
 316
 317         andi.   r9, r11, _PAGE_RW       /* Is it writeable? */
 318         beq     2f                      /* Bail if not */
 319
 320         /* Update 'changed'.
 321         */
 322         ori     r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
 323         stw     r11, 0(r12)             /* Update Linux page table */
 324
 325         /* Most of the Linux PTE is ready to load into the TLB LO.
 326          * We set ZSEL, where only the LS-bit determines user access.
 327          * We set execute, because we don't have the granularity to
 328          * properly set this at the page level (Linux problem).
 329          * If shared is set, we cause a zero PID->TID load.
 330          * Many of these bits are software only.  Bits we don't set
 331          * here we (properly should) assume have the appropriate value.
 332          */
 333         li      r12, 0x0ce2
 334         andc    r11, r11, r12           /* Make sure 20, 21 are zero */
 335
 336         /* find the TLB index that caused the fault.  It has to be here.
 337         */
 338         tlbsx   r9, 0, r10
 339
 340         tlbwe   r11, r9, TLB_DATA               /* Load TLB LO */
 341
 342         /* Done...restore registers and get out of here.
 343         */
 344 #ifdef CONFIG_403GCX
 345         lwz     r12, 12(r0)
 346         lwz     r11, 8(r0)
 347         mtspr   SPRN_PID, r12
 348         mtcr    r11
 349         lwz     r9, 4(r0)
 350         lwz     r12, 0(r0)
 351 #else
 352         mfspr   r12, SPRN_SPRG6
 353         mfspr   r11, SPRN_SPRG7
 354         mtspr   SPRN_PID, r12
 355         mtcr    r11
 356         mfspr   r9, SPRN_SPRG5
 357         mfspr   r12, SPRN_SPRG4
 358 #endif
 359         mfspr   r11, SPRN_SPRG1
 360         mfspr   r10, SPRN_SPRG0
 361         PPC405_ERR77_SYNC
 362         rfi                     /* Should sync shadow TLBs */
 363         b       .               /* prevent prefetch past rfi */
 364
 365 2:
 366         /* The bailout.  Restore registers to pre-exception conditions
 367          * and call the heavyweights to help us out.
 368          */
 369 #ifdef CONFIG_403GCX
 370         lwz     r12, 12(r0)
 371         lwz     r11, 8(r0)
 372         mtspr   SPRN_PID, r12
 373         mtcr    r11
 374         lwz     r9, 4(r0)
 375         lwz     r12, 0(r0)
 376 #else
 377         mfspr   r12, SPRN_SPRG6
 378         mfspr   r11, SPRN_SPRG7
 379         mtspr   SPRN_PID, r12
 380         mtcr    r11
 381         mfspr   r9, SPRN_SPRG5
 382         mfspr   r12, SPRN_SPRG4
 383 #endif
 384         mfspr   r11, SPRN_SPRG1
 385         mfspr   r10, SPRN_SPRG0
 386         b       DataAccess
 387
 388 /*
 389  * 0x0400 - Instruction Storage Exception
 390  * This is caused by a fetch from non-execute or guarded pages.
 391  */
 392         START_EXCEPTION(0x0400, InstructionAccess)
 393         NORMAL_EXCEPTION_PROLOG
 394         mr      r4,r12                  /* Pass SRR0 as arg2 */
 395         li      r5,0                    /* Pass zero as arg3 */
 396         EXC_XFER_EE_LITE(0x400, handle_page_fault)
 397
 398 /* 0x0500 - External Interrupt Exception */
 399         EXCEPTION(0x0500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
 400
 401 /* 0x0600 - Alignment Exception */
 402         START_EXCEPTION(0x0600, Alignment)
 403         NORMAL_EXCEPTION_PROLOG
 404         mfspr   r4,SPRN_DEAR            /* Grab the DEAR and save it */
 405         stw     r4,_DEAR(r11)
 406         addi    r3,r1,STACK_FRAME_OVERHEAD
 407         EXC_XFER_EE(0x600, AlignmentException)
 408
 409 /* 0x0700 - Program Exception */
 410         START_EXCEPTION(0x0700, ProgramCheck)
 411         NORMAL_EXCEPTION_PROLOG
 412         mfspr   r4,SPRN_ESR             /* Grab the ESR and save it */
 413         stw     r4,_ESR(r11)
 414         addi    r3,r1,STACK_FRAME_OVERHEAD
 415         EXC_XFER_STD(0x700, ProgramCheckException)
 416
 417         EXCEPTION(0x0800, Trap_08, UnknownException, EXC_XFER_EE)
 418         EXCEPTION(0x0900, Trap_09, UnknownException, EXC_XFER_EE)
 419         EXCEPTION(0x0A00, Trap_0A, UnknownException, EXC_XFER_EE)
 420         EXCEPTION(0x0B00, Trap_0B, UnknownException, EXC_XFER_EE)
 421
 422 /* 0x0C00 - System Call Exception */
 423         START_EXCEPTION(0x0C00, SystemCall)
 424         NORMAL_EXCEPTION_PROLOG
 425         EXC_XFER_EE_LITE(0xc00, DoSyscall)
 426
 427         EXCEPTION(0x0D00, Trap_0D, UnknownException, EXC_XFER_EE)
 428         EXCEPTION(0x0E00, Trap_0E, UnknownException, EXC_XFER_EE)
 429         EXCEPTION(0x0F00, Trap_0F, UnknownException, EXC_XFER_EE)
 430
 431 /* 0x1000 - Programmable Interval Timer (PIT) Exception */
 432         START_EXCEPTION(0x1000, Decrementer)
 433         NORMAL_EXCEPTION_PROLOG
 434         lis     r0,TSR_PIS@h
 435         mtspr   SPRN_TSR,r0             /* Clear the PIT exception */
 436         addi    r3,r1,STACK_FRAME_OVERHEAD
 437         EXC_XFER_LITE(0x1000, timer_interrupt)
 438
 439 #if 0
 440 /* NOTE:
 441  * FIT and WDT handlers are not implemented yet.
 442  */
 443
 444 /* 0x1010 - Fixed Interval Timer (FIT) Exception
 445 */
 446         STND_EXCEPTION(0x1010,  FITException,           UnknownException)
 447
 448 /* 0x1020 - Watchdog Timer (WDT) Exception
 449 */
 450
 451         CRITICAL_EXCEPTION(0x1020, WDTException, UnknownException)
 452 #endif
 453
 454 /* 0x1100 - Data TLB Miss Exception
 455  * As the name implies, translation is not in the MMU, so search the
 456  * page tables and fix it.  The only purpose of this function is to
 457  * load TLB entries from the page table if they exist.
 458  */
 459         START_EXCEPTION(0x1100, DTLBMiss)
 460         mtspr   SPRN_SPRG0, r10         /* Save some working registers */
 461         mtspr   SPRN_SPRG1, r11
 462 #ifdef CONFIG_403GCX
 463         stw     r12, 0(r0)
 464         stw     r9, 4(r0)
 465         mfcr    r11
 466         mfspr   r12, SPRN_PID
 467         stw     r11, 8(r0)
 468         stw     r12, 12(r0)
 469 #else
 470         mtspr   SPRN_SPRG4, r12
 471         mtspr   SPRN_SPRG5, r9
 472         mfcr    r11
 473         mfspr   r12, SPRN_PID
 474         mtspr   SPRN_SPRG7, r11
 475         mtspr   SPRN_SPRG6, r12
 476 #endif
 477         mfspr   r10, SPRN_DEAR          /* Get faulting address */
 478
 479         /* If we are faulting a kernel address, we have to use the
 480          * kernel page tables.
 481          */
 482         andis.  r11, r10, 0x8000
 483         beq     3f
 484         lis     r11, swapper_pg_dir@h
 485         ori     r11, r11, swapper_pg_dir@l
 486         li      r9, 0
 487         mtspr   SPRN_PID, r9            /* TLB will have 0 TID */
 488         b       4f
 489
 490         /* Get the PGD for the current thread.
 491          */
 492 3:
 493         mfspr   r11,SPRN_SPRG3
 494         lwz     r11,PGDIR(r11)
 495 4:
 496         tophys(r11, r11)
 497         rlwimi  r11, r10, 12, 20, 29    /* Create L1 (pgdir/pmd) address */
 498         lwz     r12, 0(r11)             /* Get L1 entry */
 499         andi.   r9, r12, _PMD_PRESENT   /* Check if it points to a PTE page */
 500         beq     2f                      /* Bail if no table */
 501
 502         rlwimi  r12, r10, 22, 20, 29    /* Compute PTE address */
 503         lwz     r11, 0(r12)             /* Get Linux PTE */
 504         andi.   r9, r11, _PAGE_PRESENT
 505         beq     5f
 506
 507         ori     r11, r11, _PAGE_ACCESSED
 508         stw     r11, 0(r12)
 509
 510         /* Create TLB tag.  This is the faulting address plus a static
 511          * set of bits.  These are size, valid, E, U0.
 512         */
 513         li      r12, 0x00c0
 514         rlwimi  r10, r12, 0, 20, 31
 515
 516         b       finish_tlb_load
 517
 518 2:      /* Check for possible large-page pmd entry */
 519         rlwinm. r9, r12, 2, 22, 24
 520         beq     5f
 521
 522         /* Create TLB tag.  This is the faulting address, plus a static
 523          * set of bits (valid, E, U0) plus the size from the PMD.
 524          */
 525         ori     r9, r9, 0x40
 526         rlwimi  r10, r9, 0, 20, 31
 527         mr      r11, r12
 528
 529         b       finish_tlb_load
 530
 531 5:
 532         /* The bailout.  Restore registers to pre-exception conditions
 533          * and call the heavyweights to help us out.
 534          */
 535 #ifdef CONFIG_403GCX
 536         lwz     r12, 12(r0)
 537         lwz     r11, 8(r0)
 538         mtspr   SPRN_PID, r12
 539         mtcr    r11
 540         lwz     r9, 4(r0)
 541         lwz     r12, 0(r0)
 542 #else
 543         mfspr   r12, SPRN_SPRG6
 544         mfspr   r11, SPRN_SPRG7
 545         mtspr   SPRN_PID, r12
 546         mtcr    r11
 547         mfspr   r9, SPRN_SPRG5
 548         mfspr   r12, SPRN_SPRG4
 549 #endif
 550         mfspr   r11, SPRN_SPRG1
 551         mfspr   r10, SPRN_SPRG0
 552         b       DataAccess
 553
 554 /* 0x1200 - Instruction TLB Miss Exception
 555  * Nearly the same as above, except we get our information from different
 556  * registers and bailout to a different point.
 557  */
 558         START_EXCEPTION(0x1200, ITLBMiss)
 559         mtspr   SPRN_SPRG0, r10         /* Save some working registers */
 560         mtspr   SPRN_SPRG1, r11
 561 #ifdef CONFIG_403GCX
 562         stw     r12, 0(r0)
 563         stw     r9, 4(r0)
 564         mfcr    r11
 565         mfspr   r12, SPRN_PID
 566         stw     r11, 8(r0)
 567         stw     r12, 12(r0)
 568 #else
 569         mtspr   SPRN_SPRG4, r12
 570         mtspr   SPRN_SPRG5, r9
 571         mfcr    r11
 572         mfspr   r12, SPRN_PID
 573         mtspr   SPRN_SPRG7, r11
 574         mtspr   SPRN_SPRG6, r12
 575 #endif
 576         mfspr   r10, SPRN_SRR0          /* Get faulting address */
 577
 578         /* If we are faulting a kernel address, we have to use the
 579          * kernel page tables.
 580          */
 581         andis.  r11, r10, 0x8000
 582         beq     3f
 583         lis     r11, swapper_pg_dir@h
 584         ori     r11, r11, swapper_pg_dir@l
 585         li      r9, 0
 586         mtspr   SPRN_PID, r9            /* TLB will have 0 TID */
 587         b       4f
 588
 589         /* Get the PGD for the current thread.
 590          */
 591 3:
 592         mfspr   r11,SPRN_SPRG3
 593         lwz     r11,PGDIR(r11)
 594 4:
 595         tophys(r11, r11)
 596         rlwimi  r11, r10, 12, 20, 29    /* Create L1 (pgdir/pmd) address */
 597         lwz     r12, 0(r11)             /* Get L1 entry */
 598         andi.   r9, r12, _PMD_PRESENT   /* Check if it points to a PTE page */
 599         beq     2f                      /* Bail if no table */
 600
 601         rlwimi  r12, r10, 22, 20, 29    /* Compute PTE address */
 602         lwz     r11, 0(r12)             /* Get Linux PTE */
 603         andi.   r9, r11, _PAGE_PRESENT
 604         beq     5f
 605
 606         ori     r11, r11, _PAGE_ACCESSED
 607         stw     r11, 0(r12)
 608
 609         /* Create TLB tag.  This is the faulting address plus a static
 610          * set of bits.  These are size, valid, E, U0.
 611         */
 612         li      r12, 0x00c0
 613         rlwimi  r10, r12, 0, 20, 31
 614
 615         b       finish_tlb_load
 616
 617 2:      /* Check for possible large-page pmd entry */
 618         rlwinm. r9, r12, 2, 22, 24
 619         beq     5f
 620
 621         /* Create TLB tag.  This is the faulting address, plus a static
 622          * set of bits (valid, E, U0) plus the size from the PMD.
 623          */
 624         ori     r9, r9, 0x40
 625         rlwimi  r10, r9, 0, 20, 31
 626         mr      r11, r12
 627
 628         b       finish_tlb_load
 629
 630 5:
 631         /* The bailout.  Restore registers to pre-exception conditions
 632          * and call the heavyweights to help us out.
 633          */
 634 #ifdef CONFIG_403GCX
 635         lwz     r12, 12(r0)
 636         lwz     r11, 8(r0)
 637         mtspr   SPRN_PID, r12
 638         mtcr    r11
 639         lwz     r9, 4(r0)
 640         lwz     r12, 0(r0)
 641 #else
 642         mfspr   r12, SPRN_SPRG6
 643         mfspr   r11, SPRN_SPRG7
 644         mtspr   SPRN_PID, r12
 645         mtcr    r11
 646         mfspr   r9, SPRN_SPRG5
 647         mfspr   r12, SPRN_SPRG4
 648 #endif
 649         mfspr   r11, SPRN_SPRG1
 650         mfspr   r10, SPRN_SPRG0
 651         b       InstructionAccess
 652
 653         EXCEPTION(0x1300, Trap_13, UnknownException, EXC_XFER_EE)
 654         EXCEPTION(0x1400, Trap_14, UnknownException, EXC_XFER_EE)
 655         EXCEPTION(0x1500, Trap_15, UnknownException, EXC_XFER_EE)
 656         EXCEPTION(0x1600, Trap_16, UnknownException, EXC_XFER_EE)
 657 #ifdef CONFIG_IBM405_ERR51
 658         /* 405GP errata 51 */
 659         START_EXCEPTION(0x1700, Trap_17)
 660         b DTLBMiss
 661 #else
 662         EXCEPTION(0x1700, Trap_17, UnknownException, EXC_XFER_EE)
 663 #endif
 664         EXCEPTION(0x1800, Trap_18, UnknownException, EXC_XFER_EE)
 665         EXCEPTION(0x1900, Trap_19, UnknownException, EXC_XFER_EE)
 666         EXCEPTION(0x1A00, Trap_1A, UnknownException, EXC_XFER_EE)
 667         EXCEPTION(0x1B00, Trap_1B, UnknownException, EXC_XFER_EE)
 668         EXCEPTION(0x1C00, Trap_1C, UnknownException, EXC_XFER_EE)
 669         EXCEPTION(0x1D00, Trap_1D, UnknownException, EXC_XFER_EE)
 670         EXCEPTION(0x1E00, Trap_1E, UnknownException, EXC_XFER_EE)
 671         EXCEPTION(0x1F00, Trap_1F, UnknownException, EXC_XFER_EE)
 672
 673 /* Check for a single step debug exception while in an exception
 674  * handler before state has been saved.  This is to catch the case
 675  * where an instruction that we are trying to single step causes
 676  * an exception (eg ITLB/DTLB miss) and thus the first instruction of
 677  * the exception handler generates a single step debug exception.
 678  *
 679  * If we get a debug trap on the first instruction of an exception handler,
 680  * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
 681  * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
 682  * The exception handler was handling a non-critical interrupt, so it will
 683  * save (and later restore) the MSR via SPRN_SRR1, which will still have
 684  * the MSR_DE bit set.
 685  */
 686         /* 0x2000 - Debug Exception */
 687         START_EXCEPTION(0x2000, DebugTrap)
 688         CRITICAL_EXCEPTION_PROLOG
 689
 690         /*
 691          * If this is a single step or branch-taken exception in an
 692          * exception entry sequence, it was probably meant to apply to
 693          * the code where the exception occurred (since exception entry
 694          * doesn't turn off DE automatically).  We simulate the effect
 695          * of turning off DE on entry to an exception handler by turning
 696          * off DE in the SRR3 value and clearing the debug status.
 697          */
 698         mfspr   r10,SPRN_DBSR           /* check single-step/branch taken */
 699         andis.  r10,r10,DBSR_IC@h
 700         beq+    2f
 701
 702         andi.   r10,r9,MSR_IR|MSR_PR    /* check supervisor + MMU off */
 703         beq     1f                      /* branch and fix it up */
 704
 705         mfspr   r10,SPRN_SRR2           /* Faulting instruction address */
 706         cmplwi  r10,0x2100
 707         bgt+    2f                      /* address above exception vectors */
 708
 709         /* here it looks like we got an inappropriate debug exception. */
 710 1:      rlwinm  r9,r9,0,~MSR_DE         /* clear DE in the SRR3 value */
 711         lis     r10,DBSR_IC@h           /* clear the IC event */
 712         mtspr   SPRN_DBSR,r10
 713         /* restore state and get out */
 714         lwz     r10,_CCR(r11)
 715         lwz     r0,GPR0(r11)
 716         lwz     r1,GPR1(r11)
 717         mtcrf   0x80,r10
 718         mtspr   SPRN_SRR2,r12
 719         mtspr   SPRN_SRR3,r9
 720         lwz     r9,GPR9(r11)
 721         lwz     r12,GPR12(r11)
 722         lwz     r10,crit_r10@l(0)
 723         lwz     r11,crit_r11@l(0)
 724         PPC405_ERR77_SYNC
 725         rfci
 726         b       .
 727
 728         /* continue normal handling for a critical exception... */
 729 2:      mfspr   r4,SPRN_DBSR
 730         addi    r3,r1,STACK_FRAME_OVERHEAD
 731         EXC_XFER_TEMPLATE(DebugException, 0x2002, \
 732                 (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
 733                 NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)
 734
 735 /*
 736  * The other Data TLB exceptions bail out to this point
 737  * if they can't resolve the lightweight TLB fault.
 738  */
 739 DataAccess:
 740         NORMAL_EXCEPTION_PROLOG
 741         mfspr   r5,SPRN_ESR             /* Grab the ESR, save it, pass arg3 */
 742         stw     r5,_ESR(r11)
 743         mfspr   r4,SPRN_DEAR            /* Grab the DEAR, save it, pass arg2 */
 744         EXC_XFER_EE_LITE(0x300, handle_page_fault)
 745
 746 /* Other PowerPC processors, namely those derived from the 6xx-series
 747  * have vectors from 0x2100 through 0x2F00 defined, but marked as reserved.
 748  * However, for the 4xx-series processors these are neither defined nor
 749  * reserved.
 750  */
 751
 752         /* Damn, I came up one instruction too many to fit into the
 753          * exception space :-).  Both the instruction and data TLB
 754          * miss get to this point to load the TLB.
 755          *      r10 - TLB_TAG value
 756          *      r11 - Linux PTE
 757          *      r12, r9 - avilable to use
 758          *      PID - loaded with proper value when we get here
 759          *      Upon exit, we reload everything and RFI.
 760          * Actually, it will fit now, but oh well.....a common place
 761          * to load the TLB.
 762          */
 763 tlb_4xx_index:
 764         .long   0
 765 finish_tlb_load:
 766         /* load the next available TLB index.
 767         */
 768         lwz     r9, tlb_4xx_index@l(0)
 769         addi    r9, r9, 1
 770         andi.   r9, r9, (PPC4XX_TLB_SIZE-1)
 771         stw     r9, tlb_4xx_index@l(0)
 772
 773 6:
 774         /*
 775          * Clear out the software-only bits in the PTE to generate the
 776          * TLB_DATA value.  These are the bottom 2 bits of the RPM, the
 777          * top 3 bits of the zone field, and M.
 778          */
 779         li      r12, 0x0ce2
 780         andc    r11, r11, r12
 781
 782         tlbwe   r11, r9, TLB_DATA               /* Load TLB LO */
 783         tlbwe   r10, r9, TLB_TAG                /* Load TLB HI */
 784
 785         /* Done...restore registers and get out of here.
 786         */
 787 #ifdef CONFIG_403GCX
 788         lwz     r12, 12(r0)
 789         lwz     r11, 8(r0)
 790         mtspr   SPRN_PID, r12
 791         mtcr    r11
 792         lwz     r9, 4(r0)
 793         lwz     r12, 0(r0)
 794 #else
 795         mfspr   r12, SPRN_SPRG6
 796         mfspr   r11, SPRN_SPRG7
 797         mtspr   SPRN_PID, r12
 798         mtcr    r11
 799         mfspr   r9, SPRN_SPRG5
 800         mfspr   r12, SPRN_SPRG4
 801 #endif
 802         mfspr   r11, SPRN_SPRG1
 803         mfspr   r10, SPRN_SPRG0
 804         PPC405_ERR77_SYNC
 805         rfi                     /* Should sync shadow TLBs */
 806         b       .               /* prevent prefetch past rfi */
 807
 808 /* extern void giveup_fpu(struct task_struct *prev)
 809  *
 810  * The PowerPC 4xx family of processors do not have an FPU, so this just
 811  * returns.
 812  */
 813 _GLOBAL(giveup_fpu)
 814         blr
 815
 816 /* This is where the main kernel code starts.
 817  */
 818 start_here:
 819
 820         /* ptr to current */
 821         lis     r2,init_task@h
 822         ori     r2,r2,init_task@l
 823
 824         /* ptr to phys current thread */
 825         tophys(r4,r2)
 826         addi    r4,r4,THREAD    /* init task's THREAD */
 827         mtspr   SPRN_SPRG3,r4
 828
 829         /* stack */
 830         lis     r1,init_thread_union@ha
 831         addi    r1,r1,init_thread_union@l
 832         li      r0,0
 833         stwu    r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
 834
 835         bl      early_init      /* We have to do this with MMU on */
 836
 837 /*
 838  * Decide what sort of machine this is and initialize the MMU.
 839  */
 840         mr      r3,r31
 841         mr      r4,r30
 842         mr      r5,r29
 843         mr      r6,r28
 844         mr      r7,r27
 845         bl      machine_init
 846         bl      MMU_init
 847
 848 /* Go back to running unmapped so we can load up new values
 849  * and change to using our exception vectors.
 850  * On the 4xx, all we have to do is invalidate the TLB to clear
 851  * the old 16M byte TLB mappings.
 852  */
 853         lis     r4,2f@h
 854         ori     r4,r4,2f@l
 855         tophys(r4,r4)
 856         lis     r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@h
 857         ori     r3,r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@l
 858         mtspr   SPRN_SRR0,r4
 859         mtspr   SPRN_SRR1,r3
 860         rfi
 861         b       .               /* prevent prefetch past rfi */
 862
 863 /* Load up the kernel context */
 864 2:
 865         sync                    /* Flush to memory before changing TLB */
 866         tlbia
 867         isync                   /* Flush shadow TLBs */
 868
 869         /* set up the PTE pointers for the Abatron bdiGDB.
 870         */
 871         lis     r6, swapper_pg_dir@h
 872         ori     r6, r6, swapper_pg_dir@l
 873         lis     r5, abatron_pteptrs@h
 874         ori     r5, r5, abatron_pteptrs@l
 875         stw     r5, 0xf0(r0)    /* Must match your Abatron config file */
 876         tophys(r5,r5)
 877         stw     r6, 0(r5)
 878
 879 /* Now turn on the MMU for real! */
 880         lis     r4,MSR_KERNEL@h
 881         ori     r4,r4,MSR_KERNEL@l
 882         lis     r3,start_kernel@h
 883         ori     r3,r3,start_kernel@l
 884         mtspr   SPRN_SRR0,r3
 885         mtspr   SPRN_SRR1,r4
 886         rfi                     /* enable MMU and jump to start_kernel */
 887         b       .               /* prevent prefetch past rfi */
 888
 889 /* Set up the initial MMU state so we can do the first level of
 890  * kernel initialization.  This maps the first 16 MBytes of memory 1:1
 891  * virtual to physical and more importantly sets the cache mode.
 892  */
 893 initial_mmu:
 894         tlbia                   /* Invalidate all TLB entries */
 895         isync
 896
 897         /* We should still be executing code at physical address 0x0000xxxx
 898          * at this point. However, start_here is at virtual address
 899          * 0xC000xxxx. So, set up a TLB mapping to cover this once
 900          * translation is enabled.
 901          */
 902
 903         lis     r3,KERNELBASE@h         /* Load the kernel virtual address */
 904         ori     r3,r3,KERNELBASE@l
 905         tophys(r4,r3)                   /* Load the kernel physical address */
 906
 907         iccci   r0,r3                   /* Invalidate the i-cache before use */
 908
 909         /* Load the kernel PID.
 910         */
 911         li      r0,0
 912         mtspr   SPRN_PID,r0
 913         sync
 914
 915         /* Configure and load two entries into TLB slots 62 and 63.
 916          * In case we are pinning TLBs, these are reserved in by the
 917          * other TLB functions.  If not reserving, then it doesn't
 918          * matter where they are loaded.
 919          */
 920         clrrwi  r4,r4,10                /* Mask off the real page number */
 921         ori     r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */
 922
 923         clrrwi  r3,r3,10                /* Mask off the effective page number */
 924         ori     r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M))
 925
 926         li      r0,63                    /* TLB slot 63 */
 927
 928         tlbwe   r4,r0,TLB_DATA          /* Load the data portion of the entry */
 929         tlbwe   r3,r0,TLB_TAG           /* Load the tag portion of the entry */
 930
 931 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(SERIAL_DEBUG_IO_BASE)
 932
 933         /* Load a TLB entry for the UART, so that ppc4xx_progress() can use
 934          * the UARTs nice and early.  We use a 4k real==virtual mapping. */
 935
 936         lis     r3,SERIAL_DEBUG_IO_BASE@h
 937         ori     r3,r3,SERIAL_DEBUG_IO_BASE@l
 938         mr      r4,r3
 939         clrrwi  r4,r4,12
 940         ori     r4,r4,(TLB_WR|TLB_I|TLB_M|TLB_G)
 941
 942         clrrwi  r3,r3,12
 943         ori     r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K))
 944
 945         li      r0,0                    /* TLB slot 0 */
 946         tlbwe   r4,r0,TLB_DATA
 947         tlbwe   r3,r0,TLB_TAG
 948 #endif /* CONFIG_SERIAL_DEBUG_TEXT && SERIAL_DEBUG_IO_BASE */
 949
 950         isync
 951
 952         /* Establish the exception vector base
 953         */
 954         lis     r4,KERNELBASE@h         /* EVPR only uses the high 16-bits */
 955         tophys(r0,r4)                   /* Use the physical address */
 956         mtspr   SPRN_EVPR,r0
 957
 958         blr
 959
 960 _GLOBAL(abort)
 961         mfspr   r13,SPRN_DBCR0
 962         oris    r13,r13,DBCR0_RST_SYSTEM@h
 963         mtspr   SPRN_DBCR0,r13
 964
 965 _GLOBAL(set_context)
 966
 967 #ifdef CONFIG_BDI_SWITCH
 968         /* Context switch the PTE pointer for the Abatron BDI2000.
 969          * The PGDIR is the second parameter.
 970          */
 971         lis     r5, KERNELBASE@h
 972         lwz     r5, 0xf0(r5)
 973         stw     r4, 0x4(r5)
 974 #endif
 975         sync
 976         mtspr   SPRN_PID,r3
 977         isync                           /* Need an isync to flush shadow */
 978                                         /* TLBs after changing PID */
 979         blr
 980
 981 /* We put a few things here that have to be page-aligned. This stuff
 982  * goes at the beginning of the data segment, which is page-aligned.
 983  */
 984         .data
 985 _GLOBAL(sdata)
 986 _GLOBAL(empty_zero_page)
 987         .space  4096
 988 _GLOBAL(swapper_pg_dir)
 989         .space  4096
 990
 991
 992 /* Stack for handling critical exceptions from kernel mode */
 993         .section .bss
 994         .align 12
 995 exception_stack_bottom:
 996         .space  4096
 997 critical_stack_top:
 998 _GLOBAL(exception_stack_top)
 999
1000 /* This space gets a copy of optional info passed to us by the bootstrap
1001  * which is used to pass parameters into the kernel like root=/dev/sda1, etc.
1002  */
1003 _GLOBAL(cmd_line)
1004         .space  512
1005
1006 /* Room for two PTE pointers, usually the kernel and current user pointers
1007  * to their respective root page table.
1008  */
1009 abatron_pteptrs:
1010         .space  8