2 * arch/ppc/platforms/4xx/bamboo.c
4 * Bamboo board specific routines
6 * Wade Farnsworth <wfarnsworth@mvista.com>
7 * Copyright 2004 MontaVista Software Inc.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
15 #include <linux/config.h>
16 #include <linux/stddef.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/errno.h>
20 #include <linux/reboot.h>
21 #include <linux/pci.h>
22 #include <linux/kdev_t.h>
23 #include <linux/types.h>
24 #include <linux/major.h>
25 #include <linux/blkdev.h>
26 #include <linux/console.h>
27 #include <linux/delay.h>
28 #include <linux/ide.h>
29 #include <linux/initrd.h>
30 #include <linux/irq.h>
31 #include <linux/seq_file.h>
32 #include <linux/root_dev.h>
33 #include <linux/tty.h>
34 #include <linux/serial.h>
35 #include <linux/serial_core.h>
36 #include <linux/ethtool.h>
38 #include <asm/system.h>
39 #include <asm/pgtable.h>
43 #include <asm/machdep.h>
45 #include <asm/pci-bridge.h>
48 #include <asm/bootinfo.h>
49 #include <asm/ppc4xx_pic.h>
50 #include <asm/ppcboot.h>
52 #include <syslib/gen550.h>
53 #include <syslib/ibm440gx_common.h>
56 * This is a horrible kludge, we eventually need to abstract this
57 * generic PHY stuff, so the standard phy mode defines can be
58 * easily used from arch code.
60 #include "../../../../drivers/net/ibm_emac/ibm_emac_phy.h"
64 static struct ibm44x_clocks clocks __initdata
;
67 * Bamboo external IRQ triggering/polarity settings
69 unsigned char ppc4xx_uic_ext_irq_cfg
[] __initdata
= {
70 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* IRQ0: Ethernet transceiver */
71 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* IRQ1: Expansion connector */
72 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* IRQ2: PCI slot 0 */
73 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* IRQ3: PCI slot 1 */
74 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* IRQ4: PCI slot 2 */
75 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* IRQ5: PCI slot 3 */
76 (IRQ_SENSE_EDGE
| IRQ_POLARITY_NEGATIVE
), /* IRQ6: SMI pushbutton */
77 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* IRQ7: EXT */
78 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* IRQ8: EXT */
79 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* IRQ9: EXT */
83 bamboo_calibrate_decr(void)
87 if (mfspr(SPRN_CCR1
) & CCR1_TCS
)
92 ibm44x_calibrate_decr(freq
);
97 bamboo_show_cpuinfo(struct seq_file
*m
)
99 seq_printf(m
, "vendor\t\t: IBM\n");
100 seq_printf(m
, "machine\t\t: PPC440EP EVB (Bamboo)\n");
106 bamboo_map_irq(struct pci_dev
*dev
, unsigned char idsel
, unsigned char pin
)
108 static char pci_irq_table
[][4] =
110 * PCI IDSEL/INTPIN->INTLINE
114 { 28, 28, 28, 28 }, /* IDSEL 1 - PCI Slot 0 */
115 { 27, 27, 27, 27 }, /* IDSEL 2 - PCI Slot 1 */
116 { 26, 26, 26, 26 }, /* IDSEL 3 - PCI Slot 2 */
117 { 25, 25, 25, 25 }, /* IDSEL 4 - PCI Slot 3 */
120 const long min_idsel
= 1, max_idsel
= 4, irqs_per_slot
= 4;
121 return PCI_IRQ_TABLE_LOOKUP
;
124 static void __init
bamboo_set_emacdata(void)
126 unsigned char * selection1_base
;
128 struct ocp_func_emac_data
*emacdata
;
132 selection1_base
= ioremap64(BAMBOO_FPGA_SELECTION1_REG_ADDR
, 16);
133 selection1_val
= readb(selection1_base
);
134 iounmap((void *) selection1_base
);
135 if (BAMBOO_SEL_MII(selection1_val
))
137 else if (BAMBOO_SEL_RMII(selection1_val
))
138 mode
= PHY_MODE_RMII
;
140 mode
= PHY_MODE_SMII
;
142 /* Set mac_addr and phy mode for each EMAC */
144 def
= ocp_get_one_device(OCP_VENDOR_IBM
, OCP_FUNC_EMAC
, 0);
145 emacdata
= def
->additions
;
146 memcpy(emacdata
->mac_addr
, __res
.bi_enetaddr
, 6);
147 emacdata
->phy_mode
= mode
;
149 def
= ocp_get_one_device(OCP_VENDOR_IBM
, OCP_FUNC_EMAC
, 1);
150 emacdata
= def
->additions
;
151 memcpy(emacdata
->mac_addr
, __res
.bi_enet1addr
, 6);
152 emacdata
->phy_mode
= mode
;
156 bamboo_exclude_device(unsigned char bus
, unsigned char devfn
)
158 return (bus
== 0 && devfn
== 0);
161 #define PCI_READW(offset) \
162 (readw((void *)((u32)pci_reg_base+offset)))
164 #define PCI_WRITEW(value, offset) \
165 (writew(value, (void *)((u32)pci_reg_base+offset)))
167 #define PCI_WRITEL(value, offset) \
168 (writel(value, (void *)((u32)pci_reg_base+offset)))
171 bamboo_setup_pci(void)
174 unsigned long memory_size
;
175 memory_size
= ppc_md
.find_end_of_memory();
177 pci_reg_base
= ioremap64(BAMBOO_PCIL0_BASE
, BAMBOO_PCIL0_SIZE
);
179 /* Enable PCI I/O, Mem, and Busmaster cycles */
180 PCI_WRITEW(PCI_READW(PCI_COMMAND
) |
182 PCI_COMMAND_MASTER
, PCI_COMMAND
);
184 /* Disable region first */
185 PCI_WRITEL(0, BAMBOO_PCIL0_PMM0MA
);
187 /* PLB starting addr: 0x00000000A0000000 */
188 PCI_WRITEL(BAMBOO_PCI_PHY_MEM_BASE
, BAMBOO_PCIL0_PMM0LA
);
190 /* PCI start addr, 0xA0000000 (PCI Address) */
191 PCI_WRITEL(BAMBOO_PCI_MEM_BASE
, BAMBOO_PCIL0_PMM0PCILA
);
192 PCI_WRITEL(0, BAMBOO_PCIL0_PMM0PCIHA
);
194 /* Enable no pre-fetch, enable region */
195 PCI_WRITEL(((0xffffffff -
196 (BAMBOO_PCI_UPPER_MEM
- BAMBOO_PCI_MEM_BASE
)) | 0x01),
197 BAMBOO_PCIL0_PMM0MA
);
199 /* Disable region one */
200 PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA
);
201 PCI_WRITEL(0, BAMBOO_PCIL0_PMM1LA
);
202 PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCILA
);
203 PCI_WRITEL(0, BAMBOO_PCIL0_PMM1PCIHA
);
204 PCI_WRITEL(0, BAMBOO_PCIL0_PMM1MA
);
206 /* Disable region two */
207 PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA
);
208 PCI_WRITEL(0, BAMBOO_PCIL0_PMM2LA
);
209 PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCILA
);
210 PCI_WRITEL(0, BAMBOO_PCIL0_PMM2PCIHA
);
211 PCI_WRITEL(0, BAMBOO_PCIL0_PMM2MA
);
213 /* Now configure the PCI->PLB windows, we only use PTM1
215 * For Inbound flow, set the window size to all available memory
216 * This is required because if size is smaller,
217 * then Eth/PCI DD would fail as PCI card not able to access
218 * the memory allocated by DD.
221 PCI_WRITEL(0, BAMBOO_PCIL0_PTM1MS
); /* disabled region 1 */
222 PCI_WRITEL(0, BAMBOO_PCIL0_PTM1LA
); /* begin of address map */
224 memory_size
= 1 << fls(memory_size
- 1);
226 /* Size low + Enabled */
227 PCI_WRITEL((0xffffffff - (memory_size
- 1)) | 0x1, BAMBOO_PCIL0_PTM1MS
);
230 iounmap(pci_reg_base
);
234 bamboo_setup_hose(void)
236 unsigned int bar_response
, bar
;
237 struct pci_controller
*hose
;
241 hose
= pcibios_alloc_controller();
246 hose
->first_busno
= 0;
247 hose
->last_busno
= 0xff;
249 hose
->pci_mem_offset
= BAMBOO_PCI_MEM_OFFSET
;
251 pci_init_resource(&hose
->io_resource
,
257 pci_init_resource(&hose
->mem_resources
[0],
258 BAMBOO_PCI_LOWER_MEM
,
259 BAMBOO_PCI_UPPER_MEM
,
263 ppc_md
.pci_exclude_device
= bamboo_exclude_device
;
265 hose
->io_space
.start
= BAMBOO_PCI_LOWER_IO
;
266 hose
->io_space
.end
= BAMBOO_PCI_UPPER_IO
;
267 hose
->mem_space
.start
= BAMBOO_PCI_LOWER_MEM
;
268 hose
->mem_space
.end
= BAMBOO_PCI_UPPER_MEM
;
270 (unsigned long)ioremap64(BAMBOO_PCI_IO_BASE
, BAMBOO_PCI_IO_SIZE
);
271 hose
->io_base_virt
= (void *)isa_io_base
;
273 setup_indirect_pci(hose
,
274 BAMBOO_PCI_CFGA_PLB32
,
275 BAMBOO_PCI_CFGD_PLB32
);
276 hose
->set_cfg_type
= 1;
278 /* Zero config bars */
279 for (bar
= PCI_BASE_ADDRESS_1
; bar
<= PCI_BASE_ADDRESS_2
; bar
+= 4) {
280 early_write_config_dword(hose
, hose
->first_busno
,
281 PCI_FUNC(hose
->first_busno
), bar
,
283 early_read_config_dword(hose
, hose
->first_busno
,
284 PCI_FUNC(hose
->first_busno
), bar
,
288 hose
->last_busno
= pciauto_bus_scan(hose
, hose
->first_busno
);
290 ppc_md
.pci_swizzle
= common_swizzle
;
291 ppc_md
.pci_map_irq
= bamboo_map_irq
;
297 bamboo_early_serial_map(void)
299 struct uart_port port
;
301 /* Setup ioremapped serial port access */
302 memset(&port
, 0, sizeof(port
));
303 port
.membase
= ioremap64(PPC440EP_UART0_ADDR
, 8);
305 port
.uartclk
= clocks
.uart0
;
307 port
.iotype
= SERIAL_IO_MEM
;
308 port
.flags
= ASYNC_BOOT_AUTOCONF
| ASYNC_SKIP_TEST
;
311 if (early_serial_setup(&port
) != 0) {
312 printk("Early serial init of port 0 failed\n");
315 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
316 /* Configure debug serial access */
317 gen550_init(0, &port
);
320 port
.membase
= ioremap64(PPC440EP_UART1_ADDR
, 8);
322 port
.uartclk
= clocks
.uart1
;
325 if (early_serial_setup(&port
) != 0) {
326 printk("Early serial init of port 1 failed\n");
329 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
330 /* Configure debug serial access */
331 gen550_init(1, &port
);
334 port
.membase
= ioremap64(PPC440EP_UART2_ADDR
, 8);
336 port
.uartclk
= clocks
.uart2
;
339 if (early_serial_setup(&port
) != 0) {
340 printk("Early serial init of port 2 failed\n");
343 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
344 /* Configure debug serial access */
345 gen550_init(2, &port
);
348 port
.membase
= ioremap64(PPC440EP_UART3_ADDR
, 8);
350 port
.uartclk
= clocks
.uart3
;
353 if (early_serial_setup(&port
) != 0) {
354 printk("Early serial init of port 3 failed\n");
359 bamboo_setup_arch(void)
362 bamboo_set_emacdata();
364 ibm440gx_get_clocks(&clocks
, 33333333, 6 * 1843200);
365 ocp_sys_info
.opb_bus_freq
= clocks
.opb
;
367 /* Setup TODC access */
368 TODC_INIT(TODC_TYPE_DS1743
,
371 ioremap64(BAMBOO_RTC_ADDR
, BAMBOO_RTC_SIZE
),
374 /* init to some ~sane value until calibrate_delay() runs */
375 loops_per_jiffy
= 50000000/HZ
;
377 /* Setup PCI host bridge */
380 #ifdef CONFIG_BLK_DEV_INITRD
382 ROOT_DEV
= Root_RAM0
;
385 #ifdef CONFIG_ROOT_NFS
388 ROOT_DEV
= Root_HDA1
;
391 bamboo_early_serial_map();
393 /* Identify the system */
394 printk("IBM Bamboo port (MontaVista Software, Inc. (source@mvista.com))\n");
397 void __init
platform_init(unsigned long r3
, unsigned long r4
,
398 unsigned long r5
, unsigned long r6
, unsigned long r7
)
400 parse_bootinfo(find_bootinfo());
403 * If we were passed in a board information, copy it into the
404 * residual data area.
407 __res
= *(bd_t
*)(r3
+ KERNELBASE
);
410 ibm44x_platform_init();
412 ppc_md
.setup_arch
= bamboo_setup_arch
;
413 ppc_md
.show_cpuinfo
= bamboo_show_cpuinfo
;
414 ppc_md
.get_irq
= NULL
; /* Set in ppc4xx_pic_init() */
416 ppc_md
.calibrate_decr
= bamboo_calibrate_decr
;
417 ppc_md
.time_init
= todc_time_init
;
418 ppc_md
.set_rtc_time
= todc_set_rtc_time
;
419 ppc_md
.get_rtc_time
= todc_get_rtc_time
;
421 ppc_md
.nvram_read_val
= todc_direct_read_val
;
422 ppc_md
.nvram_write_val
= todc_direct_write_val
;
424 ppc_md
.early_serial_map
= bamboo_early_serial_map
;