arch/ppc/platforms/4xx/ppc440spe.h

   1 /*
   2  * arch/ppc/platforms/4xx/ibm440spe.h
   3  *
   4  * PPC440SPe definitions
   5  *
   6  * Roland Dreier <rolandd@cisco.com>
   7  * Copyright (c) 2005 Cisco Systems.  All rights reserved.
   8  *
   9  * Matt Porter <mporter@kernel.crashing.org>
  10  * Copyright 2004-2005 MontaVista Software, Inc.
  11  *
  12  * This program is free software; you can redistribute  it and/or modify it
  13  * under  the terms of  the GNU General  Public License as published by the
  14  * Free Software Foundation;  either version 2 of the  License, or (at your
  15  * option) any later version.
  16  */
  17
  18 #ifdef __KERNEL__
  19 #ifndef __PPC_PLATFORMS_PPC440SPE_H
  20 #define __PPC_PLATFORMS_PPC440SPE_H
  21
  22 #include <linux/config.h>
  23
  24 #include <asm/ibm44x.h>
  25
  26 /* UART */
  27 #define PPC440SPE_UART0_ADDR    0x00000004f0000200ULL
  28 #define PPC440SPE_UART1_ADDR    0x00000004f0000300ULL
  29 #define PPC440SPE_UART2_ADDR    0x00000004f0000600ULL
  30 #define UART0_INT               0
  31 #define UART1_INT               1
  32 #define UART2_INT               37
  33
  34 /* Clock and Power Management */
  35 #define IBM_CPM_IIC0            0x80000000      /* IIC interface */
  36 #define IBM_CPM_IIC1            0x40000000      /* IIC interface */
  37 #define IBM_CPM_PCI             0x20000000      /* PCI bridge */
  38 #define IBM_CPM_CPU                 0x02000000  /* processor core */
  39 #define IBM_CPM_DMA                 0x01000000  /* DMA controller */
  40 #define IBM_CPM_BGO                 0x00800000  /* PLB to OPB bus arbiter */
  41 #define IBM_CPM_BGI                 0x00400000  /* OPB to PLB bridge */
  42 #define IBM_CPM_EBC                 0x00200000  /* External Bux Controller */
  43 #define IBM_CPM_EBM                 0x00100000  /* Ext Bus Master Interface */
  44 #define IBM_CPM_DMC                 0x00080000  /* SDRAM peripheral controller */
  45 #define IBM_CPM_PLB                 0x00040000  /* PLB bus arbiter */
  46 #define IBM_CPM_SRAM            0x00020000      /* SRAM memory controller */
  47 #define IBM_CPM_PPM                 0x00002000  /* PLB Performance Monitor */
  48 #define IBM_CPM_UIC1            0x00001000      /* Universal Interrupt Controller */
  49 #define IBM_CPM_GPIO0           0x00000800      /* General Purpose IO (??) */
  50 #define IBM_CPM_GPT                 0x00000400  /* General Purpose Timers  */
  51 #define IBM_CPM_UART0           0x00000200      /* serial port 0 */
  52 #define IBM_CPM_UART1           0x00000100      /* serial port 1 */
  53 #define IBM_CPM_UART2           0x00000100      /* serial port 1 */
  54 #define IBM_CPM_UIC0            0x00000080      /* Universal Interrupt Controller */
  55 #define IBM_CPM_TMRCLK          0x00000040      /* CPU timers */
  56 #define IBM_CPM_EMAC0           0x00000020      /* EMAC 0     */
  57
  58 #define DFLT_IBM4xx_PM          ~(IBM_CPM_UIC | IBM_CPM_UIC1 | IBM_CPM_CPU \
  59                                 | IBM_CPM_EBC | IBM_CPM_SRAM | IBM_CPM_BGO \
  60                                 | IBM_CPM_EBM | IBM_CPM_PLB | IBM_CPM_OPB \
  61                                 | IBM_CPM_TMRCLK | IBM_CPM_DMA | IBM_CPM_PCI \
  62                                 | IBM_CPM_TAHOE0 | IBM_CPM_TAHOE1 \
  63                                 | IBM_CPM_EMAC0 | IBM_CPM_EMAC1 \
  64                                 | IBM_CPM_EMAC2 | IBM_CPM_EMAC3 )
  65 #endif /* __PPC_PLATFORMS_PPC440SP_H */
  66 #endif /* __KERNEL__ */