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[PATCH] powerpc: CPM2 interrupt handler failure after 100,000 interrupts
[mirror_ubuntu-kernels.git] / arch / ppc / platforms / 85xx / mpc85xx_cds_common.c
1 /*
2 * arch/ppc/platform/85xx/mpc85xx_cds_common.c
3 *
4 * MPC85xx CDS board specific routines
5 *
6 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
7 *
8 * Copyright 2004 Freescale Semiconductor, Inc
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
14 */
15
16 #include <linux/config.h>
17 #include <linux/stddef.h>
18 #include <linux/kernel.h>
19 #include <linux/init.h>
20 #include <linux/errno.h>
21 #include <linux/reboot.h>
22 #include <linux/pci.h>
23 #include <linux/kdev_t.h>
24 #include <linux/major.h>
25 #include <linux/console.h>
26 #include <linux/delay.h>
27 #include <linux/seq_file.h>
28 #include <linux/serial.h>
29 #include <linux/module.h>
30 #include <linux/root_dev.h>
31 #include <linux/initrd.h>
32 #include <linux/tty.h>
33 #include <linux/serial_core.h>
34 #include <linux/fsl_devices.h>
35
36 #include <asm/system.h>
37 #include <asm/pgtable.h>
38 #include <asm/page.h>
39 #include <asm/atomic.h>
40 #include <asm/time.h>
41 #include <asm/todc.h>
42 #include <asm/io.h>
43 #include <asm/machdep.h>
44 #include <asm/open_pic.h>
45 #include <asm/i8259.h>
46 #include <asm/bootinfo.h>
47 #include <asm/pci-bridge.h>
48 #include <asm/mpc85xx.h>
49 #include <asm/irq.h>
50 #include <asm/immap_85xx.h>
51 #include <asm/cpm2.h>
52 #include <asm/ppc_sys.h>
53 #include <asm/kgdb.h>
54
55 #include <mm/mmu_decl.h>
56 #include <syslib/cpm2_pic.h>
57 #include <syslib/ppc85xx_common.h>
58 #include <syslib/ppc85xx_setup.h>
59
60
61 #ifndef CONFIG_PCI
62 unsigned long isa_io_base = 0;
63 unsigned long isa_mem_base = 0;
64 #endif
65
66 extern unsigned long total_memory; /* in mm/init */
67
68 unsigned char __res[sizeof (bd_t)];
69
70 static int cds_pci_slot = 2;
71 static volatile u8 * cadmus;
72
73 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
74 static u_char mpc85xx_cds_openpic_initsenses[] __initdata = {
75 MPC85XX_INTERNAL_IRQ_SENSES,
76 #if defined(CONFIG_PCI)
77 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 0: PCI1 slot */
78 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 1: PCI1 slot */
79 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 2: PCI1 slot */
80 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 3: PCI1 slot */
81 #else
82 0x0, /* External 0: */
83 0x0, /* External 1: */
84 0x0, /* External 2: */
85 0x0, /* External 3: */
86 #endif
87 0x0, /* External 4: */
88 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 5: PHY */
89 0x0, /* External 6: */
90 0x0, /* External 7: */
91 0x0, /* External 8: */
92 0x0, /* External 9: */
93 0x0, /* External 10: */
94 #if defined(CONFIG_85xx_PCI2) && defined(CONFIG_PCI)
95 (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* External 11: PCI2 slot 0 */
96 #else
97 0x0, /* External 11: */
98 #endif
99 };
100
101 /* ************************************************************************ */
102 int
103 mpc85xx_cds_show_cpuinfo(struct seq_file *m)
104 {
105 uint pvid, svid, phid1;
106 uint memsize = total_memory;
107 bd_t *binfo = (bd_t *) __res;
108 unsigned int freq;
109
110 /* get the core frequency */
111 freq = binfo->bi_intfreq;
112
113 pvid = mfspr(SPRN_PVR);
114 svid = mfspr(SPRN_SVR);
115
116 seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
117 seq_printf(m, "Machine\t\t: CDS - MPC%s (%x)\n", cur_ppc_sys_spec->ppc_sys_name, cadmus[CM_VER]);
118 seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
119 seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
120 seq_printf(m, "SVR\t\t: 0x%x\n", svid);
121
122 /* Display cpu Pll setting */
123 phid1 = mfspr(SPRN_HID1);
124 seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
125
126 /* Display the amount of memory */
127 seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
128
129 return 0;
130 }
131
132 #ifdef CONFIG_CPM2
133 static irqreturn_t cpm2_cascade(int irq, void *dev_id, struct pt_regs *regs)
134 {
135 while((irq = cpm2_get_irq(regs)) >= 0)
136 __do_IRQ(irq, regs);
137 return IRQ_HANDLED;
138 }
139
140 static struct irqaction cpm2_irqaction = {
141 .handler = cpm2_cascade,
142 .flags = SA_INTERRUPT,
143 .mask = CPU_MASK_NONE,
144 .name = "cpm2_cascade",
145 };
146 #endif /* CONFIG_CPM2 */
147
148 void __init
149 mpc85xx_cds_init_IRQ(void)
150 {
151 bd_t *binfo = (bd_t *) __res;
152 int i;
153
154 /* Determine the Physical Address of the OpenPIC regs */
155 phys_addr_t OpenPIC_PAddr = binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
156 OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
157 OpenPIC_InitSenses = mpc85xx_cds_openpic_initsenses;
158 OpenPIC_NumInitSenses = sizeof (mpc85xx_cds_openpic_initsenses);
159
160 /* Skip reserved space and internal sources */
161 #ifdef CONFIG_MPC8548
162 openpic_set_sources(0, 48, OpenPIC_Addr + 0x10200);
163 #else
164 openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
165 #endif
166 /* Map PIC IRQs 0-11 */
167 openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
168
169 /* we let openpic interrupts starting from an offset, to
170 * leave space for cascading interrupts underneath.
171 */
172 openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
173
174 #ifdef CONFIG_PCI
175 openpic_hookup_cascade(PIRQ0A, "82c59 cascade", i8259_irq);
176
177 i8259_init(0, 0);
178 #endif
179
180 #ifdef CONFIG_CPM2
181 /* Setup CPM2 PIC */
182 cpm2_init_IRQ();
183
184 setup_irq(MPC85xx_IRQ_CPM, &cpm2_irqaction);
185 #endif
186
187 return;
188 }
189
190 #ifdef CONFIG_PCI
191 /*
192 * interrupt routing
193 */
194 int
195 mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
196 {
197 struct pci_controller *hose = pci_bus_to_hose(dev->bus->number);
198
199 if (!hose->index)
200 {
201 /* Handle PCI1 interrupts */
202 char pci_irq_table[][4] =
203 /*
204 * PCI IDSEL/INTPIN->INTLINE
205 * A B C D
206 */
207
208 /* Note IRQ assignment for slots is based on which slot the elysium is
209 * in -- in this setup elysium is in slot #2 (this PIRQA as first
210 * interrupt on slot */
211 {
212 { 0, 1, 2, 3 }, /* 16 - PMC */
213 { 0, 1, 2, 3 }, /* 17 P2P (Tsi320) */
214 { 0, 1, 2, 3 }, /* 18 - Slot 1 */
215 { 1, 2, 3, 0 }, /* 19 - Slot 2 */
216 { 2, 3, 0, 1 }, /* 20 - Slot 3 */
217 { 3, 0, 1, 2 }, /* 21 - Slot 4 */
218 };
219
220 const long min_idsel = 16, max_idsel = 21, irqs_per_slot = 4;
221 int i, j;
222
223 for (i = 0; i < 6; i++)
224 for (j = 0; j < 4; j++)
225 pci_irq_table[i][j] =
226 ((pci_irq_table[i][j] + 5 -
227 cds_pci_slot) & 0x3) + PIRQ0A;
228
229 return PCI_IRQ_TABLE_LOOKUP;
230 } else {
231 /* Handle PCI2 interrupts (if we have one) */
232 char pci_irq_table[][4] =
233 {
234 /*
235 * We only have one slot and one interrupt
236 * going to PIRQA - PIRQD */
237 { PIRQ1A, PIRQ1A, PIRQ1A, PIRQ1A }, /* 21 - slot 0 */
238 };
239
240 const long min_idsel = 21, max_idsel = 21, irqs_per_slot = 4;
241
242 return PCI_IRQ_TABLE_LOOKUP;
243 }
244 }
245
246 #define ARCADIA_HOST_BRIDGE_IDSEL 17
247 #define ARCADIA_2ND_BRIDGE_IDSEL 3
248
249 extern int mpc85xx_pci1_last_busno;
250
251 int
252 mpc85xx_exclude_device(u_char bus, u_char devfn)
253 {
254 if (bus == 0 && PCI_SLOT(devfn) == 0)
255 return PCIBIOS_DEVICE_NOT_FOUND;
256 #ifdef CONFIG_85xx_PCI2
257 if (mpc85xx_pci1_last_busno)
258 if (bus == (mpc85xx_pci1_last_busno + 1) && PCI_SLOT(devfn) == 0)
259 return PCIBIOS_DEVICE_NOT_FOUND;
260 #endif
261 /* We explicitly do not go past the Tundra 320 Bridge */
262 if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
263 return PCIBIOS_DEVICE_NOT_FOUND;
264 if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
265 return PCIBIOS_DEVICE_NOT_FOUND;
266 else
267 return PCIBIOS_SUCCESSFUL;
268 }
269
270 void __init
271 mpc85xx_cds_enable_via(struct pci_controller *hose)
272 {
273 u32 pci_class;
274 u16 vid, did;
275
276 early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class);
277 if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI)
278 return;
279
280 /* Configure P2P so that we can reach bus 1 */
281 early_write_config_byte(hose, 0, 0x88, PCI_PRIMARY_BUS, 0);
282 early_write_config_byte(hose, 0, 0x88, PCI_SECONDARY_BUS, 1);
283 early_write_config_byte(hose, 0, 0x88, PCI_SUBORDINATE_BUS, 0xff);
284
285 early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid);
286 early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did);
287
288 if ((vid != PCI_VENDOR_ID_VIA) ||
289 (did != PCI_DEVICE_ID_VIA_82C686))
290 return;
291
292 /* Enable USB and IDE functions */
293 early_write_config_byte(hose, 1, 0x10, 0x48, 0x08);
294 }
295
296 void __init
297 mpc85xx_cds_fixup_via(struct pci_controller *hose)
298 {
299 u32 pci_class;
300 u16 vid, did;
301
302 early_read_config_dword(hose, 0, 0x88, PCI_CLASS_REVISION, &pci_class);
303 if ((pci_class >> 16) != PCI_CLASS_BRIDGE_PCI)
304 return;
305
306 /*
307 * Force the backplane P2P bridge to have a window
308 * open from 0x00000000-0x00001fff in PCI I/O space.
309 * This allows legacy I/O (i8259, etc) on the VIA
310 * southbridge to be accessed.
311 */
312 early_write_config_byte(hose, 0, 0x88, PCI_IO_BASE, 0x00);
313 early_write_config_word(hose, 0, 0x88, PCI_IO_BASE_UPPER16, 0x0000);
314 early_write_config_byte(hose, 0, 0x88, PCI_IO_LIMIT, 0x10);
315 early_write_config_word(hose, 0, 0x88, PCI_IO_LIMIT_UPPER16, 0x0000);
316
317 early_read_config_word(hose, 1, 0x10, PCI_VENDOR_ID, &vid);
318 early_read_config_word(hose, 1, 0x10, PCI_DEVICE_ID, &did);
319 if ((vid != PCI_VENDOR_ID_VIA) ||
320 (did != PCI_DEVICE_ID_VIA_82C686))
321 return;
322
323 /*
324 * Since the P2P window was forced to cover the fixed
325 * legacy I/O addresses, it is necessary to manually
326 * place the base addresses for the IDE and USB functions
327 * within this window.
328 */
329 /* Function 1, IDE */
330 early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_0, 0x1ff8);
331 early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_1, 0x1ff4);
332 early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_2, 0x1fe8);
333 early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_3, 0x1fe4);
334 early_write_config_dword(hose, 1, 0x11, PCI_BASE_ADDRESS_4, 0x1fd0);
335
336 /* Function 2, USB ports 0-1 */
337 early_write_config_dword(hose, 1, 0x12, PCI_BASE_ADDRESS_4, 0x1fa0);
338
339 /* Function 3, USB ports 2-3 */
340 early_write_config_dword(hose, 1, 0x13, PCI_BASE_ADDRESS_4, 0x1f80);
341
342 /* Function 5, Power Management */
343 early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_0, 0x1e00);
344 early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_1, 0x1dfc);
345 early_write_config_dword(hose, 1, 0x15, PCI_BASE_ADDRESS_2, 0x1df8);
346
347 /* Function 6, AC97 Interface */
348 early_write_config_dword(hose, 1, 0x16, PCI_BASE_ADDRESS_0, 0x1c00);
349 }
350
351 void __init
352 mpc85xx_cds_pcibios_fixup(void)
353 {
354 struct pci_dev *dev = NULL;
355 u_char c;
356
357 if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
358 PCI_DEVICE_ID_VIA_82C586_1, NULL))) {
359 /*
360 * U-Boot does not set the enable bits
361 * for the IDE device. Force them on here.
362 */
363 pci_read_config_byte(dev, 0x40, &c);
364 c |= 0x03; /* IDE: Chip Enable Bits */
365 pci_write_config_byte(dev, 0x40, c);
366
367 /*
368 * Since only primary interface works, force the
369 * IDE function to standard primary IDE interrupt
370 * w/ 8259 offset
371 */
372 dev->irq = 14;
373 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
374 }
375
376 /*
377 * Force legacy USB interrupt routing
378 */
379 if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
380 PCI_DEVICE_ID_VIA_82C586_2, NULL))) {
381 dev->irq = 10;
382 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 10);
383 }
384
385 if ((dev = pci_find_device(PCI_VENDOR_ID_VIA,
386 PCI_DEVICE_ID_VIA_82C586_2, dev))) {
387 dev->irq = 11;
388 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, 11);
389 }
390 }
391 #endif /* CONFIG_PCI */
392
393 TODC_ALLOC();
394
395 static const char *GFAR_PHY_0 = "phy0:0";
396 static const char *GFAR_PHY_1 = "phy0:1";
397
398 /* ************************************************************************
399 *
400 * Setup the architecture
401 *
402 */
403 static void __init
404 mpc85xx_cds_setup_arch(void)
405 {
406 bd_t *binfo = (bd_t *) __res;
407 unsigned int freq;
408 struct gianfar_platform_data *pdata;
409 struct gianfar_mdio_data *mdata;
410
411 /* get the core frequency */
412 freq = binfo->bi_intfreq;
413
414 printk("mpc85xx_cds_setup_arch\n");
415
416 #ifdef CONFIG_CPM2
417 cpm2_reset();
418 #endif
419
420 cadmus = ioremap(CADMUS_BASE, CADMUS_SIZE);
421 cds_pci_slot = ((cadmus[CM_CSR] >> 6) & 0x3) + 1;
422 printk("CDS Version = %x in PCI slot %d\n", cadmus[CM_VER], cds_pci_slot);
423
424 /* Setup TODC access */
425 TODC_INIT(TODC_TYPE_DS1743,
426 0,
427 0,
428 ioremap(CDS_RTC_ADDR, CDS_RTC_SIZE),
429 8);
430
431 /* Set loops_per_jiffy to a half-way reasonable value,
432 for use until calibrate_delay gets called. */
433 loops_per_jiffy = freq / HZ;
434
435 #ifdef CONFIG_PCI
436 /* VIA IDE configuration */
437 ppc_md.pcibios_fixup = mpc85xx_cds_pcibios_fixup;
438
439 /* setup PCI host bridges */
440 mpc85xx_setup_hose();
441 #endif
442
443 #ifdef CONFIG_SERIAL_8250
444 mpc85xx_early_serial_map();
445 #endif
446
447 #ifdef CONFIG_SERIAL_TEXT_DEBUG
448 /* Invalidate the entry we stole earlier the serial ports
449 * should be properly mapped */
450 invalidate_tlbcam_entry(num_tlbcam_entries - 1);
451 #endif
452
453 /* setup the board related info for the MDIO bus */
454 mdata = (struct gianfar_mdio_data *) ppc_sys_get_pdata(MPC85xx_MDIO);
455
456 mdata->irq[0] = MPC85xx_IRQ_EXT5;
457 mdata->irq[1] = MPC85xx_IRQ_EXT5;
458 mdata->irq[2] = -1;
459 mdata->irq[3] = -1;
460 mdata->irq[31] = -1;
461 mdata->paddr += binfo->bi_immr_base;
462
463 /* setup the board related information for the enet controllers */
464 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC1);
465 if (pdata) {
466 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
467 pdata->bus_id = GFAR_PHY_0;
468 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
469 }
470
471 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_TSEC2);
472 if (pdata) {
473 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
474 pdata->bus_id = GFAR_PHY_1;
475 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
476 }
477
478 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC1);
479 if (pdata) {
480 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
481 pdata->bus_id = GFAR_PHY_0;
482 memcpy(pdata->mac_addr, binfo->bi_enetaddr, 6);
483 }
484
485 pdata = (struct gianfar_platform_data *) ppc_sys_get_pdata(MPC85xx_eTSEC2);
486 if (pdata) {
487 pdata->board_flags = FSL_GIANFAR_BRD_HAS_PHY_INTR;
488 pdata->bus_id = GFAR_PHY_1;
489 memcpy(pdata->mac_addr, binfo->bi_enet1addr, 6);
490 }
491
492 ppc_sys_device_remove(MPC85xx_eTSEC3);
493 ppc_sys_device_remove(MPC85xx_eTSEC4);
494
495 #ifdef CONFIG_BLK_DEV_INITRD
496 if (initrd_start)
497 ROOT_DEV = Root_RAM0;
498 else
499 #endif
500 #ifdef CONFIG_ROOT_NFS
501 ROOT_DEV = Root_NFS;
502 #else
503 ROOT_DEV = Root_HDA1;
504 #endif
505 }
506
507 /* ************************************************************************ */
508 void __init
509 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
510 unsigned long r6, unsigned long r7)
511 {
512 /* parse_bootinfo must always be called first */
513 parse_bootinfo(find_bootinfo());
514
515 /*
516 * If we were passed in a board information, copy it into the
517 * residual data area.
518 */
519 if (r3) {
520 memcpy((void *) __res, (void *) (r3 + KERNELBASE),
521 sizeof (bd_t));
522
523 }
524 #ifdef CONFIG_SERIAL_TEXT_DEBUG
525 {
526 bd_t *binfo = (bd_t *) __res;
527 struct uart_port p;
528
529 /* Use the last TLB entry to map CCSRBAR to allow access to DUART regs */
530 settlbcam(num_tlbcam_entries - 1, binfo->bi_immr_base,
531 binfo->bi_immr_base, MPC85xx_CCSRBAR_SIZE, _PAGE_IO, 0);
532
533 memset(&p, 0, sizeof (p));
534 p.iotype = SERIAL_IO_MEM;
535 p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART0_OFFSET;
536 p.uartclk = binfo->bi_busfreq;
537
538 gen550_init(0, &p);
539
540 memset(&p, 0, sizeof (p));
541 p.iotype = SERIAL_IO_MEM;
542 p.membase = (void *) binfo->bi_immr_base + MPC85xx_UART1_OFFSET;
543 p.uartclk = binfo->bi_busfreq;
544
545 gen550_init(1, &p);
546 }
547 #endif
548
549 #if defined(CONFIG_BLK_DEV_INITRD)
550 /*
551 * If the init RAM disk has been configured in, and there's a valid
552 * starting address for it, set it up.
553 */
554 if (r4) {
555 initrd_start = r4 + KERNELBASE;
556 initrd_end = r5 + KERNELBASE;
557 }
558 #endif /* CONFIG_BLK_DEV_INITRD */
559
560 /* Copy the kernel command line arguments to a safe place. */
561
562 if (r6) {
563 *(char *) (r7 + KERNELBASE) = 0;
564 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
565 }
566
567 identify_ppc_sys_by_id(mfspr(SPRN_SVR));
568
569 /* setup the PowerPC module struct */
570 ppc_md.setup_arch = mpc85xx_cds_setup_arch;
571 ppc_md.show_cpuinfo = mpc85xx_cds_show_cpuinfo;
572
573 ppc_md.init_IRQ = mpc85xx_cds_init_IRQ;
574 ppc_md.get_irq = openpic_get_irq;
575
576 ppc_md.restart = mpc85xx_restart;
577 ppc_md.power_off = mpc85xx_power_off;
578 ppc_md.halt = mpc85xx_halt;
579
580 ppc_md.find_end_of_memory = mpc85xx_find_end_of_memory;
581
582 ppc_md.calibrate_decr = mpc85xx_calibrate_decr;
583
584 ppc_md.time_init = todc_time_init;
585 ppc_md.set_rtc_time = todc_set_rtc_time;
586 ppc_md.get_rtc_time = todc_get_rtc_time;
587
588 ppc_md.nvram_read_val = todc_direct_read_val;
589 ppc_md.nvram_write_val = todc_direct_write_val;
590
591 #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_SERIAL_TEXT_DEBUG)
592 ppc_md.progress = gen550_progress;
593 #endif /* CONFIG_SERIAL_8250 && CONFIG_SERIAL_TEXT_DEBUG */
594 #if defined(CONFIG_SERIAL_8250) && defined(CONFIG_KGDB)
595 ppc_md.early_serial_map = mpc85xx_early_serial_map;
596 #endif /* CONFIG_SERIAL_8250 && CONFIG_KGDB */
597
598 if (ppc_md.progress)
599 ppc_md.progress("mpc85xx_cds_init(): exit", 0);
600
601 return;
602 }
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