arch/ppc/platforms/chestnut.c

   1 /*
   2  * arch/ppc/platforms/chestnut.c
   3  *
   4  * Board setup routines for IBM Chestnut
   5  *
   6  * Author: <source@mvista.com>
   7  *
   8  * <2004> (c) MontaVista Software, Inc. This file is licensed under
   9  * the terms of the GNU General Public License version 2. This program
  10  * is licensed "as is" without any warranty of any kind, whether express
  11  * or implied.
  12  */
  13
  14 #include <linux/config.h>
  15 #include <linux/stddef.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/errno.h>
  19 #include <linux/reboot.h>
  20 #include <linux/kdev_t.h>
  21 #include <linux/major.h>
  22 #include <linux/blkdev.h>
  23 #include <linux/console.h>
  24 #include <linux/root_dev.h>
  25 #include <linux/initrd.h>
  26 #include <linux/delay.h>
  27 #include <linux/seq_file.h>
  28 #include <linux/ide.h>
  29 #include <linux/serial.h>
  30 #include <linux/serial_core.h>
  31 #include <linux/mtd/physmap.h>
  32 #include <asm/system.h>
  33 #include <asm/pgtable.h>
  34 #include <asm/page.h>
  35 #include <asm/time.h>
  36 #include <asm/dma.h>
  37 #include <asm/io.h>
  38 #include <linux/irq.h>
  39 #include <asm/hw_irq.h>
  40 #include <asm/machdep.h>
  41 #include <asm/kgdb.h>
  42 #include <asm/bootinfo.h>
  43 #include <asm/mv64x60.h>
  44 #include <platforms/chestnut.h>
  45
  46 static void __iomem *sram_base; /* Virtual addr of Internal SRAM */
  47 static void __iomem *cpld_base; /* Virtual addr of CPLD Regs */
  48
  49 static mv64x60_handle_t bh;
  50
  51 extern void gen550_progress(char *, unsigned short);
  52 extern void gen550_init(int, struct uart_port *);
  53 extern void mv64360_pcibios_fixup(mv64x60_handle_t *bh);
  54
  55 #define BIT(x) (1<<x)
  56 #define CHESTNUT_PRESERVE_MASK (BIT(MV64x60_CPU2DEV_0_WIN) | \
  57                                 BIT(MV64x60_CPU2DEV_1_WIN) | \
  58                                 BIT(MV64x60_CPU2DEV_2_WIN) | \
  59                                 BIT(MV64x60_CPU2DEV_3_WIN) | \
  60                                 BIT(MV64x60_CPU2BOOT_WIN))
  61 /**************************************************************************
  62  * FUNCTION: chestnut_calibrate_decr
  63  *
  64  * DESCRIPTION: initialize decrementer interrupt frequency (used as system
  65  *              timer)
  66  *
  67  ****/
  68 static void __init
  69 chestnut_calibrate_decr(void)
  70 {
  71         ulong freq;
  72
  73         freq = CHESTNUT_BUS_SPEED / 4;
  74
  75         printk("time_init: decrementer frequency = %lu.%.6lu MHz\n",
  76                 freq/1000000, freq%1000000);
  77
  78         tb_ticks_per_jiffy = freq / HZ;
  79         tb_to_us = mulhwu_scale_factor(freq, 1000000);
  80 }
  81
  82 static int
  83 chestnut_show_cpuinfo(struct seq_file *m)
  84 {
  85         seq_printf(m, "vendor\t\t: IBM\n");
  86         seq_printf(m, "machine\t\t: 750FX/GX Eval Board (Chestnut/Buckeye)\n");
  87
  88         return 0;
  89 }
  90
  91 /**************************************************************************
  92  * FUNCTION: chestnut_find_end_of_memory
  93  *
  94  * DESCRIPTION: ppc_md memory size callback
  95  *
  96  ****/
  97 unsigned long __init
  98 chestnut_find_end_of_memory(void)
  99 {
 100         static int  mem_size = 0;
 101
 102         if (mem_size == 0) {
 103                 mem_size = mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE,
 104                                 MV64x60_TYPE_MV64460);
 105         }
 106         return mem_size;
 107 }
 108
 109 #if defined(CONFIG_SERIAL_8250)
 110 static void __init
 111 chestnut_early_serial_map(void)
 112 {
 113         struct uart_port port;
 114
 115         /* Setup serial port access */
 116         memset(&port, 0, sizeof(port));
 117         port.uartclk = BASE_BAUD * 16;
 118         port.irq = UART0_INT;
 119         port.flags = STD_COM_FLAGS | UPF_IOREMAP;
 120         port.iotype = SERIAL_IO_MEM;
 121         port.mapbase = CHESTNUT_UART0_IO_BASE;
 122         port.regshift = 0;
 123
 124         if (early_serial_setup(&port) != 0)
 125                 printk("Early serial init of port 0 failed\n");
 126
 127         /* Assume early_serial_setup() doesn't modify serial_req */
 128         port.line = 1;
 129         port.irq = UART1_INT;
 130         port.mapbase = CHESTNUT_UART1_IO_BASE;
 131
 132         if (early_serial_setup(&port) != 0)
 133                 printk("Early serial init of port 1 failed\n");
 134 }
 135 #endif
 136
 137 /**************************************************************************
 138  * FUNCTION: chestnut_map_irq
 139  *
 140  * DESCRIPTION: 0 return since PCI IRQs not needed
 141  *
 142  ****/
 143 static int __init
 144 chestnut_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 145 {
 146         static char pci_irq_table[][4] = {
 147                 {CHESTNUT_PCI_SLOT0_IRQ, CHESTNUT_PCI_SLOT0_IRQ,
 148                  CHESTNUT_PCI_SLOT0_IRQ, CHESTNUT_PCI_SLOT0_IRQ},
 149                 {CHESTNUT_PCI_SLOT1_IRQ, CHESTNUT_PCI_SLOT1_IRQ,
 150                  CHESTNUT_PCI_SLOT1_IRQ, CHESTNUT_PCI_SLOT1_IRQ},
 151                 {CHESTNUT_PCI_SLOT2_IRQ, CHESTNUT_PCI_SLOT2_IRQ,
 152                  CHESTNUT_PCI_SLOT2_IRQ, CHESTNUT_PCI_SLOT2_IRQ},
 153                 {CHESTNUT_PCI_SLOT3_IRQ, CHESTNUT_PCI_SLOT3_IRQ,
 154                  CHESTNUT_PCI_SLOT3_IRQ, CHESTNUT_PCI_SLOT3_IRQ},
 155         };
 156         const long min_idsel = 1, max_idsel = 4, irqs_per_slot = 4;
 157
 158         return PCI_IRQ_TABLE_LOOKUP;
 159 }
 160
 161
 162 /**************************************************************************
 163  * FUNCTION: chestnut_setup_bridge
 164  *
 165  * DESCRIPTION: initalize board-specific settings on the MV64360
 166  *
 167  ****/
 168 static void __init
 169 chestnut_setup_bridge(void)
 170 {
 171         struct mv64x60_setup_info       si;
 172         int i;
 173
 174         if ( ppc_md.progress )
 175                 ppc_md.progress("chestnut_setup_bridge: enter", 0);
 176
 177         memset(&si, 0, sizeof(si));
 178
 179         si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
 180
 181         /* setup only PCI bus 0 (bus 1 not used) */
 182         si.pci_0.enable_bus = 1;
 183         si.pci_0.pci_io.cpu_base = CHESTNUT_PCI0_IO_PROC_ADDR;
 184         si.pci_0.pci_io.pci_base_hi = 0;
 185         si.pci_0.pci_io.pci_base_lo = CHESTNUT_PCI0_IO_PCI_ADDR;
 186         si.pci_0.pci_io.size = CHESTNUT_PCI0_IO_SIZE;
 187         si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
 188         si.pci_0.pci_mem[0].cpu_base = CHESTNUT_PCI0_MEM_PROC_ADDR;
 189         si.pci_0.pci_mem[0].pci_base_hi = CHESTNUT_PCI0_MEM_PCI_HI_ADDR;
 190         si.pci_0.pci_mem[0].pci_base_lo = CHESTNUT_PCI0_MEM_PCI_LO_ADDR;
 191         si.pci_0.pci_mem[0].size = CHESTNUT_PCI0_MEM_SIZE;
 192         si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE; /* no swapping */
 193         si.pci_0.pci_cmd_bits = 0;
 194         si.pci_0.latency_timer = 0x80;
 195
 196         for (i=0; i<MV64x60_CPU2MEM_WINDOWS; i++) {
 197 #if defined(CONFIG_NOT_COHERENT_CACHE)
 198                 si.cpu_prot_options[i] = 0;
 199                 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
 200                 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
 201                 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
 202
 203                 si.pci_1.acc_cntl_options[i] =
 204                     MV64360_PCI_ACC_CNTL_SNOOP_NONE |
 205                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
 206                     MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
 207                     MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
 208 #else
 209                 si.cpu_prot_options[i] = 0;
 210                 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE; /* errata */
 211                 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE; /* errata */
 212                 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE; /* errata */
 213
 214                 si.pci_1.acc_cntl_options[i] =
 215                     MV64360_PCI_ACC_CNTL_SNOOP_WB |
 216                     MV64360_PCI_ACC_CNTL_SWAP_NONE |
 217                     MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
 218                     MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
 219 #endif
 220         }
 221
 222         /* Lookup host bridge - on CPU 0 - no SMP support */
 223         if (mv64x60_init(&bh, &si)) {
 224                 printk("\n\nPCI Bridge initialization failed!\n");
 225         }
 226
 227         pci_dram_offset = 0;
 228         ppc_md.pci_swizzle = common_swizzle;
 229         ppc_md.pci_map_irq = chestnut_map_irq;
 230         ppc_md.pci_exclude_device = mv64x60_pci_exclude_device;
 231
 232         mv64x60_set_bus(&bh, 0, 0);
 233         bh.hose_a->first_busno = 0;
 234         bh.hose_a->last_busno = 0xff;
 235         bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
 236 }
 237
 238 void __init
 239 chestnut_setup_peripherals(void)
 240 {
 241         mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
 242                         CHESTNUT_BOOT_8BIT_BASE, CHESTNUT_BOOT_8BIT_SIZE, 0);
 243         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
 244
 245         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_0_WIN,
 246                         CHESTNUT_32BIT_BASE, CHESTNUT_32BIT_SIZE, 0);
 247         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_0_WIN);
 248
 249         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_1_WIN,
 250                         CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE, 0);
 251         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_1_WIN);
 252         cpld_base = ioremap(CHESTNUT_CPLD_BASE, CHESTNUT_CPLD_SIZE);
 253
 254         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
 255                         CHESTNUT_UART_BASE, CHESTNUT_UART_SIZE, 0);
 256         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
 257
 258         mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
 259                         CHESTNUT_FRAM_BASE, CHESTNUT_FRAM_SIZE, 0);
 260         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
 261
 262         mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
 263                         CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE, 0);
 264         bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
 265
 266 #ifdef CONFIG_NOT_COHERENT_CACHE
 267         mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b0);
 268 #else
 269         mv64x60_write(&bh, MV64360_SRAM_CONFIG, 0x001600b2);
 270 #endif
 271         sram_base = ioremap(CHESTNUT_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE);
 272         memset(sram_base, 0, MV64360_SRAM_SIZE);
 273
 274         /*
 275          * Configure MPP pins for PCI DMA
 276          *
 277          * PCI Slot     GNT pin         REQ pin
 278          *      0       MPP16           MPP17
 279          *      1       MPP18           MPP19
 280          *      2       MPP20           MPP21
 281          *      3       MPP22           MPP23
 282          */
 283         mv64x60_write(&bh, MV64x60_MPP_CNTL_2,
 284                         (0x1 << 0)  |   /* MPPSel16 PCI0_GNT[0] */
 285                         (0x1 << 4)  |   /* MPPSel17 PCI0_REQ[0] */
 286                         (0x1 << 8)  |   /* MPPSel18 PCI0_GNT[1] */
 287                         (0x1 << 12) |   /* MPPSel19 PCI0_REQ[1] */
 288                         (0x1 << 16) |   /* MPPSel20 PCI0_GNT[2] */
 289                         (0x1 << 20) |   /* MPPSel21 PCI0_REQ[2] */
 290                         (0x1 << 24) |   /* MPPSel22 PCI0_GNT[3] */
 291                         (0x1 << 28));   /* MPPSel23 PCI0_REQ[3] */
 292         /*
 293          * Set unused MPP pins for output, as per schematic note
 294          *
 295          * Unused Pins: MPP01, MPP02, MPP04, MPP05, MPP06
 296          *              MPP09, MPP10, MPP13, MPP14, MPP15
 297          */
 298         mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_0,
 299                         (0xf << 4)  |   /* MPPSel01 GPIO[1] */
 300                         (0xf << 8)  |   /* MPPSel02 GPIO[2] */
 301                         (0xf << 16) |   /* MPPSel04 GPIO[4] */
 302                         (0xf << 20) |   /* MPPSel05 GPIO[5] */
 303                         (0xf << 24));   /* MPPSel06 GPIO[6] */
 304         mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_1,
 305                         (0xf << 4)  |   /* MPPSel09 GPIO[9] */
 306                         (0xf << 8)  |   /* MPPSel10 GPIO[10] */
 307                         (0xf << 20) |   /* MPPSel13 GPIO[13] */
 308                         (0xf << 24) |   /* MPPSel14 GPIO[14] */
 309                         (0xf << 28));   /* MPPSel15 GPIO[15] */
 310         mv64x60_set_bits(&bh, MV64x60_GPP_IO_CNTL, /* Output */
 311                         BIT(1)  | BIT(2)  | BIT(4)  | BIT(5)  | BIT(6)  |
 312                         BIT(9)  | BIT(10) | BIT(13) | BIT(14) | BIT(15));
 313
 314         /*
 315          * Configure the following MPP pins to indicate a level
 316          * triggered interrupt
 317          *
 318          * MPP24 - Board Reset (just map the MPP & GPP for chestnut_reset)
 319          * MPP25 - UART A  (high)
 320          * MPP26 - UART B  (high)
 321          * MPP28 - PCI Slot 3 (low)
 322          * MPP29 - PCI Slot 2 (low)
 323          * MPP30 - PCI Slot 1 (low)
 324          * MPP31 - PCI Slot 0 (low)
 325          */
 326         mv64x60_clr_bits(&bh, MV64x60_MPP_CNTL_3,
 327                         BIT(3) | BIT(2) | BIT(1) | BIT(0)        | /* MPP 24 */
 328                         BIT(7) | BIT(6) | BIT(5) | BIT(4)        | /* MPP 25 */
 329                         BIT(11) | BIT(10) | BIT(9) | BIT(8)      | /* MPP 26 */
 330                         BIT(19) | BIT(18) | BIT(17) | BIT(16)    | /* MPP 28 */
 331                         BIT(23) | BIT(22) | BIT(21) | BIT(20)    | /* MPP 29 */
 332                         BIT(27) | BIT(26) | BIT(25) | BIT(24)    | /* MPP 30 */
 333                         BIT(31) | BIT(30) | BIT(29) | BIT(28));    /* MPP 31 */
 334
 335         /*
 336          * Define GPP 25 (high), 26 (high), 28 (low), 29 (low), 30 (low),
 337          * 31 (low) interrupt polarity input signal and level triggered
 338          */
 339         mv64x60_clr_bits(&bh, MV64x60_GPP_LEVEL_CNTL, BIT(25) | BIT(26));
 340         mv64x60_set_bits(&bh, MV64x60_GPP_LEVEL_CNTL,
 341                         BIT(28) | BIT(29) | BIT(30) | BIT(31));
 342         mv64x60_clr_bits(&bh, MV64x60_GPP_IO_CNTL,
 343                         BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
 344                         BIT(31));
 345
 346         /* Config GPP interrupt controller to respond to level trigger */
 347         mv64x60_set_bits(&bh, MV64360_COMM_ARBITER_CNTL, BIT(10));
 348
 349         /*
 350          * Dismiss and then enable interrupt on GPP interrupt cause for CPU #0
 351          */
 352         mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE,
 353                         ~(BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
 354                           BIT(31)));
 355         mv64x60_set_bits(&bh, MV64x60_GPP_INTR_MASK,
 356                         BIT(25) | BIT(26) | BIT(28) | BIT(29) | BIT(30) |
 357                         BIT(31));
 358
 359         /*
 360          * Dismiss and then enable interrupt on CPU #0 high cause register
 361          * BIT27 summarizes GPP interrupts 24-31
 362          */
 363         mv64x60_set_bits(&bh, MV64360_IC_CPU0_INTR_MASK_HI, BIT(27));
 364
 365         if (ppc_md.progress)
 366                 ppc_md.progress("chestnut_setup_bridge: exit", 0);
 367 }
 368
 369 /**************************************************************************
 370  * FUNCTION: chestnut_setup_arch
 371  *
 372  * DESCRIPTION: ppc_md machine configuration callback
 373  *
 374  ****/
 375 static void __init
 376 chestnut_setup_arch(void)
 377 {
 378         if (ppc_md.progress)
 379                 ppc_md.progress("chestnut_setup_arch: enter", 0);
 380
 381         /* init to some ~sane value until calibrate_delay() runs */
 382         loops_per_jiffy = 50000000 / HZ;
 383
 384         /* if the time base value is greater than bus freq/4 (the TB and
 385         * decrementer tick rate) + signed integer rollover value, we
 386         * can spend a fair amount of time waiting for the rollover to
 387         * happen.  To get around this, initialize the time base register
 388         * to a "safe" value.
 389         */
 390         set_tb(0, 0);
 391
 392 #ifdef CONFIG_BLK_DEV_INITRD
 393         if (initrd_start)
 394                 ROOT_DEV = Root_RAM0;
 395         else
 396 #endif
 397 #ifdef CONFIG_ROOT_NFS
 398                 ROOT_DEV = Root_NFS;
 399 #else
 400                 ROOT_DEV = Root_SDA2;
 401 #endif
 402
 403         /*
 404         * Set up the L2CR register.
 405         */
 406         _set_L2CR(_get_L2CR() | L2CR_L2E);
 407
 408         chestnut_setup_bridge();
 409         chestnut_setup_peripherals();
 410
 411 #ifdef CONFIG_DUMMY_CONSOLE
 412         conswitchp = &dummy_con;
 413 #endif
 414
 415 #if defined(CONFIG_SERIAL_8250)
 416         chestnut_early_serial_map();
 417 #endif
 418
 419         /* Identify the system */
 420         printk(KERN_INFO "System Identification: IBM 750FX/GX Eval Board\n");
 421         printk(KERN_INFO "IBM 750FX/GX port (C) 2004 MontaVista Software, Inc."
 422                 " (source@mvista.com)\n");
 423
 424         if (ppc_md.progress)
 425                 ppc_md.progress("chestnut_setup_arch: exit", 0);
 426 }
 427
 428 #ifdef CONFIG_MTD_PHYSMAP
 429 static struct mtd_partition ptbl;
 430
 431 static int __init
 432 chestnut_setup_mtd(void)
 433 {
 434         memset(&ptbl, 0, sizeof(ptbl));
 435
 436         ptbl.name = "User FS";
 437         ptbl.size = CHESTNUT_32BIT_SIZE;
 438
 439         physmap_map.size = CHESTNUT_32BIT_SIZE;
 440         physmap_set_partitions(&ptbl, 1);
 441         return 0;
 442 }
 443
 444 arch_initcall(chestnut_setup_mtd);
 445 #endif
 446
 447 /**************************************************************************
 448  * FUNCTION: chestnut_restart
 449  *
 450  * DESCRIPTION: ppc_md machine reset callback
 451  *              reset the board via the CPLD command register
 452  *
 453  ****/
 454 static void
 455 chestnut_restart(char *cmd)
 456 {
 457         volatile ulong i = 10000000;
 458
 459         local_irq_disable();
 460
 461         /*
 462          * Set CPLD Reg 3 bit 0 to 1 to allow MPP signals on reset to work
 463          *
 464          * MPP24 - board reset
 465          */
 466         writeb(0x1, cpld_base + 3);
 467
 468         /* GPP pin tied to MPP earlier */
 469         mv64x60_set_bits(&bh, MV64x60_GPP_VALUE_SET, BIT(24));
 470
 471         while (i-- > 0);
 472         panic("restart failed\n");
 473 }
 474
 475 static void
 476 chestnut_halt(void)
 477 {
 478         local_irq_disable();
 479         for (;;);
 480         /* NOTREACHED */
 481 }
 482
 483 static void
 484 chestnut_power_off(void)
 485 {
 486         chestnut_halt();
 487         /* NOTREACHED */
 488 }
 489
 490 /**************************************************************************
 491  * FUNCTION: chestnut_map_io
 492  *
 493  * DESCRIPTION: configure fixed memory-mapped IO
 494  *
 495  ****/
 496 static void __init
 497 chestnut_map_io(void)
 498 {
 499 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 500         io_block_mapping(CHESTNUT_UART_BASE, CHESTNUT_UART_BASE, 0x100000,
 501                 _PAGE_IO);
 502 #endif
 503 }
 504
 505 /**************************************************************************
 506  * FUNCTION: chestnut_set_bat
 507  *
 508  * DESCRIPTION: configures a (temporary) bat mapping for early access to
 509  *              device I/O
 510  *
 511  ****/
 512 static __inline__ void
 513 chestnut_set_bat(void)
 514 {
 515         mb();
 516         mtspr(SPRN_DBAT3U, 0xf0001ffe);
 517         mtspr(SPRN_DBAT3L, 0xf000002a);
 518         mb();
 519 }
 520
 521 /**************************************************************************
 522  * FUNCTION: platform_init
 523  *
 524  * DESCRIPTION: main entry point for configuring board-specific machine
 525  *              callbacks
 526  *
 527  ****/
 528 void __init
 529 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 530               unsigned long r6, unsigned long r7)
 531 {
 532         parse_bootinfo(find_bootinfo());
 533
 534         /* Copy the kernel command line arguments to a safe place. */
 535
 536         if (r6) {
 537                 *(char *) (r7 + KERNELBASE) = 0;
 538                 strcpy(cmd_line, (char *) (r6 + KERNELBASE));
 539         }
 540
 541         isa_mem_base = 0;
 542
 543         ppc_md.setup_arch = chestnut_setup_arch;
 544         ppc_md.show_cpuinfo = chestnut_show_cpuinfo;
 545         ppc_md.irq_canonicalize = NULL;
 546         ppc_md.init_IRQ = mv64360_init_irq;
 547         ppc_md.get_irq = mv64360_get_irq;
 548         ppc_md.init = NULL;
 549
 550         ppc_md.find_end_of_memory = chestnut_find_end_of_memory;
 551         ppc_md.setup_io_mappings  = chestnut_map_io;
 552
 553         ppc_md.restart = chestnut_restart;
 554         ppc_md.power_off = chestnut_power_off;
 555         ppc_md.halt = chestnut_halt;
 556
 557         ppc_md.time_init = NULL;
 558         ppc_md.set_rtc_time = NULL;
 559         ppc_md.get_rtc_time = NULL;
 560         ppc_md.calibrate_decr = chestnut_calibrate_decr;
 561
 562         ppc_md.nvram_read_val = NULL;
 563         ppc_md.nvram_write_val = NULL;
 564
 565         ppc_md.heartbeat = NULL;
 566
 567         bh.p_base = CONFIG_MV64X60_NEW_BASE;
 568
 569         chestnut_set_bat();
 570
 571 #if defined(CONFIG_SERIAL_TEXT_DEBUG)
 572         ppc_md.progress = gen550_progress;
 573 #endif
 574 #if defined(CONFIG_KGDB)
 575         ppc_md.kgdb_map_scc = gen550_kgdb_map_scc;
 576 #endif
 577
 578         if (ppc_md.progress)
 579                 ppc_md.progress("chestnut_init(): exit", 0);
 580 }