2 * Board setup routines for the Marvell EV-64360-BP Evaluation Board.
4 * Author: Lee Nicks <allinux@gmail.com>
6 * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
7 * Based on code done by - Mark A. Greer <mgreer@mvista.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 #include <linux/config.h>
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/kdev_t.h>
18 #include <linux/console.h>
19 #include <linux/initrd.h>
20 #include <linux/root_dev.h>
21 #include <linux/delay.h>
22 #include <linux/seq_file.h>
23 #include <linux/bootmem.h>
24 #include <linux/mtd/physmap.h>
25 #include <linux/mv643xx.h>
26 #include <linux/platform_device.h>
28 #include <linux/bootimg.h>
34 #include <asm/bootinfo.h>
35 #include <asm/ppcboot.h>
36 #include <asm/mv64x60.h>
37 #include <asm/machdep.h>
38 #include <platforms/ev64360.h>
40 #define BOARD_VENDOR "Marvell"
41 #define BOARD_MACHINE "EV-64360-BP"
43 static struct mv64x60_handle bh
;
44 static void __iomem
*sram_base
;
46 static u32 ev64360_flash_size_0
;
47 static u32 ev64360_flash_size_1
;
49 static u32 ev64360_bus_frequency
;
51 unsigned char __res
[sizeof(bd_t
)];
56 ev64360_map_irq(struct pci_dev
*dev
, unsigned char idsel
, unsigned char pin
)
62 ev64360_setup_bridge(void)
64 struct mv64x60_setup_info si
;
67 memset(&si
, 0, sizeof(si
));
69 si
.phys_reg_base
= CONFIG_MV64X60_NEW_BASE
;
72 si
.pci_1
.enable_bus
= 1;
73 si
.pci_1
.pci_io
.cpu_base
= EV64360_PCI1_IO_START_PROC_ADDR
;
74 si
.pci_1
.pci_io
.pci_base_hi
= 0;
75 si
.pci_1
.pci_io
.pci_base_lo
= EV64360_PCI1_IO_START_PCI_ADDR
;
76 si
.pci_1
.pci_io
.size
= EV64360_PCI1_IO_SIZE
;
77 si
.pci_1
.pci_io
.swap
= MV64x60_CPU2PCI_SWAP_NONE
;
78 si
.pci_1
.pci_mem
[0].cpu_base
= EV64360_PCI1_MEM_START_PROC_ADDR
;
79 si
.pci_1
.pci_mem
[0].pci_base_hi
= EV64360_PCI1_MEM_START_PCI_HI_ADDR
;
80 si
.pci_1
.pci_mem
[0].pci_base_lo
= EV64360_PCI1_MEM_START_PCI_LO_ADDR
;
81 si
.pci_1
.pci_mem
[0].size
= EV64360_PCI1_MEM_SIZE
;
82 si
.pci_1
.pci_mem
[0].swap
= MV64x60_CPU2PCI_SWAP_NONE
;
83 si
.pci_1
.pci_cmd_bits
= 0;
84 si
.pci_1
.latency_timer
= 0x80;
86 si
.pci_0
.enable_bus
= 0;
87 si
.pci_1
.enable_bus
= 0;
90 for (i
= 0; i
< MV64x60_CPU2MEM_WINDOWS
; i
++) {
91 #if defined(CONFIG_NOT_COHERENT_CACHE)
92 si
.cpu_prot_options
[i
] = 0;
93 si
.enet_options
[i
] = MV64360_ENET2MEM_SNOOP_NONE
;
94 si
.mpsc_options
[i
] = MV64360_MPSC2MEM_SNOOP_NONE
;
95 si
.idma_options
[i
] = MV64360_IDMA2MEM_SNOOP_NONE
;
97 si
.pci_1
.acc_cntl_options
[i
] =
98 MV64360_PCI_ACC_CNTL_SNOOP_NONE
|
99 MV64360_PCI_ACC_CNTL_SWAP_NONE
|
100 MV64360_PCI_ACC_CNTL_MBURST_128_BYTES
|
101 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES
;
103 si
.cpu_prot_options
[i
] = 0;
104 si
.enet_options
[i
] = MV64360_ENET2MEM_SNOOP_NONE
; /* errata */
105 si
.mpsc_options
[i
] = MV64360_MPSC2MEM_SNOOP_NONE
; /* errata */
106 si
.idma_options
[i
] = MV64360_IDMA2MEM_SNOOP_NONE
; /* errata */
108 si
.pci_1
.acc_cntl_options
[i
] =
109 MV64360_PCI_ACC_CNTL_SNOOP_WB
|
110 MV64360_PCI_ACC_CNTL_SWAP_NONE
|
111 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES
|
112 MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES
;
116 if (mv64x60_init(&bh
, &si
))
117 printk(KERN_WARNING
"Bridge initialization failed.\n");
120 pci_dram_offset
= 0; /* sys mem at same addr on PCI & cpu bus */
121 ppc_md
.pci_swizzle
= common_swizzle
;
122 ppc_md
.pci_map_irq
= ev64360_map_irq
;
123 ppc_md
.pci_exclude_device
= mv64x60_pci_exclude_device
;
125 mv64x60_set_bus(&bh
, 1, 0);
126 bh
.hose_b
->first_busno
= 0;
127 bh
.hose_b
->last_busno
= 0xff;
131 /* Bridge & platform setup routines */
133 ev64360_intr_setup(void)
135 /* MPP 8, 9, and 10 */
136 mv64x60_clr_bits(&bh
, MV64x60_MPP_CNTL_1
, 0xfff);
139 * Define GPP 8,9,and 10 interrupt polarity as active low
140 * input signal and level triggered
142 mv64x60_set_bits(&bh
, MV64x60_GPP_LEVEL_CNTL
, 0x700);
143 mv64x60_clr_bits(&bh
, MV64x60_GPP_IO_CNTL
, 0x700);
145 /* Config GPP intr ctlr to respond to level trigger */
146 mv64x60_set_bits(&bh
, MV64x60_COMM_ARBITER_CNTL
, (1<<10));
148 /* Erranum FEr PCI-#8 */
149 mv64x60_clr_bits(&bh
, MV64x60_PCI0_CMD
, (1<<5) | (1<<9));
150 mv64x60_clr_bits(&bh
, MV64x60_PCI1_CMD
, (1<<5) | (1<<9));
153 * Dismiss and then enable interrupt on GPP interrupt cause
156 mv64x60_write(&bh
, MV64x60_GPP_INTR_CAUSE
, ~0x700);
157 mv64x60_set_bits(&bh
, MV64x60_GPP_INTR_MASK
, 0x700);
160 * Dismiss and then enable interrupt on CPU #0 high cause reg
161 * BIT25 summarizes GPP interrupts 8-15
163 mv64x60_set_bits(&bh
, MV64360_IC_CPU0_INTR_MASK_HI
, (1<<25));
167 ev64360_setup_peripherals(void)
171 /* Set up window for boot CS */
172 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2BOOT_WIN
,
173 EV64360_BOOT_WINDOW_BASE
, EV64360_BOOT_WINDOW_SIZE
, 0);
174 bh
.ci
->enable_window_32bit(&bh
, MV64x60_CPU2BOOT_WIN
);
176 /* We only use the 32-bit flash */
177 mv64x60_get_32bit_window(&bh
, MV64x60_CPU2BOOT_WIN
, &base
,
178 &ev64360_flash_size_0
);
179 ev64360_flash_size_1
= 0;
181 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2DEV_1_WIN
,
182 EV64360_RTC_WINDOW_BASE
, EV64360_RTC_WINDOW_SIZE
, 0);
183 bh
.ci
->enable_window_32bit(&bh
, MV64x60_CPU2DEV_1_WIN
);
185 TODC_INIT(TODC_TYPE_DS1501
, 0, 0,
186 ioremap(EV64360_RTC_WINDOW_BASE
, EV64360_RTC_WINDOW_SIZE
), 8);
188 mv64x60_set_32bit_window(&bh
, MV64x60_CPU2SRAM_WIN
,
189 EV64360_INTERNAL_SRAM_BASE
, MV64360_SRAM_SIZE
, 0);
190 bh
.ci
->enable_window_32bit(&bh
, MV64x60_CPU2SRAM_WIN
);
191 sram_base
= ioremap(EV64360_INTERNAL_SRAM_BASE
, MV64360_SRAM_SIZE
);
193 /* Set up Enet->SRAM window */
194 mv64x60_set_32bit_window(&bh
, MV64x60_ENET2MEM_4_WIN
,
195 EV64360_INTERNAL_SRAM_BASE
, MV64360_SRAM_SIZE
, 0x2);
196 bh
.ci
->enable_window_32bit(&bh
, MV64x60_ENET2MEM_4_WIN
);
198 /* Give enet r/w access to memory region */
199 mv64x60_set_bits(&bh
, MV64360_ENET2MEM_ACC_PROT_0
, (0x3 << (4 << 1)));
200 mv64x60_set_bits(&bh
, MV64360_ENET2MEM_ACC_PROT_1
, (0x3 << (4 << 1)));
201 mv64x60_set_bits(&bh
, MV64360_ENET2MEM_ACC_PROT_2
, (0x3 << (4 << 1)));
203 mv64x60_clr_bits(&bh
, MV64x60_PCI1_PCI_DECODE_CNTL
, (1 << 3));
204 mv64x60_clr_bits(&bh
, MV64x60_TIMR_CNTR_0_3_CNTL
,
205 ((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24)));
207 #if defined(CONFIG_NOT_COHERENT_CACHE)
208 mv64x60_write(&bh
, MV64360_SRAM_CONFIG
, 0x00160000);
210 mv64x60_write(&bh
, MV64360_SRAM_CONFIG
, 0x001600b2);
214 * Setting the SRAM to 0. Note that this generates parity errors on
215 * internal data path in SRAM since it's first time accessing it
216 * while after reset it's not configured.
218 memset(sram_base
, 0, MV64360_SRAM_SIZE
);
220 /* set up PCI interrupt controller */
221 ev64360_intr_setup();
225 ev64360_setup_arch(void)
228 ppc_md
.progress("ev64360_setup_arch: enter", 0);
232 #ifdef CONFIG_BLK_DEV_INITRD
234 ROOT_DEV
= Root_RAM0
;
237 #ifdef CONFIG_ROOT_NFS
240 ROOT_DEV
= Root_SDA2
;
244 * Set up the L2CR register.
246 _set_L2CR(L2CR_L2E
| L2CR_L2PE
);
249 ppc_md
.progress("ev64360_setup_arch: calling setup_bridge", 0);
251 ev64360_setup_bridge();
252 ev64360_setup_peripherals();
253 ev64360_bus_frequency
= ev64360_bus_freq();
255 printk(KERN_INFO
"%s %s port (C) 2005 Lee Nicks "
256 "(allinux@gmail.com)\n", BOARD_VENDOR
, BOARD_MACHINE
);
258 ppc_md
.progress("ev64360_setup_arch: exit", 0);
261 /* Platform device data fixup routines. */
262 #if defined(CONFIG_SERIAL_MPSC)
264 ev64360_fixup_mpsc_pdata(struct platform_device
*pdev
)
266 struct mpsc_pdata
*pdata
;
268 pdata
= (struct mpsc_pdata
*)pdev
->dev
.platform_data
;
270 pdata
->max_idle
= 40;
271 pdata
->default_baud
= EV64360_DEFAULT_BAUD
;
272 pdata
->brg_clk_src
= EV64360_MPSC_CLK_SRC
;
274 * TCLK (not SysCLk) is routed to BRG, then to the MPSC. On most parts,
275 * TCLK == SysCLK but on 64460, they are separate pins.
276 * SysCLK can go up to 200 MHz but TCLK can only go up to 133 MHz.
278 pdata
->brg_clk_freq
= min(ev64360_bus_frequency
, MV64x60_TCLK_FREQ_MAX
);
282 #if defined(CONFIG_MV643XX_ETH)
284 ev64360_fixup_eth_pdata(struct platform_device
*pdev
)
286 struct mv643xx_eth_platform_data
*eth_pd
;
287 static u16 phy_addr
[] = {
288 EV64360_ETH0_PHY_ADDR
,
289 EV64360_ETH1_PHY_ADDR
,
290 EV64360_ETH2_PHY_ADDR
,
293 eth_pd
= pdev
->dev
.platform_data
;
294 eth_pd
->force_phy_addr
= 1;
295 eth_pd
->phy_addr
= phy_addr
[pdev
->id
];
296 eth_pd
->tx_queue_size
= EV64360_ETH_TX_QUEUE_SIZE
;
297 eth_pd
->rx_queue_size
= EV64360_ETH_RX_QUEUE_SIZE
;
302 ev64360_platform_notify(struct device
*dev
)
306 void ((*rtn
)(struct platform_device
*pdev
));
308 #if defined(CONFIG_SERIAL_MPSC)
309 { MPSC_CTLR_NAME
".0", ev64360_fixup_mpsc_pdata
},
310 { MPSC_CTLR_NAME
".1", ev64360_fixup_mpsc_pdata
},
312 #if defined(CONFIG_MV643XX_ETH)
313 { MV643XX_ETH_NAME
".0", ev64360_fixup_eth_pdata
},
314 { MV643XX_ETH_NAME
".1", ev64360_fixup_eth_pdata
},
315 { MV643XX_ETH_NAME
".2", ev64360_fixup_eth_pdata
},
318 struct platform_device
*pdev
;
321 if (dev
&& dev
->bus_id
)
322 for (i
=0; i
<ARRAY_SIZE(dev_map
); i
++)
323 if (!strncmp(dev
->bus_id
, dev_map
[i
].bus_id
,
326 pdev
= container_of(dev
,
327 struct platform_device
, dev
);
328 dev_map
[i
].rtn(pdev
);
334 #ifdef CONFIG_MTD_PHYSMAP
343 * FLASH Amount: 0xff000000 - 0xffffffff
344 * ------------- -----------------------
345 * Reserved: 0xff000000 - 0xff03ffff
346 * JFFS2 file system: 0xff040000 - 0xffefffff
347 * U-boot: 0xfff00000 - 0xffffffff
350 ev64360_setup_mtd(void)
354 static struct mtd_partition
*ptbl
;
356 size
= ev64360_flash_size_0
+ ev64360_flash_size_1
;
362 if ((ptbl
= kmalloc(ptbl_entries
* sizeof(struct mtd_partition
),
363 GFP_KERNEL
)) == NULL
) {
365 printk(KERN_WARNING
"Can't alloc MTD partition table\n");
368 memset(ptbl
, 0, ptbl_entries
* sizeof(struct mtd_partition
));
370 ptbl
[0].name
= "reserved";
372 ptbl
[0].size
= EV64360_MTD_RESERVED_SIZE
;
373 ptbl
[1].name
= "jffs2";
374 ptbl
[1].offset
= EV64360_MTD_RESERVED_SIZE
;
375 ptbl
[1].size
= EV64360_MTD_JFFS2_SIZE
;
376 ptbl
[2].name
= "U-BOOT";
377 ptbl
[2].offset
= EV64360_MTD_RESERVED_SIZE
+ EV64360_MTD_JFFS2_SIZE
;
378 ptbl
[2].size
= EV64360_MTD_UBOOT_SIZE
;
380 physmap_map
.size
= size
;
381 physmap_set_partitions(ptbl
, ptbl_entries
);
385 arch_initcall(ev64360_setup_mtd
);
389 ev64360_restart(char *cmd
)
391 ulong i
= 0xffffffff;
392 volatile unsigned char * rtc_base
= ioremap(EV64360_RTC_WINDOW_BASE
,0x4000);
394 /* issue hard reset */
395 rtc_base
[0xf] = 0x80;
396 rtc_base
[0xc] = 0x00;
397 rtc_base
[0xd] = 0x01;
398 rtc_base
[0xf] = 0x83;
401 panic("restart failed\n");
412 ev64360_power_off(void)
419 ev64360_show_cpuinfo(struct seq_file
*m
)
421 seq_printf(m
, "vendor\t\t: " BOARD_VENDOR
"\n");
422 seq_printf(m
, "machine\t\t: " BOARD_MACHINE
"\n");
423 seq_printf(m
, "bus speed\t: %dMHz\n", ev64360_bus_frequency
/1000/1000);
429 ev64360_calibrate_decr(void)
433 freq
= ev64360_bus_frequency
/ 4;
435 printk(KERN_INFO
"time_init: decrementer frequency = %lu.%.6lu MHz\n",
436 (long)freq
/ 1000000, (long)freq
% 1000000);
438 tb_ticks_per_jiffy
= freq
/ HZ
;
439 tb_to_us
= mulhwu_scale_factor(freq
, 1000000);
443 ev64360_find_end_of_memory(void)
445 return mv64x60_get_mem_size(CONFIG_MV64X60_NEW_BASE
,
446 MV64x60_TYPE_MV64360
);
450 ev64360_set_bat(void)
453 mtspr(SPRN_DBAT2U
, 0xf0001ffe);
454 mtspr(SPRN_DBAT2L
, 0xf000002a);
458 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
462 io_block_mapping(CONFIG_MV64X60_NEW_BASE
, \
463 CONFIG_MV64X60_NEW_BASE
, \
464 0x00020000, _PAGE_IO
);
469 platform_init(unsigned long r3
, unsigned long r4
, unsigned long r5
,
470 unsigned long r6
, unsigned long r7
)
472 parse_bootinfo(find_bootinfo());
474 /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer)
475 * are non-zero, then we should use the board info from the bd_t
476 * structure and the cmdline pointed to by r6 instead of the
477 * information from birecs, if any. Otherwise, use the information
478 * from birecs as discovered by the preceeding call to
479 * parse_bootinfo(). This rule should work with both PPCBoot, which
480 * uses a bd_t board info structure, and the kernel boot wrapper,
484 /* copy board info structure */
485 memcpy( (void *)__res
,(void *)(r3
+KERNELBASE
), sizeof(bd_t
) );
486 /* copy command line */
487 *(char *)(r7
+KERNELBASE
) = 0;
488 strcpy(cmd_line
, (char *)(r6
+KERNELBASE
));
494 ppc_md
.setup_arch
= ev64360_setup_arch
;
495 ppc_md
.show_cpuinfo
= ev64360_show_cpuinfo
;
496 ppc_md
.init_IRQ
= mv64360_init_irq
;
497 ppc_md
.get_irq
= mv64360_get_irq
;
498 ppc_md
.restart
= ev64360_restart
;
499 ppc_md
.power_off
= ev64360_power_off
;
500 ppc_md
.halt
= ev64360_halt
;
501 ppc_md
.find_end_of_memory
= ev64360_find_end_of_memory
;
504 ppc_md
.time_init
= todc_time_init
;
505 ppc_md
.set_rtc_time
= todc_set_rtc_time
;
506 ppc_md
.get_rtc_time
= todc_get_rtc_time
;
507 ppc_md
.nvram_read_val
= todc_direct_read_val
;
508 ppc_md
.nvram_write_val
= todc_direct_write_val
;
509 ppc_md
.calibrate_decr
= ev64360_calibrate_decr
;
511 #if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(CONFIG_SERIAL_MPSC_CONSOLE)
512 ppc_md
.setup_io_mappings
= ev64360_map_io
;
513 ppc_md
.progress
= mv64x60_mpsc_progress
;
514 mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE
);
517 #if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH)
518 platform_notify
= ev64360_platform_notify
;
521 ev64360_set_bat(); /* Need for ev64360_find_end_of_memory and progress */