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1 /*
2 * Board setup routines for the Radstone PPC7D boards.
3 *
4 * Author: James Chapman <jchapman@katalix.com>
5 *
6 * Based on code done by Rabeeh Khoury - rabeeh@galileo.co.il
7 * Based on code done by - Mark A. Greer <mgreer@mvista.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 */
14
15 /* Radstone PPC7D boards are rugged VME boards with PPC 7447A CPUs,
16 * Discovery-II, dual gigabit ethernet, dual PMC, USB, keyboard/mouse,
17 * 4 serial ports, 2 high speed serial ports (MPSCs) and optional
18 * SCSI / VGA.
19 */
20
21 #include <linux/config.h>
22 #include <linux/stddef.h>
23 #include <linux/kernel.h>
24 #include <linux/init.h>
25 #include <linux/errno.h>
26 #include <linux/reboot.h>
27 #include <linux/pci.h>
28 #include <linux/kdev_t.h>
29 #include <linux/major.h>
30 #include <linux/initrd.h>
31 #include <linux/console.h>
32 #include <linux/delay.h>
33 #include <linux/ide.h>
34 #include <linux/seq_file.h>
35 #include <linux/root_dev.h>
36 #include <linux/serial.h>
37 #include <linux/tty.h> /* for linux/serial_core.h */
38 #include <linux/serial_core.h>
39 #include <linux/mv643xx.h>
40 #include <linux/netdevice.h>
41 #include <linux/platform_device.h>
42
43 #include <asm/system.h>
44 #include <asm/pgtable.h>
45 #include <asm/page.h>
46 #include <asm/time.h>
47 #include <asm/dma.h>
48 #include <asm/io.h>
49 #include <asm/machdep.h>
50 #include <asm/prom.h>
51 #include <asm/smp.h>
52 #include <asm/vga.h>
53 #include <asm/open_pic.h>
54 #include <asm/i8259.h>
55 #include <asm/todc.h>
56 #include <asm/bootinfo.h>
57 #include <asm/mpc10x.h>
58 #include <asm/pci-bridge.h>
59 #include <asm/mv64x60.h>
60
61 #include "radstone_ppc7d.h"
62
63 #undef DEBUG
64
65 #define PPC7D_RST_PIN 17 /* GPP17 */
66
67 extern u32 mv64360_irq_base;
68 extern spinlock_t rtc_lock;
69
70 static struct mv64x60_handle bh;
71 static int ppc7d_has_alma;
72
73 extern void gen550_progress(char *, unsigned short);
74 extern void gen550_init(int, struct uart_port *);
75
76 /* FIXME - move to h file */
77 extern int ds1337_do_command(int id, int cmd, void *arg);
78 #define DS1337_GET_DATE 0
79 #define DS1337_SET_DATE 1
80
81 /* residual data */
82 unsigned char __res[sizeof(bd_t)];
83
84 /*****************************************************************************
85 * Serial port code
86 *****************************************************************************/
87
88 #if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG)
89 static void __init ppc7d_early_serial_map(void)
90 {
91 #if defined(CONFIG_SERIAL_MPSC_CONSOLE)
92 mv64x60_progress_init(CONFIG_MV64X60_NEW_BASE);
93 #elif defined(CONFIG_SERIAL_8250)
94 struct uart_port serial_req;
95
96 /* Setup serial port access */
97 memset(&serial_req, 0, sizeof(serial_req));
98 serial_req.uartclk = UART_CLK;
99 serial_req.irq = 4;
100 serial_req.flags = STD_COM_FLAGS;
101 serial_req.iotype = UPIO_MEM;
102 serial_req.membase = (u_char *) PPC7D_SERIAL_0;
103
104 gen550_init(0, &serial_req);
105 if (early_serial_setup(&serial_req) != 0)
106 printk(KERN_ERR "Early serial init of port 0 failed\n");
107
108 /* Assume early_serial_setup() doesn't modify serial_req */
109 serial_req.line = 1;
110 serial_req.irq = 3;
111 serial_req.membase = (u_char *) PPC7D_SERIAL_1;
112
113 gen550_init(1, &serial_req);
114 if (early_serial_setup(&serial_req) != 0)
115 printk(KERN_ERR "Early serial init of port 1 failed\n");
116 #else
117 #error CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG has no supported CONFIG_SERIAL_XXX
118 #endif
119 }
120 #endif /* CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG */
121
122 /*****************************************************************************
123 * Low-level board support code
124 *****************************************************************************/
125
126 static unsigned long __init ppc7d_find_end_of_memory(void)
127 {
128 bd_t *bp = (bd_t *) __res;
129
130 if (bp->bi_memsize)
131 return bp->bi_memsize;
132
133 return (256 * 1024 * 1024);
134 }
135
136 static void __init ppc7d_map_io(void)
137 {
138 /* remove temporary mapping */
139 mtspr(SPRN_DBAT3U, 0x00000000);
140 mtspr(SPRN_DBAT3L, 0x00000000);
141
142 io_block_mapping(0xe8000000, 0xe8000000, 0x08000000, _PAGE_IO);
143 io_block_mapping(0xfe000000, 0xfe000000, 0x02000000, _PAGE_IO);
144 }
145
146 static void ppc7d_restart(char *cmd)
147 {
148 u32 data;
149
150 /* Disable GPP17 interrupt */
151 data = mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
152 data &= ~(1 << PPC7D_RST_PIN);
153 mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, data);
154
155 /* Configure MPP17 as GPP */
156 data = mv64x60_read(&bh, MV64x60_MPP_CNTL_2);
157 data &= ~(0x0000000f << 4);
158 mv64x60_write(&bh, MV64x60_MPP_CNTL_2, data);
159
160 /* Enable pin GPP17 for output */
161 data = mv64x60_read(&bh, MV64x60_GPP_IO_CNTL);
162 data |= (1 << PPC7D_RST_PIN);
163 mv64x60_write(&bh, MV64x60_GPP_IO_CNTL, data);
164
165 /* Toggle GPP9 pin to reset the board */
166 mv64x60_write(&bh, MV64x60_GPP_VALUE_CLR, 1 << PPC7D_RST_PIN);
167 mv64x60_write(&bh, MV64x60_GPP_VALUE_SET, 1 << PPC7D_RST_PIN);
168
169 for (;;) ; /* Spin until reset happens */
170 /* NOTREACHED */
171 }
172
173 static void ppc7d_power_off(void)
174 {
175 u32 data;
176
177 local_irq_disable();
178
179 /* Ensure that internal MV643XX watchdog is disabled.
180 * The Disco watchdog uses MPP17 on this hardware.
181 */
182 data = mv64x60_read(&bh, MV64x60_MPP_CNTL_2);
183 data &= ~(0x0000000f << 4);
184 mv64x60_write(&bh, MV64x60_MPP_CNTL_2, data);
185
186 data = mv64x60_read(&bh, MV64x60_WDT_WDC);
187 if (data & 0x80000000) {
188 mv64x60_write(&bh, MV64x60_WDT_WDC, 1 << 24);
189 mv64x60_write(&bh, MV64x60_WDT_WDC, 2 << 24);
190 }
191
192 for (;;) ; /* No way to shut power off with software */
193 /* NOTREACHED */
194 }
195
196 static void ppc7d_halt(void)
197 {
198 ppc7d_power_off();
199 /* NOTREACHED */
200 }
201
202 static unsigned long ppc7d_led_no_pulse;
203
204 static int __init ppc7d_led_pulse_disable(char *str)
205 {
206 ppc7d_led_no_pulse = 1;
207 return 1;
208 }
209
210 /* This kernel option disables the heartbeat pulsing of a board LED */
211 __setup("ledoff", ppc7d_led_pulse_disable);
212
213 static void ppc7d_heartbeat(void)
214 {
215 u32 data32;
216 u8 data8;
217 static int max706_wdog = 0;
218
219 /* Unfortunately we can't access the LED control registers
220 * during early init because they're on the CPLD which is the
221 * other side of a PCI bridge which goes unreachable during
222 * PCI scan. So write the LEDs only if the MV64360 watchdog is
223 * enabled (i.e. userspace apps are running so kernel is up)..
224 */
225 data32 = mv64x60_read(&bh, MV64x60_WDT_WDC);
226 if (data32 & 0x80000000) {
227 /* Enable MAX706 watchdog if not done already */
228 if (!max706_wdog) {
229 outb(3, PPC7D_CPLD_RESET);
230 max706_wdog = 1;
231 }
232
233 /* Hit the MAX706 watchdog */
234 outb(0, PPC7D_CPLD_WATCHDOG_TRIG);
235
236 /* Pulse LED DS219 if not disabled */
237 if (!ppc7d_led_no_pulse) {
238 static int led_on = 0;
239
240 data8 = inb(PPC7D_CPLD_LEDS);
241 if (led_on)
242 data8 &= ~PPC7D_CPLD_LEDS_DS219_MASK;
243 else
244 data8 |= PPC7D_CPLD_LEDS_DS219_MASK;
245
246 outb(data8, PPC7D_CPLD_LEDS);
247 led_on = !led_on;
248 }
249 }
250 ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
251 }
252
253 static int ppc7d_show_cpuinfo(struct seq_file *m)
254 {
255 u8 val;
256 u8 val1, val2;
257 static int flash_sizes[4] = { 64, 32, 0, 16 };
258 static int flash_banks[4] = { 4, 3, 2, 1 };
259 static int sdram_bank_sizes[4] = { 128, 256, 512, 1 };
260 int sdram_num_banks = 2;
261 static char *pci_modes[] = { "PCI33", "PCI66",
262 "Unknown", "Unknown",
263 "PCIX33", "PCIX66",
264 "PCIX100", "PCIX133"
265 };
266
267 seq_printf(m, "vendor\t\t: Radstone Technology\n");
268 seq_printf(m, "machine\t\t: PPC7D\n");
269
270 val = inb(PPC7D_CPLD_BOARD_REVISION);
271 val1 = (val & PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK) >> 5;
272 val2 = (val & PPC7D_CPLD_BOARD_REVISION_LETTER_MASK);
273 seq_printf(m, "revision\t: %hd%c%c\n",
274 val1,
275 (val2 <= 0x18) ? 'A' + val2 : 'Y',
276 (val2 > 0x18) ? 'A' + (val2 - 0x19) : ' ');
277
278 val = inb(PPC7D_CPLD_MOTHERBOARD_TYPE);
279 val1 = val & PPC7D_CPLD_MB_TYPE_PLL_MASK;
280 val2 = val & (PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK |
281 PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK);
282 seq_printf(m, "bus speed\t: %dMHz\n",
283 (val1 == PPC7D_CPLD_MB_TYPE_PLL_133) ? 133 :
284 (val1 == PPC7D_CPLD_MB_TYPE_PLL_100) ? 100 :
285 (val1 == PPC7D_CPLD_MB_TYPE_PLL_64) ? 64 : 0);
286
287 val = inb(PPC7D_CPLD_MEM_CONFIG);
288 if (val & PPC7D_CPLD_SDRAM_BANK_NUM_MASK) sdram_num_banks--;
289
290 val = inb(PPC7D_CPLD_MEM_CONFIG_EXTEND);
291 val1 = (val & PPC7D_CPLD_SDRAM_BANK_SIZE_MASK) >> 6;
292 seq_printf(m, "SDRAM\t\t: %d banks of %d%c, total %d%c",
293 sdram_num_banks,
294 sdram_bank_sizes[val1],
295 (sdram_bank_sizes[val1] < 128) ? 'G' : 'M',
296 sdram_num_banks * sdram_bank_sizes[val1],
297 (sdram_bank_sizes[val1] < 128) ? 'G' : 'M');
298 if (val2 & PPC7D_CPLD_MB_TYPE_ECC_FITTED_MASK) {
299 seq_printf(m, " [ECC %sabled]",
300 (val2 & PPC7D_CPLD_MB_TYPE_ECC_ENABLE_MASK) ? "en" :
301 "dis");
302 }
303 seq_printf(m, "\n");
304
305 val1 = (val & PPC7D_CPLD_FLASH_DEV_SIZE_MASK);
306 val2 = (val & PPC7D_CPLD_FLASH_BANK_NUM_MASK) >> 2;
307 seq_printf(m, "FLASH\t\t: %d banks of %dM, total %dM\n",
308 flash_banks[val2], flash_sizes[val1],
309 flash_banks[val2] * flash_sizes[val1]);
310
311 val = inb(PPC7D_CPLD_FLASH_WRITE_CNTL);
312 val1 = inb(PPC7D_CPLD_SW_FLASH_WRITE_PROTECT);
313 seq_printf(m, " write links\t: %s%s%s%s\n",
314 (val & PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK) ? "WRITE " : "",
315 (val & PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK) ? "BOOT " : "",
316 (val & PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK) ? "USER " : "",
317 (val & (PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK |
318 PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK |
319 PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK)) ==
320 0 ? "NONE" : "");
321 seq_printf(m, " write sector h/w enables: %s%s%s%s%s\n",
322 (val & PPD7D_CPLD_FLASH_CNTL_RECO_WR_MASK) ? "RECOVERY " :
323 "",
324 (val & PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK) ? "BOOT " : "",
325 (val & PPD7D_CPLD_FLASH_CNTL_USER_WR_MASK) ? "USER " : "",
326 (val1 & PPC7D_CPLD_FLASH_CNTL_NVRAM_PROT_MASK) ? "NVRAM " :
327 "",
328 (((val &
329 (PPD7D_CPLD_FLASH_CNTL_RECO_WR_MASK |
330 PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK |
331 PPD7D_CPLD_FLASH_CNTL_BOOT_WR_MASK)) == 0)
332 && ((val1 & PPC7D_CPLD_FLASH_CNTL_NVRAM_PROT_MASK) ==
333 0)) ? "NONE" : "");
334 val1 =
335 inb(PPC7D_CPLD_SW_FLASH_WRITE_PROTECT) &
336 (PPC7D_CPLD_SW_FLASH_WRPROT_SYSBOOT_MASK |
337 PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK);
338 seq_printf(m, " software sector enables: %s%s%s\n",
339 (val1 & PPC7D_CPLD_SW_FLASH_WRPROT_SYSBOOT_MASK) ? "SYSBOOT "
340 : "",
341 (val1 & PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK) ? "USER " : "",
342 (val1 == 0) ? "NONE " : "");
343
344 seq_printf(m, "Boot options\t: %s%s%s%s\n",
345 (val & PPC7D_CPLD_FLASH_CNTL_ALTBOOT_LINK_MASK) ?
346 "ALTERNATE " : "",
347 (val & PPC7D_CPLD_FLASH_CNTL_VMEBOOT_LINK_MASK) ? "VME " :
348 "",
349 (val & PPC7D_CPLD_FLASH_CNTL_RECBOOT_LINK_MASK) ? "RECOVERY "
350 : "",
351 ((val &
352 (PPC7D_CPLD_FLASH_CNTL_ALTBOOT_LINK_MASK |
353 PPC7D_CPLD_FLASH_CNTL_VMEBOOT_LINK_MASK |
354 PPC7D_CPLD_FLASH_CNTL_RECBOOT_LINK_MASK)) ==
355 0) ? "NONE" : "");
356
357 val = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_1);
358 seq_printf(m, "Fitted modules\t: %s%s%s%s\n",
359 (val & PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK) ? "" : "PMC1 ",
360 (val & PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK) ? "" : "PMC2 ",
361 (val & PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK) ? "AFIX " : "",
362 ((val & (PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK |
363 PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK |
364 PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK)) ==
365 (PPC7D_CPLD_EQPT_PRES_1_PMC1_MASK |
366 PPC7D_CPLD_EQPT_PRES_1_PMC2_MASK)) ? "NONE" : "");
367
368 if (val & PPC7D_CPLD_EQPT_PRES_1_AFIX_MASK) {
369 static const char *ids[] = {
370 "unknown",
371 "1553 (Dual Channel)",
372 "1553 (Single Channel)",
373 "8-bit SCSI + VGA",
374 "16-bit SCSI + VGA",
375 "1553 (Single Channel with sideband)",
376 "1553 (Dual Channel with sideband)",
377 NULL
378 };
379 u8 id = __raw_readb((void *)PPC7D_AFIX_REG_BASE + 0x03);
380 seq_printf(m, "AFIX module\t: 0x%hx [%s]\n", id,
381 id < 7 ? ids[id] : "unknown");
382 }
383
384 val = inb(PPC7D_CPLD_PCI_CONFIG);
385 val1 = (val & PPC7D_CPLD_PCI_CONFIG_PCI0_MASK) >> 4;
386 val2 = (val & PPC7D_CPLD_PCI_CONFIG_PCI1_MASK);
387 seq_printf(m, "PCI#0\t\t: %s\nPCI#1\t\t: %s\n",
388 pci_modes[val1], pci_modes[val2]);
389
390 val = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_2);
391 seq_printf(m, "PMC1\t\t: %s\nPMC2\t\t: %s\n",
392 (val & PPC7D_CPLD_EQPT_PRES_3_PMC1_V_MASK) ? "3.3v" : "5v",
393 (val & PPC7D_CPLD_EQPT_PRES_3_PMC2_V_MASK) ? "3.3v" : "5v");
394 seq_printf(m, "PMC power source: %s\n",
395 (val & PPC7D_CPLD_EQPT_PRES_3_PMC_POWER_MASK) ? "VME" :
396 "internal");
397
398 val = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_4);
399 val2 = inb(PPC7D_CPLD_EQUIPMENT_PRESENT_2);
400 seq_printf(m, "Fit options\t: %s%s%s%s%s%s%s\n",
401 (val & PPC7D_CPLD_EQPT_PRES_4_LPT_MASK) ? "LPT " : "",
402 (val & PPC7D_CPLD_EQPT_PRES_4_PS2_FITTED) ? "PS2 " : "",
403 (val & PPC7D_CPLD_EQPT_PRES_4_USB2_FITTED) ? "USB2 " : "",
404 (val2 & PPC7D_CPLD_EQPT_PRES_2_UNIVERSE_MASK) ? "VME " : "",
405 (val2 & PPC7D_CPLD_EQPT_PRES_2_COM36_MASK) ? "COM3-6 " : "",
406 (val2 & PPC7D_CPLD_EQPT_PRES_2_GIGE_MASK) ? "eth0 " : "",
407 (val2 & PPC7D_CPLD_EQPT_PRES_2_DUALGIGE_MASK) ? "eth1 " :
408 "");
409
410 val = inb(PPC7D_CPLD_ID_LINK);
411 val1 = val & (PPC7D_CPLD_ID_LINK_E6_MASK |
412 PPC7D_CPLD_ID_LINK_E7_MASK |
413 PPC7D_CPLD_ID_LINK_E12_MASK |
414 PPC7D_CPLD_ID_LINK_E13_MASK);
415
416 val = inb(PPC7D_CPLD_FLASH_WRITE_CNTL) &
417 (PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK |
418 PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK |
419 PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK);
420
421 seq_printf(m, "Board links present: %s%s%s%s%s%s%s%s\n",
422 (val1 & PPC7D_CPLD_ID_LINK_E6_MASK) ? "E6 " : "",
423 (val1 & PPC7D_CPLD_ID_LINK_E7_MASK) ? "E7 " : "",
424 (val & PPD7D_CPLD_FLASH_CNTL_WR_LINK_MASK) ? "E9 " : "",
425 (val & PPD7D_CPLD_FLASH_CNTL_BOOT_LINK_MASK) ? "E10 " : "",
426 (val & PPD7D_CPLD_FLASH_CNTL_USER_LINK_MASK) ? "E11 " : "",
427 (val1 & PPC7D_CPLD_ID_LINK_E12_MASK) ? "E12 " : "",
428 (val1 & PPC7D_CPLD_ID_LINK_E13_MASK) ? "E13 " : "",
429 ((val == 0) && (val1 == 0)) ? "NONE" : "");
430
431 val = inb(PPC7D_CPLD_WDOG_RESETSW_MASK);
432 seq_printf(m, "Front panel reset switch: %sabled\n",
433 (val & PPC7D_CPLD_WDOG_RESETSW_MASK) ? "dis" : "en");
434
435 return 0;
436 }
437
438 static void __init ppc7d_calibrate_decr(void)
439 {
440 ulong freq;
441
442 freq = 100000000 / 4;
443
444 pr_debug("time_init: decrementer frequency = %lu.%.6lu MHz\n",
445 freq / 1000000, freq % 1000000);
446
447 tb_ticks_per_jiffy = freq / HZ;
448 tb_to_us = mulhwu_scale_factor(freq, 1000000);
449 }
450
451 /*****************************************************************************
452 * Interrupt stuff
453 *****************************************************************************/
454
455 static irqreturn_t ppc7d_i8259_intr(int irq, void *dev_id, struct pt_regs *regs)
456 {
457 u32 temp = mv64x60_read(&bh, MV64x60_GPP_INTR_CAUSE);
458 if (temp & (1 << 28)) {
459 i8259_irq(regs);
460 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, temp & (~(1 << 28)));
461 return IRQ_HANDLED;
462 }
463
464 return IRQ_NONE;
465 }
466
467 /*
468 * Each interrupt cause is assigned an IRQ number.
469 * Southbridge has 16*2 (two 8259's) interrupts.
470 * Discovery-II has 96 interrupts (cause-hi, cause-lo, gpp x 32).
471 * If multiple interrupts are pending, get_irq() returns the
472 * lowest pending irq number first.
473 *
474 *
475 * IRQ # Source Trig Active
476 * =============================================================
477 *
478 * Southbridge
479 * -----------
480 * IRQ # Source Trig
481 * =============================================================
482 * 0 ISA High Resolution Counter Edge
483 * 1 Keyboard Edge
484 * 2 Cascade From (IRQ 8-15) Edge
485 * 3 Com 2 (Uart 2) Edge
486 * 4 Com 1 (Uart 1) Edge
487 * 5 PCI Int D/AFIX IRQZ ID4 (2,7) Level
488 * 6 GPIO Level
489 * 7 LPT Edge
490 * 8 RTC Alarm Edge
491 * 9 PCI Int A/PMC 2/AFIX IRQW ID1 (2,0) Level
492 * 10 PCI Int B/PMC 1/AFIX IRQX ID2 (2,1) Level
493 * 11 USB2 Level
494 * 12 Mouse Edge
495 * 13 Reserved internally by Ali M1535+
496 * 14 PCI Int C/VME/AFIX IRQY ID3 (2,6) Level
497 * 15 COM 5/6 Level
498 *
499 * 16..112 Discovery-II...
500 *
501 * MPP28 Southbridge Edge High
502 *
503 *
504 * Interrupts are cascaded through to the Discovery-II.
505 *
506 * PCI ---
507 * \
508 * CPLD --> ALI1535 -------> DISCOVERY-II
509 * INTF MPP28
510 */
511 static void __init ppc7d_init_irq(void)
512 {
513 int irq;
514
515 pr_debug("%s\n", __FUNCTION__);
516 i8259_init(0, 0);
517 mv64360_init_irq();
518
519 /* IRQs 5,6,9,10,11,14,15 are level sensitive */
520 irq_desc[5].status |= IRQ_LEVEL;
521 irq_desc[6].status |= IRQ_LEVEL;
522 irq_desc[9].status |= IRQ_LEVEL;
523 irq_desc[10].status |= IRQ_LEVEL;
524 irq_desc[11].status |= IRQ_LEVEL;
525 irq_desc[14].status |= IRQ_LEVEL;
526 irq_desc[15].status |= IRQ_LEVEL;
527
528 /* GPP28 is edge triggered */
529 irq_desc[mv64360_irq_base + MV64x60_IRQ_GPP28].status &= ~IRQ_LEVEL;
530 }
531
532 static u32 ppc7d_irq_canonicalize(u32 irq)
533 {
534 if ((irq >= 16) && (irq < (16 + 96)))
535 irq -= 16;
536
537 return irq;
538 }
539
540 static int ppc7d_get_irq(struct pt_regs *regs)
541 {
542 int irq;
543
544 irq = mv64360_get_irq(regs);
545 if (irq == (mv64360_irq_base + MV64x60_IRQ_GPP28))
546 irq = i8259_irq(regs);
547 return irq;
548 }
549
550 /*
551 * 9 PCI Int A/PMC 2/AFIX IRQW ID1 (2,0) Level
552 * 10 PCI Int B/PMC 1/AFIX IRQX ID2 (2,1) Level
553 * 14 PCI Int C/VME/AFIX IRQY ID3 (2,6) Level
554 * 5 PCI Int D/AFIX IRQZ ID4 (2,7) Level
555 */
556 static int __init ppc7d_map_irq(struct pci_dev *dev, unsigned char idsel,
557 unsigned char pin)
558 {
559 static const char pci_irq_table[][4] =
560 /*
561 * PCI IDSEL/INTPIN->INTLINE
562 * A B C D
563 */
564 {
565 {10, 14, 5, 9}, /* IDSEL 10 - PMC2 / AFIX IRQW */
566 {9, 10, 14, 5}, /* IDSEL 11 - PMC1 / AFIX IRQX */
567 {5, 9, 10, 14}, /* IDSEL 12 - AFIX IRQY */
568 {14, 5, 9, 10}, /* IDSEL 13 - AFIX IRQZ */
569 };
570 const long min_idsel = 10, max_idsel = 14, irqs_per_slot = 4;
571
572 pr_debug("%s: %04x/%04x/%x: idsel=%hx pin=%hu\n", __FUNCTION__,
573 dev->vendor, dev->device, PCI_FUNC(dev->devfn), idsel, pin);
574
575 return PCI_IRQ_TABLE_LOOKUP;
576 }
577
578 void __init ppc7d_intr_setup(void)
579 {
580 u32 data;
581
582 /*
583 * Define GPP 28 interrupt polarity as active high
584 * input signal and level triggered
585 */
586 data = mv64x60_read(&bh, MV64x60_GPP_LEVEL_CNTL);
587 data &= ~(1 << 28);
588 mv64x60_write(&bh, MV64x60_GPP_LEVEL_CNTL, data);
589 data = mv64x60_read(&bh, MV64x60_GPP_IO_CNTL);
590 data &= ~(1 << 28);
591 mv64x60_write(&bh, MV64x60_GPP_IO_CNTL, data);
592
593 /* Config GPP intr ctlr to respond to level trigger */
594 data = mv64x60_read(&bh, MV64x60_COMM_ARBITER_CNTL);
595 data |= (1 << 10);
596 mv64x60_write(&bh, MV64x60_COMM_ARBITER_CNTL, data);
597
598 /* XXXX Erranum FEr PCI-#8 */
599 data = mv64x60_read(&bh, MV64x60_PCI0_CMD);
600 data &= ~((1 << 5) | (1 << 9));
601 mv64x60_write(&bh, MV64x60_PCI0_CMD, data);
602 data = mv64x60_read(&bh, MV64x60_PCI1_CMD);
603 data &= ~((1 << 5) | (1 << 9));
604 mv64x60_write(&bh, MV64x60_PCI1_CMD, data);
605
606 /*
607 * Dismiss and then enable interrupt on GPP interrupt cause
608 * for CPU #0
609 */
610 mv64x60_write(&bh, MV64x60_GPP_INTR_CAUSE, ~(1 << 28));
611 data = mv64x60_read(&bh, MV64x60_GPP_INTR_MASK);
612 data |= (1 << 28);
613 mv64x60_write(&bh, MV64x60_GPP_INTR_MASK, data);
614
615 /*
616 * Dismiss and then enable interrupt on CPU #0 high cause reg
617 * BIT27 summarizes GPP interrupts 23-31
618 */
619 mv64x60_write(&bh, MV64360_IC_MAIN_CAUSE_HI, ~(1 << 27));
620 data = mv64x60_read(&bh, MV64360_IC_CPU0_INTR_MASK_HI);
621 data |= (1 << 27);
622 mv64x60_write(&bh, MV64360_IC_CPU0_INTR_MASK_HI, data);
623 }
624
625 /*****************************************************************************
626 * Platform device data fixup routines.
627 *****************************************************************************/
628
629 #if defined(CONFIG_SERIAL_MPSC)
630 static void __init ppc7d_fixup_mpsc_pdata(struct platform_device *pdev)
631 {
632 struct mpsc_pdata *pdata;
633
634 pdata = (struct mpsc_pdata *)pdev->dev.platform_data;
635
636 pdata->max_idle = 40;
637 pdata->default_baud = PPC7D_DEFAULT_BAUD;
638 pdata->brg_clk_src = PPC7D_MPSC_CLK_SRC;
639 pdata->brg_clk_freq = PPC7D_MPSC_CLK_FREQ;
640
641 return;
642 }
643 #endif
644
645 #if defined(CONFIG_MV643XX_ETH)
646 static void __init ppc7d_fixup_eth_pdata(struct platform_device *pdev)
647 {
648 struct mv643xx_eth_platform_data *eth_pd;
649 static u16 phy_addr[] = {
650 PPC7D_ETH0_PHY_ADDR,
651 PPC7D_ETH1_PHY_ADDR,
652 PPC7D_ETH2_PHY_ADDR,
653 };
654 int i;
655
656 eth_pd = pdev->dev.platform_data;
657 eth_pd->force_phy_addr = 1;
658 eth_pd->phy_addr = phy_addr[pdev->id];
659 eth_pd->tx_queue_size = PPC7D_ETH_TX_QUEUE_SIZE;
660 eth_pd->rx_queue_size = PPC7D_ETH_RX_QUEUE_SIZE;
661
662 /* Adjust IRQ by mv64360_irq_base */
663 for (i = 0; i < pdev->num_resources; i++) {
664 struct resource *r = &pdev->resource[i];
665
666 if (r->flags & IORESOURCE_IRQ) {
667 r->start += mv64360_irq_base;
668 r->end += mv64360_irq_base;
669 pr_debug("%s, uses IRQ %d\n", pdev->name,
670 (int)r->start);
671 }
672 }
673
674 }
675 #endif
676
677 #if defined(CONFIG_I2C_MV64XXX)
678 static void __init
679 ppc7d_fixup_i2c_pdata(struct platform_device *pdev)
680 {
681 struct mv64xxx_i2c_pdata *pdata;
682 int i;
683
684 pdata = pdev->dev.platform_data;
685 if (pdata == NULL) {
686 pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
687 if (pdata == NULL)
688 return;
689
690 pdev->dev.platform_data = pdata;
691 }
692
693 /* divisors M=8, N=3 for 100kHz I2C from 133MHz system clock */
694 pdata->freq_m = 8;
695 pdata->freq_n = 3;
696 pdata->timeout = 500;
697 pdata->retries = 3;
698
699 /* Adjust IRQ by mv64360_irq_base */
700 for (i = 0; i < pdev->num_resources; i++) {
701 struct resource *r = &pdev->resource[i];
702
703 if (r->flags & IORESOURCE_IRQ) {
704 r->start += mv64360_irq_base;
705 r->end += mv64360_irq_base;
706 pr_debug("%s, uses IRQ %d\n", pdev->name, (int) r->start);
707 }
708 }
709 }
710 #endif
711
712 static int ppc7d_platform_notify(struct device *dev)
713 {
714 static struct {
715 char *bus_id;
716 void ((*rtn) (struct platform_device * pdev));
717 } dev_map[] = {
718 #if defined(CONFIG_SERIAL_MPSC)
719 { MPSC_CTLR_NAME ".0", ppc7d_fixup_mpsc_pdata },
720 { MPSC_CTLR_NAME ".1", ppc7d_fixup_mpsc_pdata },
721 #endif
722 #if defined(CONFIG_MV643XX_ETH)
723 { MV643XX_ETH_NAME ".0", ppc7d_fixup_eth_pdata },
724 { MV643XX_ETH_NAME ".1", ppc7d_fixup_eth_pdata },
725 { MV643XX_ETH_NAME ".2", ppc7d_fixup_eth_pdata },
726 #endif
727 #if defined(CONFIG_I2C_MV64XXX)
728 { MV64XXX_I2C_CTLR_NAME ".0", ppc7d_fixup_i2c_pdata },
729 #endif
730 };
731 struct platform_device *pdev;
732 int i;
733
734 if (dev && dev->bus_id)
735 for (i = 0; i < ARRAY_SIZE(dev_map); i++)
736 if (!strncmp(dev->bus_id, dev_map[i].bus_id,
737 BUS_ID_SIZE)) {
738
739 pdev = container_of(dev,
740 struct platform_device,
741 dev);
742 dev_map[i].rtn(pdev);
743 }
744
745 return 0;
746 }
747
748 /*****************************************************************************
749 * PCI device fixups.
750 * These aren't really fixups per se. They are used to init devices as they
751 * are found during PCI scan.
752 *
753 * The PPC7D has an HB8 PCI-X bridge which must be set up during a PCI
754 * scan in order to find other devices on its secondary side.
755 *****************************************************************************/
756
757 static void __init ppc7d_fixup_hb8(struct pci_dev *dev)
758 {
759 u16 val16;
760
761 if (dev->bus->number == 0) {
762 pr_debug("PCI: HB8 init\n");
763
764 pci_write_config_byte(dev, 0x1c,
765 ((PPC7D_PCI0_IO_START_PCI_ADDR & 0xf000)
766 >> 8) | 0x01);
767 pci_write_config_byte(dev, 0x1d,
768 (((PPC7D_PCI0_IO_START_PCI_ADDR +
769 PPC7D_PCI0_IO_SIZE -
770 1) & 0xf000) >> 8) | 0x01);
771 pci_write_config_word(dev, 0x30,
772 PPC7D_PCI0_IO_START_PCI_ADDR >> 16);
773 pci_write_config_word(dev, 0x32,
774 ((PPC7D_PCI0_IO_START_PCI_ADDR +
775 PPC7D_PCI0_IO_SIZE -
776 1) >> 16) & 0xffff);
777
778 pci_write_config_word(dev, 0x20,
779 PPC7D_PCI0_MEM0_START_PCI_LO_ADDR >> 16);
780 pci_write_config_word(dev, 0x22,
781 ((PPC7D_PCI0_MEM0_START_PCI_LO_ADDR +
782 PPC7D_PCI0_MEM0_SIZE -
783 1) >> 16) & 0xffff);
784 pci_write_config_word(dev, 0x24, 0);
785 pci_write_config_word(dev, 0x26, 0);
786 pci_write_config_dword(dev, 0x28, 0);
787 pci_write_config_dword(dev, 0x2c, 0);
788
789 pci_read_config_word(dev, 0x3e, &val16);
790 val16 |= ((1 << 5) | (1 << 1)); /* signal master aborts and
791 * SERR to primary
792 */
793 val16 &= ~(1 << 2); /* ISA disable, so all ISA
794 * ports forwarded to secondary
795 */
796 pci_write_config_word(dev, 0x3e, val16);
797 }
798 }
799
800 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0028, ppc7d_fixup_hb8);
801
802 /* This should perhaps be a separate driver as we're actually initializing
803 * the chip for this board here. It's hardly a fixup...
804 */
805 static void __init ppc7d_fixup_ali1535(struct pci_dev *dev)
806 {
807 pr_debug("PCI: ALI1535 init\n");
808
809 if (dev->bus->number == 1) {
810 /* Configure the ISA Port Settings */
811 pci_write_config_byte(dev, 0x43, 0x00);
812
813 /* Disable PCI Interrupt polling mode */
814 pci_write_config_byte(dev, 0x45, 0x00);
815
816 /* Multifunction pin select INTFJ -> INTF */
817 pci_write_config_byte(dev, 0x78, 0x00);
818
819 /* Set PCI INT -> IRQ Routing control in for external
820 * pins south bridge.
821 */
822 pci_write_config_byte(dev, 0x48, 0x31); /* [7-4] INT B -> IRQ10
823 * [3-0] INT A -> IRQ9
824 */
825 pci_write_config_byte(dev, 0x49, 0x5D); /* [7-4] INT D -> IRQ5
826 * [3-0] INT C -> IRQ14
827 */
828
829 /* PPC7D setup */
830 /* NEC USB device on IRQ 11 (INTE) - INTF disabled */
831 pci_write_config_byte(dev, 0x4A, 0x09);
832
833 /* GPIO on IRQ 6 */
834 pci_write_config_byte(dev, 0x76, 0x07);
835
836 /* SIRQ I (COMS 5/6) use IRQ line 15.
837 * Positive (not subtractive) address decode.
838 */
839 pci_write_config_byte(dev, 0x44, 0x0f);
840
841 /* SIRQ II disabled */
842 pci_write_config_byte(dev, 0x75, 0x0);
843
844 /* On board USB and RTC disabled */
845 pci_write_config_word(dev, 0x52, (1 << 14));
846 pci_write_config_byte(dev, 0x74, 0x00);
847
848 /* On board IDE disabled */
849 pci_write_config_byte(dev, 0x58, 0x00);
850
851 /* Decode 32-bit addresses */
852 pci_write_config_byte(dev, 0x5b, 0);
853
854 /* Disable docking IO */
855 pci_write_config_word(dev, 0x5c, 0x0000);
856
857 /* Disable modem, enable sound */
858 pci_write_config_byte(dev, 0x77, (1 << 6));
859
860 /* Disable hot-docking mode */
861 pci_write_config_byte(dev, 0x7d, 0x00);
862 }
863 }
864
865 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, 0x1533, ppc7d_fixup_ali1535);
866
867 static int ppc7d_pci_exclude_device(u8 bus, u8 devfn)
868 {
869 /* Early versions of this board were fitted with IBM ALMA
870 * PCI-VME bridge chips. The PCI config space of these devices
871 * was not set up correctly and causes PCI scan problems.
872 */
873 if ((bus == 1) && (PCI_SLOT(devfn) == 4) && ppc7d_has_alma)
874 return PCIBIOS_DEVICE_NOT_FOUND;
875
876 return mv64x60_pci_exclude_device(bus, devfn);
877 }
878
879 /* This hook is called when each PCI bus is probed.
880 */
881 static void ppc7d_pci_fixup_bus(struct pci_bus *bus)
882 {
883 pr_debug("PCI BUS %hu: %lx/%lx %lx/%lx %lx/%lx %lx/%lx\n",
884 bus->number,
885 bus->resource[0] ? bus->resource[0]->start : 0,
886 bus->resource[0] ? bus->resource[0]->end : 0,
887 bus->resource[1] ? bus->resource[1]->start : 0,
888 bus->resource[1] ? bus->resource[1]->end : 0,
889 bus->resource[2] ? bus->resource[2]->start : 0,
890 bus->resource[2] ? bus->resource[2]->end : 0,
891 bus->resource[3] ? bus->resource[3]->start : 0,
892 bus->resource[3] ? bus->resource[3]->end : 0);
893
894 if ((bus->number == 1) && (bus->resource[2] != NULL)) {
895 /* Hide PCI window 2 of Bus 1 which is used only to
896 * map legacy ISA memory space.
897 */
898 bus->resource[2]->start = 0;
899 bus->resource[2]->end = 0;
900 bus->resource[2]->flags = 0;
901 }
902 }
903
904 /*****************************************************************************
905 * Board device setup code
906 *****************************************************************************/
907
908 void __init ppc7d_setup_peripherals(void)
909 {
910 u32 val32;
911
912 /* Set up windows for boot CS */
913 mv64x60_set_32bit_window(&bh, MV64x60_CPU2BOOT_WIN,
914 PPC7D_BOOT_WINDOW_BASE, PPC7D_BOOT_WINDOW_SIZE,
915 0);
916 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2BOOT_WIN);
917
918 /* Boot firmware configures the following DevCS addresses.
919 * DevCS0 - board control/status
920 * DevCS1 - test registers
921 * DevCS2 - AFIX port/address registers (for identifying)
922 * DevCS3 - FLASH
923 *
924 * We don't use DevCS0, DevCS1.
925 */
926 val32 = mv64x60_read(&bh, MV64360_CPU_BAR_ENABLE);
927 val32 |= ((1 << 4) | (1 << 5));
928 mv64x60_write(&bh, MV64360_CPU_BAR_ENABLE, val32);
929 mv64x60_write(&bh, MV64x60_CPU2DEV_0_BASE, 0);
930 mv64x60_write(&bh, MV64x60_CPU2DEV_0_SIZE, 0);
931 mv64x60_write(&bh, MV64x60_CPU2DEV_1_BASE, 0);
932 mv64x60_write(&bh, MV64x60_CPU2DEV_1_SIZE, 0);
933
934 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_2_WIN,
935 PPC7D_AFIX_REG_BASE, PPC7D_AFIX_REG_SIZE, 0);
936 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_2_WIN);
937
938 mv64x60_set_32bit_window(&bh, MV64x60_CPU2DEV_3_WIN,
939 PPC7D_FLASH_BASE, PPC7D_FLASH_SIZE_ACTUAL, 0);
940 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2DEV_3_WIN);
941
942 mv64x60_set_32bit_window(&bh, MV64x60_CPU2SRAM_WIN,
943 PPC7D_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE,
944 0);
945 bh.ci->enable_window_32bit(&bh, MV64x60_CPU2SRAM_WIN);
946
947 /* Set up Enet->SRAM window */
948 mv64x60_set_32bit_window(&bh, MV64x60_ENET2MEM_4_WIN,
949 PPC7D_INTERNAL_SRAM_BASE, MV64360_SRAM_SIZE,
950 0x2);
951 bh.ci->enable_window_32bit(&bh, MV64x60_ENET2MEM_4_WIN);
952
953 /* Give enet r/w access to memory region */
954 val32 = mv64x60_read(&bh, MV64360_ENET2MEM_ACC_PROT_0);
955 val32 |= (0x3 << (4 << 1));
956 mv64x60_write(&bh, MV64360_ENET2MEM_ACC_PROT_0, val32);
957 val32 = mv64x60_read(&bh, MV64360_ENET2MEM_ACC_PROT_1);
958 val32 |= (0x3 << (4 << 1));
959 mv64x60_write(&bh, MV64360_ENET2MEM_ACC_PROT_1, val32);
960 val32 = mv64x60_read(&bh, MV64360_ENET2MEM_ACC_PROT_2);
961 val32 |= (0x3 << (4 << 1));
962 mv64x60_write(&bh, MV64360_ENET2MEM_ACC_PROT_2, val32);
963
964 val32 = mv64x60_read(&bh, MV64x60_TIMR_CNTR_0_3_CNTL);
965 val32 &= ~((1 << 0) | (1 << 8) | (1 << 16) | (1 << 24));
966 mv64x60_write(&bh, MV64x60_TIMR_CNTR_0_3_CNTL, val32);
967
968 /* Enumerate pci bus.
969 *
970 * We scan PCI#0 first (the bus with the HB8 and other
971 * on-board peripherals). We must configure the 64360 before
972 * each scan, according to the bus number assignments. Busses
973 * are assigned incrementally, starting at 0. PCI#0 is
974 * usually assigned bus#0, the secondary side of the HB8 gets
975 * bus#1 and PCI#1 (second PMC site) gets bus#2. However, if
976 * any PMC card has a PCI bridge, these bus assignments will
977 * change.
978 */
979
980 /* Turn off PCI retries */
981 val32 = mv64x60_read(&bh, MV64x60_CPU_CONFIG);
982 val32 |= (1 << 17);
983 mv64x60_write(&bh, MV64x60_CPU_CONFIG, val32);
984
985 /* Scan PCI#0 */
986 mv64x60_set_bus(&bh, 0, 0);
987 bh.hose_a->first_busno = 0;
988 bh.hose_a->last_busno = 0xff;
989 bh.hose_a->last_busno = pciauto_bus_scan(bh.hose_a, 0);
990 printk(KERN_INFO "PCI#0: first=%d last=%d\n",
991 bh.hose_a->first_busno, bh.hose_a->last_busno);
992
993 /* Scan PCI#1 */
994 bh.hose_b->first_busno = bh.hose_a->last_busno + 1;
995 mv64x60_set_bus(&bh, 1, bh.hose_b->first_busno);
996 bh.hose_b->last_busno = 0xff;
997 bh.hose_b->last_busno = pciauto_bus_scan(bh.hose_b,
998 bh.hose_b->first_busno);
999 printk(KERN_INFO "PCI#1: first=%d last=%d\n",
1000 bh.hose_b->first_busno, bh.hose_b->last_busno);
1001
1002 /* Turn on PCI retries */
1003 val32 = mv64x60_read(&bh, MV64x60_CPU_CONFIG);
1004 val32 &= ~(1 << 17);
1005 mv64x60_write(&bh, MV64x60_CPU_CONFIG, val32);
1006
1007 /* Setup interrupts */
1008 ppc7d_intr_setup();
1009 }
1010
1011 static void __init ppc7d_setup_bridge(void)
1012 {
1013 struct mv64x60_setup_info si;
1014 int i;
1015 u32 temp;
1016
1017 mv64360_irq_base = 16; /* first 16 intrs are 2 x 8259's */
1018
1019 memset(&si, 0, sizeof(si));
1020
1021 si.phys_reg_base = CONFIG_MV64X60_NEW_BASE;
1022
1023 si.pci_0.enable_bus = 1;
1024 si.pci_0.pci_io.cpu_base = PPC7D_PCI0_IO_START_PROC_ADDR;
1025 si.pci_0.pci_io.pci_base_hi = 0;
1026 si.pci_0.pci_io.pci_base_lo = PPC7D_PCI0_IO_START_PCI_ADDR;
1027 si.pci_0.pci_io.size = PPC7D_PCI0_IO_SIZE;
1028 si.pci_0.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
1029 si.pci_0.pci_mem[0].cpu_base = PPC7D_PCI0_MEM0_START_PROC_ADDR;
1030 si.pci_0.pci_mem[0].pci_base_hi = PPC7D_PCI0_MEM0_START_PCI_HI_ADDR;
1031 si.pci_0.pci_mem[0].pci_base_lo = PPC7D_PCI0_MEM0_START_PCI_LO_ADDR;
1032 si.pci_0.pci_mem[0].size = PPC7D_PCI0_MEM0_SIZE;
1033 si.pci_0.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
1034 si.pci_0.pci_mem[1].cpu_base = PPC7D_PCI0_MEM1_START_PROC_ADDR;
1035 si.pci_0.pci_mem[1].pci_base_hi = PPC7D_PCI0_MEM1_START_PCI_HI_ADDR;
1036 si.pci_0.pci_mem[1].pci_base_lo = PPC7D_PCI0_MEM1_START_PCI_LO_ADDR;
1037 si.pci_0.pci_mem[1].size = PPC7D_PCI0_MEM1_SIZE;
1038 si.pci_0.pci_mem[1].swap = MV64x60_CPU2PCI_SWAP_NONE;
1039 si.pci_0.pci_cmd_bits = 0;
1040 si.pci_0.latency_timer = 0x80;
1041
1042 si.pci_1.enable_bus = 1;
1043 si.pci_1.pci_io.cpu_base = PPC7D_PCI1_IO_START_PROC_ADDR;
1044 si.pci_1.pci_io.pci_base_hi = 0;
1045 si.pci_1.pci_io.pci_base_lo = PPC7D_PCI1_IO_START_PCI_ADDR;
1046 si.pci_1.pci_io.size = PPC7D_PCI1_IO_SIZE;
1047 si.pci_1.pci_io.swap = MV64x60_CPU2PCI_SWAP_NONE;
1048 si.pci_1.pci_mem[0].cpu_base = PPC7D_PCI1_MEM0_START_PROC_ADDR;
1049 si.pci_1.pci_mem[0].pci_base_hi = PPC7D_PCI1_MEM0_START_PCI_HI_ADDR;
1050 si.pci_1.pci_mem[0].pci_base_lo = PPC7D_PCI1_MEM0_START_PCI_LO_ADDR;
1051 si.pci_1.pci_mem[0].size = PPC7D_PCI1_MEM0_SIZE;
1052 si.pci_1.pci_mem[0].swap = MV64x60_CPU2PCI_SWAP_NONE;
1053 si.pci_1.pci_mem[1].cpu_base = PPC7D_PCI1_MEM1_START_PROC_ADDR;
1054 si.pci_1.pci_mem[1].pci_base_hi = PPC7D_PCI1_MEM1_START_PCI_HI_ADDR;
1055 si.pci_1.pci_mem[1].pci_base_lo = PPC7D_PCI1_MEM1_START_PCI_LO_ADDR;
1056 si.pci_1.pci_mem[1].size = PPC7D_PCI1_MEM1_SIZE;
1057 si.pci_1.pci_mem[1].swap = MV64x60_CPU2PCI_SWAP_NONE;
1058 si.pci_1.pci_cmd_bits = 0;
1059 si.pci_1.latency_timer = 0x80;
1060
1061 /* Don't clear the SRAM window since we use it for debug */
1062 si.window_preserve_mask_32_lo = (1 << MV64x60_CPU2SRAM_WIN);
1063
1064 printk(KERN_INFO "PCI: MV64360 PCI#0 IO at %x, size %x\n",
1065 si.pci_0.pci_io.cpu_base, si.pci_0.pci_io.size);
1066 printk(KERN_INFO "PCI: MV64360 PCI#1 IO at %x, size %x\n",
1067 si.pci_1.pci_io.cpu_base, si.pci_1.pci_io.size);
1068
1069 for (i = 0; i < MV64x60_CPU2MEM_WINDOWS; i++) {
1070 #if defined(CONFIG_NOT_COHERENT_CACHE)
1071 si.cpu_prot_options[i] = 0;
1072 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_NONE;
1073 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_NONE;
1074 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_NONE;
1075
1076 si.pci_0.acc_cntl_options[i] =
1077 MV64360_PCI_ACC_CNTL_SNOOP_NONE |
1078 MV64360_PCI_ACC_CNTL_SWAP_NONE |
1079 MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
1080 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
1081
1082 si.pci_1.acc_cntl_options[i] =
1083 MV64360_PCI_ACC_CNTL_SNOOP_NONE |
1084 MV64360_PCI_ACC_CNTL_SWAP_NONE |
1085 MV64360_PCI_ACC_CNTL_MBURST_128_BYTES |
1086 MV64360_PCI_ACC_CNTL_RDSIZE_256_BYTES;
1087 #else
1088 si.cpu_prot_options[i] = 0;
1089 /* All PPC7D hardware uses B0 or newer MV64360 silicon which
1090 * does not have snoop bugs.
1091 */
1092 si.enet_options[i] = MV64360_ENET2MEM_SNOOP_WB;
1093 si.mpsc_options[i] = MV64360_MPSC2MEM_SNOOP_WB;
1094 si.idma_options[i] = MV64360_IDMA2MEM_SNOOP_WB;
1095
1096 si.pci_0.acc_cntl_options[i] =
1097 MV64360_PCI_ACC_CNTL_SNOOP_WB |
1098 MV64360_PCI_ACC_CNTL_SWAP_NONE |
1099 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
1100 MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
1101
1102 si.pci_1.acc_cntl_options[i] =
1103 MV64360_PCI_ACC_CNTL_SNOOP_WB |
1104 MV64360_PCI_ACC_CNTL_SWAP_NONE |
1105 MV64360_PCI_ACC_CNTL_MBURST_32_BYTES |
1106 MV64360_PCI_ACC_CNTL_RDSIZE_32_BYTES;
1107 #endif
1108 }
1109
1110 /* Lookup PCI host bridges */
1111 if (mv64x60_init(&bh, &si))
1112 printk(KERN_ERR "MV64360 initialization failed.\n");
1113
1114 pr_debug("MV64360 regs @ %lx/%p\n", bh.p_base, bh.v_base);
1115
1116 /* Enable WB Cache coherency on SRAM */
1117 temp = mv64x60_read(&bh, MV64360_SRAM_CONFIG);
1118 pr_debug("SRAM_CONFIG: %x\n", temp);
1119 #if defined(CONFIG_NOT_COHERENT_CACHE)
1120 mv64x60_write(&bh, MV64360_SRAM_CONFIG, temp & ~0x2);
1121 #else
1122 mv64x60_write(&bh, MV64360_SRAM_CONFIG, temp | 0x2);
1123 #endif
1124 /* If system operates with internal bus arbiter (CPU master
1125 * control bit8) clear AACK Delay bit [25] in CPU
1126 * configuration register.
1127 */
1128 temp = mv64x60_read(&bh, MV64x60_CPU_MASTER_CNTL);
1129 if (temp & (1 << 8)) {
1130 temp = mv64x60_read(&bh, MV64x60_CPU_CONFIG);
1131 mv64x60_write(&bh, MV64x60_CPU_CONFIG, (temp & ~(1 << 25)));
1132 }
1133
1134 /* Data and address parity is enabled */
1135 temp = mv64x60_read(&bh, MV64x60_CPU_CONFIG);
1136 mv64x60_write(&bh, MV64x60_CPU_CONFIG,
1137 (temp | (1 << 26) | (1 << 19)));
1138
1139 pci_dram_offset = 0; /* sys mem at same addr on PCI & cpu bus */
1140 ppc_md.pci_swizzle = common_swizzle;
1141 ppc_md.pci_map_irq = ppc7d_map_irq;
1142 ppc_md.pci_exclude_device = ppc7d_pci_exclude_device;
1143
1144 mv64x60_set_bus(&bh, 0, 0);
1145 bh.hose_a->first_busno = 0;
1146 bh.hose_a->last_busno = 0xff;
1147 bh.hose_a->mem_space.start = PPC7D_PCI0_MEM0_START_PCI_LO_ADDR;
1148 bh.hose_a->mem_space.end =
1149 PPC7D_PCI0_MEM0_START_PCI_LO_ADDR + PPC7D_PCI0_MEM0_SIZE;
1150
1151 /* These will be set later, as a result of PCI0 scan */
1152 bh.hose_b->first_busno = 0;
1153 bh.hose_b->last_busno = 0xff;
1154 bh.hose_b->mem_space.start = PPC7D_PCI1_MEM0_START_PCI_LO_ADDR;
1155 bh.hose_b->mem_space.end =
1156 PPC7D_PCI1_MEM0_START_PCI_LO_ADDR + PPC7D_PCI1_MEM0_SIZE;
1157
1158 pr_debug("MV64360: PCI#0 IO decode %08x/%08x IO remap %08x\n",
1159 mv64x60_read(&bh, 0x48), mv64x60_read(&bh, 0x50),
1160 mv64x60_read(&bh, 0xf0));
1161 }
1162
1163 static void __init ppc7d_setup_arch(void)
1164 {
1165 int port;
1166
1167 loops_per_jiffy = 100000000 / HZ;
1168
1169 #ifdef CONFIG_BLK_DEV_INITRD
1170 if (initrd_start)
1171 ROOT_DEV = Root_RAM0;
1172 else
1173 #endif
1174 #ifdef CONFIG_ROOT_NFS
1175 ROOT_DEV = Root_NFS;
1176 #else
1177 ROOT_DEV = Root_HDA1;
1178 #endif
1179
1180 if ((cur_cpu_spec->cpu_features & CPU_FTR_SPEC7450) ||
1181 (cur_cpu_spec->cpu_features & CPU_FTR_L3CR))
1182 /* 745x is different. We only want to pass along enable. */
1183 _set_L2CR(L2CR_L2E);
1184 else if (cur_cpu_spec->cpu_features & CPU_FTR_L2CR)
1185 /* All modules have 1MB of L2. We also assume that an
1186 * L2 divisor of 3 will work.
1187 */
1188 _set_L2CR(L2CR_L2E | L2CR_L2SIZ_1MB | L2CR_L2CLK_DIV3
1189 | L2CR_L2RAM_PIPE | L2CR_L2OH_1_0 | L2CR_L2DF);
1190
1191 if (cur_cpu_spec->cpu_features & CPU_FTR_L3CR)
1192 /* No L3 cache */
1193 _set_L3CR(0);
1194
1195 #ifdef CONFIG_DUMMY_CONSOLE
1196 conswitchp = &dummy_con;
1197 #endif
1198
1199 /* Lookup PCI host bridges */
1200 if (ppc_md.progress)
1201 ppc_md.progress("ppc7d_setup_arch: calling setup_bridge", 0);
1202
1203 ppc7d_setup_bridge();
1204 ppc7d_setup_peripherals();
1205
1206 /* Disable ethernet. It might have been setup by the bootrom */
1207 for (port = 0; port < 3; port++)
1208 mv64x60_write(&bh, MV643XX_ETH_RECEIVE_QUEUE_COMMAND_REG(port),
1209 0x0000ff00);
1210
1211 /* Clear queue pointers to ensure they are all initialized,
1212 * otherwise since queues 1-7 are unused, they have random
1213 * pointers which look strange in register dumps. Don't bother
1214 * with queue 0 since it will be initialized later.
1215 */
1216 for (port = 0; port < 3; port++) {
1217 mv64x60_write(&bh,
1218 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_1(port),
1219 0x00000000);
1220 mv64x60_write(&bh,
1221 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_2(port),
1222 0x00000000);
1223 mv64x60_write(&bh,
1224 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_3(port),
1225 0x00000000);
1226 mv64x60_write(&bh,
1227 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_4(port),
1228 0x00000000);
1229 mv64x60_write(&bh,
1230 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_5(port),
1231 0x00000000);
1232 mv64x60_write(&bh,
1233 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_6(port),
1234 0x00000000);
1235 mv64x60_write(&bh,
1236 MV643XX_ETH_RX_CURRENT_QUEUE_DESC_PTR_7(port),
1237 0x00000000);
1238 }
1239
1240 printk(KERN_INFO "Radstone Technology PPC7D\n");
1241 if (ppc_md.progress)
1242 ppc_md.progress("ppc7d_setup_arch: exit", 0);
1243
1244 }
1245
1246 /* Real Time Clock support.
1247 * PPC7D has a DS1337 accessed by I2C.
1248 */
1249 static ulong ppc7d_get_rtc_time(void)
1250 {
1251 struct rtc_time tm;
1252 int result;
1253
1254 spin_lock(&rtc_lock);
1255 result = ds1337_do_command(0, DS1337_GET_DATE, &tm);
1256 spin_unlock(&rtc_lock);
1257
1258 if (result == 0)
1259 result = mktime(tm.tm_year, tm.tm_mon, tm.tm_mday, tm.tm_hour, tm.tm_min, tm.tm_sec);
1260
1261 return result;
1262 }
1263
1264 static int ppc7d_set_rtc_time(unsigned long nowtime)
1265 {
1266 struct rtc_time tm;
1267 int result;
1268
1269 spin_lock(&rtc_lock);
1270 to_tm(nowtime, &tm);
1271 result = ds1337_do_command(0, DS1337_SET_DATE, &tm);
1272 spin_unlock(&rtc_lock);
1273
1274 return result;
1275 }
1276
1277 /* This kernel command line parameter can be used to have the target
1278 * wait for a JTAG debugger to attach. Of course, a JTAG debugger
1279 * with hardware breakpoint support can have the target stop at any
1280 * location during init, but this is a convenience feature that makes
1281 * it easier in the common case of loading the code using the ppcboot
1282 * bootloader..
1283 */
1284 static unsigned long ppc7d_wait_debugger;
1285
1286 static int __init ppc7d_waitdbg(char *str)
1287 {
1288 ppc7d_wait_debugger = 1;
1289 return 1;
1290 }
1291
1292 __setup("waitdbg", ppc7d_waitdbg);
1293
1294 /* Second phase board init, called after other (architecture common)
1295 * low-level services have been initialized.
1296 */
1297 static void ppc7d_init2(void)
1298 {
1299 unsigned long flags;
1300 u32 data;
1301 u8 data8;
1302
1303 pr_debug("%s: enter\n", __FUNCTION__);
1304
1305 /* Wait for debugger? */
1306 if (ppc7d_wait_debugger) {
1307 printk("Waiting for debugger...\n");
1308
1309 while (readl(&ppc7d_wait_debugger)) ;
1310 }
1311
1312 /* Hook up i8259 interrupt which is connected to GPP28 */
1313 request_irq(mv64360_irq_base + MV64x60_IRQ_GPP28, ppc7d_i8259_intr,
1314 SA_INTERRUPT, "I8259 (GPP28) interrupt", (void *)0);
1315
1316 /* Configure MPP16 as watchdog NMI, MPP17 as watchdog WDE */
1317 spin_lock_irqsave(&mv64x60_lock, flags);
1318 data = mv64x60_read(&bh, MV64x60_MPP_CNTL_2);
1319 data &= ~(0x0000000f << 0);
1320 data |= (0x00000004 << 0);
1321 data &= ~(0x0000000f << 4);
1322 data |= (0x00000004 << 4);
1323 mv64x60_write(&bh, MV64x60_MPP_CNTL_2, data);
1324 spin_unlock_irqrestore(&mv64x60_lock, flags);
1325
1326 /* All LEDs off */
1327 data8 = inb(PPC7D_CPLD_LEDS);
1328 data8 &= ~0x08;
1329 data8 |= 0x07;
1330 outb(data8, PPC7D_CPLD_LEDS);
1331
1332 /* Hook up RTC. We couldn't do this earlier because we need the I2C subsystem */
1333 ppc_md.set_rtc_time = ppc7d_set_rtc_time;
1334 ppc_md.get_rtc_time = ppc7d_get_rtc_time;
1335
1336 pr_debug("%s: exit\n", __FUNCTION__);
1337 }
1338
1339 /* Called from machine_init(), early, before any of the __init functions
1340 * have run. We must init software-configurable pins before other functions
1341 * such as interrupt controllers are initialised.
1342 */
1343 void __init platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
1344 unsigned long r6, unsigned long r7)
1345 {
1346 u8 val8;
1347 u8 rev_num;
1348
1349 /* Map 0xe0000000-0xffffffff early because we need access to SRAM
1350 * and the ISA memory space (for serial port) here. This mapping
1351 * is redone properly in ppc7d_map_io() later.
1352 */
1353 mtspr(SPRN_DBAT3U, 0xe0003fff);
1354 mtspr(SPRN_DBAT3L, 0xe000002a);
1355
1356 /*
1357 * Zero SRAM. Note that this generates parity errors on
1358 * internal data path in SRAM if it's first time accessing it
1359 * after reset.
1360 *
1361 * We do this ASAP to avoid parity errors when reading
1362 * uninitialized SRAM.
1363 */
1364 memset((void *)PPC7D_INTERNAL_SRAM_BASE, 0, MV64360_SRAM_SIZE);
1365
1366 pr_debug("platform_init: r3-r7: %lx %lx %lx %lx %lx\n",
1367 r3, r4, r5, r6, r7);
1368
1369 parse_bootinfo(find_bootinfo());
1370
1371 /* ASSUMPTION: If both r3 (bd_t pointer) and r6 (cmdline pointer)
1372 * are non-zero, then we should use the board info from the bd_t
1373 * structure and the cmdline pointed to by r6 instead of the
1374 * information from birecs, if any. Otherwise, use the information
1375 * from birecs as discovered by the preceeding call to
1376 * parse_bootinfo(). This rule should work with both PPCBoot, which
1377 * uses a bd_t board info structure, and the kernel boot wrapper,
1378 * which uses birecs.
1379 */
1380 if (r3 && r6) {
1381 bd_t *bp = (bd_t *) __res;
1382
1383 /* copy board info structure */
1384 memcpy((void *)__res, (void *)(r3 + KERNELBASE), sizeof(bd_t));
1385 /* copy command line */
1386 *(char *)(r7 + KERNELBASE) = 0;
1387 strcpy(cmd_line, (char *)(r6 + KERNELBASE));
1388
1389 printk(KERN_INFO "Board info data:-\n");
1390 printk(KERN_INFO " Internal freq: %lu MHz, bus freq: %lu MHz\n",
1391 bp->bi_intfreq, bp->bi_busfreq);
1392 printk(KERN_INFO " Memory: %lx, size %lx\n", bp->bi_memstart,
1393 bp->bi_memsize);
1394 printk(KERN_INFO " Console baudrate: %lu\n", bp->bi_baudrate);
1395 printk(KERN_INFO " Ethernet address: "
1396 "%02x:%02x:%02x:%02x:%02x:%02x\n",
1397 bp->bi_enetaddr[0], bp->bi_enetaddr[1],
1398 bp->bi_enetaddr[2], bp->bi_enetaddr[3],
1399 bp->bi_enetaddr[4], bp->bi_enetaddr[5]);
1400 }
1401 #ifdef CONFIG_BLK_DEV_INITRD
1402 /* take care of initrd if we have one */
1403 if (r4) {
1404 initrd_start = r4 + KERNELBASE;
1405 initrd_end = r5 + KERNELBASE;
1406 printk(KERN_INFO "INITRD @ %lx/%lx\n", initrd_start, initrd_end);
1407 }
1408 #endif /* CONFIG_BLK_DEV_INITRD */
1409
1410 /* Map in board regs, etc. */
1411 isa_io_base = 0xe8000000;
1412 isa_mem_base = 0xe8000000;
1413 pci_dram_offset = 0x00000000;
1414 ISA_DMA_THRESHOLD = 0x00ffffff;
1415 DMA_MODE_READ = 0x44;
1416 DMA_MODE_WRITE = 0x48;
1417
1418 ppc_md.setup_arch = ppc7d_setup_arch;
1419 ppc_md.init = ppc7d_init2;
1420 ppc_md.show_cpuinfo = ppc7d_show_cpuinfo;
1421 /* XXX this is broken... */
1422 ppc_md.irq_canonicalize = ppc7d_irq_canonicalize;
1423 ppc_md.init_IRQ = ppc7d_init_irq;
1424 ppc_md.get_irq = ppc7d_get_irq;
1425
1426 ppc_md.restart = ppc7d_restart;
1427 ppc_md.power_off = ppc7d_power_off;
1428 ppc_md.halt = ppc7d_halt;
1429
1430 ppc_md.find_end_of_memory = ppc7d_find_end_of_memory;
1431 ppc_md.setup_io_mappings = ppc7d_map_io;
1432
1433 ppc_md.time_init = NULL;
1434 ppc_md.set_rtc_time = NULL;
1435 ppc_md.get_rtc_time = NULL;
1436 ppc_md.calibrate_decr = ppc7d_calibrate_decr;
1437 ppc_md.nvram_read_val = NULL;
1438 ppc_md.nvram_write_val = NULL;
1439
1440 ppc_md.heartbeat = ppc7d_heartbeat;
1441 ppc_md.heartbeat_reset = HZ;
1442 ppc_md.heartbeat_count = ppc_md.heartbeat_reset;
1443
1444 ppc_md.pcibios_fixup_bus = ppc7d_pci_fixup_bus;
1445
1446 #if defined(CONFIG_SERIAL_MPSC) || defined(CONFIG_MV643XX_ETH) || \
1447 defined(CONFIG_I2C_MV64XXX)
1448 platform_notify = ppc7d_platform_notify;
1449 #endif
1450
1451 #ifdef CONFIG_SERIAL_MPSC
1452 /* On PPC7D, we must configure MPSC support via CPLD control
1453 * registers.
1454 */
1455 outb(PPC7D_CPLD_RTS_COM4_SCLK |
1456 PPC7D_CPLD_RTS_COM56_ENABLED, PPC7D_CPLD_RTS);
1457 outb(PPC7D_CPLD_COMS_COM3_TCLKEN |
1458 PPC7D_CPLD_COMS_COM3_TXEN |
1459 PPC7D_CPLD_COMS_COM4_TCLKEN |
1460 PPC7D_CPLD_COMS_COM4_TXEN, PPC7D_CPLD_COMS);
1461 #endif /* CONFIG_SERIAL_MPSC */
1462
1463 #if defined(CONFIG_KGDB) || defined(CONFIG_SERIAL_TEXT_DEBUG)
1464 ppc7d_early_serial_map();
1465 #ifdef CONFIG_SERIAL_TEXT_DEBUG
1466 #if defined(CONFIG_SERIAL_MPSC_CONSOLE)
1467 ppc_md.progress = mv64x60_mpsc_progress;
1468 #elif defined(CONFIG_SERIAL_8250)
1469 ppc_md.progress = gen550_progress;
1470 #else
1471 #error CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG has no supported CONFIG_SERIAL_XXX
1472 #endif /* CONFIG_SERIAL_8250 */
1473 #endif /* CONFIG_SERIAL_TEXT_DEBUG */
1474 #endif /* CONFIG_KGDB || CONFIG_SERIAL_TEXT_DEBUG */
1475
1476 /* Enable write access to user flash. This is necessary for
1477 * flash probe.
1478 */
1479 val8 = readb((void *)isa_io_base + PPC7D_CPLD_SW_FLASH_WRITE_PROTECT);
1480 writeb(val8 | (PPC7D_CPLD_SW_FLASH_WRPROT_ENABLED &
1481 PPC7D_CPLD_SW_FLASH_WRPROT_USER_MASK),
1482 (void *)isa_io_base + PPC7D_CPLD_SW_FLASH_WRITE_PROTECT);
1483
1484 /* Determine if this board has IBM ALMA VME devices */
1485 val8 = readb((void *)isa_io_base + PPC7D_CPLD_BOARD_REVISION);
1486 rev_num = (val8 & PPC7D_CPLD_BOARD_REVISION_NUMBER_MASK) >> 5;
1487 if (rev_num <= 1)
1488 ppc7d_has_alma = 1;
1489
1490 #ifdef DEBUG
1491 console_printk[0] = 8;
1492 #endif
1493 }
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