2 * arch/ppc/kernel/setup.c
4 * Copyright (C) 1995 Linus Torvalds
5 * Adapted from 'alpha' version by Gary Thomas
6 * Modified by Cort Dougan (cort@cs.nmt.edu)
7 * Modified for MBX using prep/chrp/pmac functions by Dan (dmalek@jlc.net)
8 * Further modified for generic 8xx by Dan.
12 * bootup setup stuff..
15 #include <linux/config.h>
16 #include <linux/errno.h>
17 #include <linux/sched.h>
18 #include <linux/kernel.h>
20 #include <linux/stddef.h>
21 #include <linux/unistd.h>
22 #include <linux/ptrace.h>
23 #include <linux/slab.h>
24 #include <linux/user.h>
25 #include <linux/a.out.h>
26 #include <linux/tty.h>
27 #include <linux/major.h>
28 #include <linux/interrupt.h>
29 #include <linux/reboot.h>
30 #include <linux/init.h>
31 #include <linux/initrd.h>
32 #include <linux/ioport.h>
33 #include <linux/bootmem.h>
34 #include <linux/seq_file.h>
35 #include <linux/root_dev.h>
39 #include <asm/residual.h>
41 #include <asm/pgtable.h>
42 #include <asm/mpc8xx.h>
43 #include <asm/8xx_immap.h>
44 #include <asm/machdep.h>
45 #include <asm/bootinfo.h>
49 #include "ppc8xx_pic.h"
51 static int m8xx_set_rtc_time(unsigned long time
);
52 static unsigned long m8xx_get_rtc_time(void);
53 void m8xx_calibrate_decr(void);
55 unsigned char __res
[sizeof(bd_t
)];
57 extern void m8xx_ide_init(void);
59 extern unsigned long find_available_memory(void);
60 extern void m8xx_cpm_reset(void);
61 extern void m8xx_wdt_handler_install(bd_t
*bp
);
62 extern void rpxfb_alloc_pages(void);
63 extern void cpm_interrupt_init(void);
65 void __attribute__ ((weak
))
73 /* Reset the Communication Processor Module.
82 ROOT_DEV
= Root_HDA1
; /* hda1 */
85 #ifdef CONFIG_BLK_DEV_INITRD
87 ROOT_DEV
= Root_FD0
; /* floppy */
92 #if 0 /* XXX this may need to be updated for the new bootmem stuff,
93 or possibly just deleted (see set_phys_avail() in init.c).
95 /* initrd_start and size are setup by boot/head.S and kernel/head.S */
98 if (initrd_end
> *memory_end_p
)
100 printk("initrd extends beyond end of memory "
101 "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
102 initrd_end
,*memory_end_p
);
117 machine_restart(NULL
);
123 /* A place holder for time base interrupts, if they are ever enabled. */
124 irqreturn_t
timebase_interrupt(int irq
, void * dev
, struct pt_regs
* regs
)
126 printk ("timebase_interrupt()\n");
131 static struct irqaction tbint_irqaction
= {
132 .handler
= timebase_interrupt
,
133 .mask
= CPU_MASK_NONE
,
137 /* The decrementer counts at the system (internal) clock frequency divided by
138 * sixteen, or external oscillator divided by four. We force the processor
139 * to use system clock divided by sixteen.
141 void __init
m8xx_calibrate_decr(void)
143 bd_t
*binfo
= (bd_t
*)__res
;
144 int freq
, fp
, divisor
;
146 /* Unlock the SCCR. */
147 out_be32(&((immap_t
*)IMAP_ADDR
)->im_clkrstk
.cark_sccrk
, ~KAPWR_KEY
);
148 out_be32(&((immap_t
*)IMAP_ADDR
)->im_clkrstk
.cark_sccrk
, KAPWR_KEY
);
150 /* Force all 8xx processors to use divide by 16 processor clock. */
151 out_be32(&((immap_t
*)IMAP_ADDR
)->im_clkrst
.car_sccr
,
152 in_be32(&((immap_t
*)IMAP_ADDR
)->im_clkrst
.car_sccr
)|0x02000000);
153 /* Processor frequency is MHz.
154 * The value 'fp' is the number of decrementer ticks per second.
156 fp
= binfo
->bi_intfreq
/ 16;
157 freq
= fp
*60; /* try to make freq/1e6 an integer */
159 printk("Decrementer Frequency = %d/%d\n", freq
, divisor
);
160 tb_ticks_per_jiffy
= freq
/ HZ
/ divisor
;
161 tb_to_us
= mulhwu_scale_factor(freq
/ divisor
, 1000000);
163 /* Perform some more timer/timebase initialization. This used
164 * to be done elsewhere, but other changes caused it to get
165 * called more than once....that is a bad thing.
167 * First, unlock all of the registers we are going to modify.
168 * To protect them from corruption during power down, registers
169 * that are maintained by keep alive power are "locked". To
170 * modify these registers we have to write the key value to
171 * the key location associated with the register.
172 * Some boards power up with these unlocked, while others
173 * are locked. Writing anything (including the unlock code?)
174 * to the unlocked registers will lock them again. So, here
175 * we guarantee the registers are locked, then we unlock them
178 out_be32(&((immap_t
*)IMAP_ADDR
)->im_sitk
.sitk_tbscrk
, ~KAPWR_KEY
);
179 out_be32(&((immap_t
*)IMAP_ADDR
)->im_sitk
.sitk_rtcsck
, ~KAPWR_KEY
);
180 out_be32(&((immap_t
*)IMAP_ADDR
)->im_sitk
.sitk_tbk
, ~KAPWR_KEY
);
181 out_be32(&((immap_t
*)IMAP_ADDR
)->im_sitk
.sitk_tbscrk
, KAPWR_KEY
);
182 out_be32(&((immap_t
*)IMAP_ADDR
)->im_sitk
.sitk_rtcsck
, KAPWR_KEY
);
183 out_be32(&((immap_t
*)IMAP_ADDR
)->im_sitk
.sitk_tbk
, KAPWR_KEY
);
185 /* Disable the RTC one second and alarm interrupts. */
186 out_be16(&((immap_t
*)IMAP_ADDR
)->im_sit
.sit_rtcsc
, in_be16(&((immap_t
*)IMAP_ADDR
)->im_sit
.sit_rtcsc
) & ~(RTCSC_SIE
| RTCSC_ALE
));
188 out_be16(&((immap_t
*)IMAP_ADDR
)->im_sit
.sit_rtcsc
, in_be16(&((immap_t
*)IMAP_ADDR
)->im_sit
.sit_rtcsc
) | (RTCSC_RTF
| RTCSC_RTE
));
190 /* Enabling the decrementer also enables the timebase interrupts
191 * (or from the other point of view, to get decrementer interrupts
192 * we have to enable the timebase). The decrementer interrupt
193 * is wired into the vector table, nothing to do here for that.
195 out_be16(&((immap_t
*)IMAP_ADDR
)->im_sit
.sit_tbscr
, (mk_int_int_mask(DEC_INTERRUPT
) << 8) | (TBSCR_TBF
| TBSCR_TBE
));
197 if (setup_irq(DEC_INTERRUPT
, &tbint_irqaction
))
198 panic("Could not allocate timer IRQ!");
200 #ifdef CONFIG_8xx_WDT
201 /* Install watchdog timer handler early because it might be
202 * already enabled by the bootloader
204 m8xx_wdt_handler_install(binfo
);
208 /* The RTC on the MPC8xx is an internal register.
209 * We want to protect this during power down, so we need to unlock,
210 * modify, and re-lock.
213 m8xx_set_rtc_time(unsigned long time
)
215 out_be32(&((immap_t
*)IMAP_ADDR
)->im_sitk
.sitk_rtck
, KAPWR_KEY
);
216 out_be32(&((immap_t
*)IMAP_ADDR
)->im_sit
.sit_rtc
, time
);
217 out_be32(&((immap_t
*)IMAP_ADDR
)->im_sitk
.sitk_rtck
, ~KAPWR_KEY
);
222 m8xx_get_rtc_time(void)
224 /* Get time from the RTC. */
225 return (unsigned long) in_be32(&((immap_t
*)IMAP_ADDR
)->im_sit
.sit_rtc
);
229 m8xx_restart(char *cmd
)
231 __volatile__
unsigned char dummy
;
234 out_be32(&((immap_t
*)IMAP_ADDR
)->im_clkrst
.car_plprcr
, in_be32(&((immap_t
*)IMAP_ADDR
)->im_clkrst
.car_plprcr
) | 0x00000080);
236 /* Clear the ME bit in MSR to cause checkstop on machine check
238 mtmsr(mfmsr() & ~0x1000);
240 dummy
= in_8(&((immap_t
*)IMAP_ADDR
)->im_clkrst
.res
[0]);
241 printk("Restart failed\n");
259 m8xx_show_percpuinfo(struct seq_file
*m
, int i
)
265 seq_printf(m
, "clock\t\t: %uMHz\n"
266 "bus clock\t: %uMHz\n",
267 bp
->bi_intfreq
/ 1000000,
268 bp
->bi_busfreq
/ 1000000);
274 static struct irqaction mbx_i8259_irqaction
= {
275 .handler
= mbx_i8259_action
,
276 .mask
= CPU_MASK_NONE
,
277 .name
= "i8259 cascade",
281 /* Initialize the internal interrupt controller. The number of
282 * interrupts supported can vary with the processor type, and the
283 * 82xx family can have up to 64.
284 * External interrupts can be either edge or level triggered, and
285 * need to be initialized by the appropriate driver.
292 for (i
= SIU_IRQ_OFFSET
; i
< SIU_IRQ_OFFSET
+ NR_SIU_INTS
; i
++)
293 irq_desc
[i
].handler
= &ppc8xx_pic
;
295 cpm_interrupt_init();
297 #if defined(CONFIG_PCI)
298 for (i
= I8259_IRQ_OFFSET
; i
< I8259_IRQ_OFFSET
+ NR_8259_INTS
; i
++)
299 irq_desc
[i
].handler
= &i8259_pic
;
301 i8259_pic_irq_offset
= I8259_IRQ_OFFSET
;
304 /* The i8259 cascade interrupt must be level sensitive. */
305 out_be32(&((immap_t
*)IMAP_ADDR
)->im_siu_conf
.sc_siel
, in_be32(&((immap_t
*)IMAP_ADDR
)->im_siu_conf
.sc_siel
& ~(0x80000000 >> ISA_BRIDGE_INT
)));
307 if (setup_irq(ISA_BRIDGE_INT
, &mbx_i8259_irqaction
))
308 enable_irq(ISA_BRIDGE_INT
);
309 #endif /* CONFIG_PCI */
312 /* -------------------------------------------------------------------- */
315 * This is a big hack right now, but it may turn into something real
318 * For the 8xx boards (at this time anyway), there is nothing to initialize
319 * associated the PROM. Rather than include all of the prom.c
320 * functions in the image just to get prom_init, all we really need right
321 * now is the initialization of the physical memory region.
323 static unsigned long __init
324 m8xx_find_end_of_memory(void)
327 extern unsigned char __res
[];
329 binfo
= (bd_t
*)__res
;
331 return binfo
->bi_memsize
;
335 * Now map in some of the I/O space that is generically needed
336 * or shared with multiple devices.
337 * All of this fits into the same 4Mbyte region, so it only
338 * requires one page table page. (or at least it used to -- paulus)
343 io_block_mapping(IMAP_ADDR
, IMAP_ADDR
, IMAP_SIZE
, _PAGE_IO
);
345 io_block_mapping(NVRAM_ADDR
, NVRAM_ADDR
, NVRAM_SIZE
, _PAGE_IO
);
346 io_block_mapping(MBX_CSR_ADDR
, MBX_CSR_ADDR
, MBX_CSR_SIZE
, _PAGE_IO
);
347 io_block_mapping(PCI_CSR_ADDR
, PCI_CSR_ADDR
, PCI_CSR_SIZE
, _PAGE_IO
);
349 /* Map some of the PCI/ISA I/O space to get the IDE interface.
351 io_block_mapping(PCI_ISA_IO_ADDR
, PCI_ISA_IO_ADDR
, 0x4000, _PAGE_IO
);
352 io_block_mapping(PCI_IDE_ADDR
, PCI_IDE_ADDR
, 0x4000, _PAGE_IO
);
354 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
355 io_block_mapping(RPX_CSR_ADDR
, RPX_CSR_ADDR
, RPX_CSR_SIZE
, _PAGE_IO
);
356 #if !defined(CONFIG_PCI)
357 io_block_mapping(_IO_BASE
,_IO_BASE
,_IO_BASE_SIZE
, _PAGE_IO
);
360 #if defined(CONFIG_HTDMSOUND) || defined(CONFIG_RPXTOUCH) || defined(CONFIG_FB_RPX)
361 io_block_mapping(HIOX_CSR_ADDR
, HIOX_CSR_ADDR
, HIOX_CSR_SIZE
, _PAGE_IO
);
364 io_block_mapping(BCSR_ADDR
, BCSR_ADDR
, BCSR_SIZE
, _PAGE_IO
);
367 io_block_mapping(PCI_CSR_ADDR
, PCI_CSR_ADDR
, PCI_CSR_SIZE
, _PAGE_IO
);
369 #if defined(CONFIG_NETTA)
370 io_block_mapping(_IO_BASE
,_IO_BASE
,_IO_BASE_SIZE
, _PAGE_IO
);
375 platform_init(unsigned long r3
, unsigned long r4
, unsigned long r5
,
376 unsigned long r6
, unsigned long r7
)
378 parse_bootinfo(find_bootinfo());
381 memcpy( (void *)__res
,(void *)(r3
+KERNELBASE
), sizeof(bd_t
) );
384 m8xx_setup_pci_ptrs();
387 #ifdef CONFIG_BLK_DEV_INITRD
388 /* take care of initrd if we have one */
391 initrd_start
= r4
+ KERNELBASE
;
392 initrd_end
= r5
+ KERNELBASE
;
394 #endif /* CONFIG_BLK_DEV_INITRD */
395 /* take care of cmd line */
398 *(char *)(r7
+KERNELBASE
) = 0;
399 strcpy(cmd_line
, (char *)(r6
+KERNELBASE
));
402 ppc_md
.setup_arch
= m8xx_setup_arch
;
403 ppc_md
.show_percpuinfo
= m8xx_show_percpuinfo
;
404 ppc_md
.init_IRQ
= m8xx_init_IRQ
;
405 ppc_md
.get_irq
= m8xx_get_irq
;
408 ppc_md
.restart
= m8xx_restart
;
409 ppc_md
.power_off
= m8xx_power_off
;
410 ppc_md
.halt
= m8xx_halt
;
412 ppc_md
.time_init
= NULL
;
413 ppc_md
.set_rtc_time
= m8xx_set_rtc_time
;
414 ppc_md
.get_rtc_time
= m8xx_get_rtc_time
;
415 ppc_md
.calibrate_decr
= m8xx_calibrate_decr
;
417 ppc_md
.find_end_of_memory
= m8xx_find_end_of_memory
;
418 ppc_md
.setup_io_mappings
= m8xx_map_io
;
420 #if defined(CONFIG_BLK_DEV_MPC8xx_IDE)