arch/ppc/syslib/ppc85xx_setup.c

   1 /*
   2  * arch/ppc/syslib/ppc85xx_setup.c
   3  *
   4  * MPC85XX common board code
   5  *
   6  * Maintainer: Kumar Gala <kumar.gala@freescale.com>
   7  *
   8  * Copyright 2004 Freescale Semiconductor Inc.
   9  *
  10  * This program is free software; you can redistribute  it and/or modify it
  11  * under  the terms of  the GNU General  Public License as published by the
  12  * Free Software Foundation;  either version 2 of the  License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/types.h>
  18 #include <linux/module.h>
  19 #include <linux/init.h>
  20 #include <linux/pci.h>
  21 #include <linux/serial.h>
  22 #include <linux/tty.h>  /* for linux/serial_core.h */
  23 #include <linux/serial_core.h>
  24 #include <linux/serial_8250.h>
  25
  26 #include <asm/prom.h>
  27 #include <asm/time.h>
  28 #include <asm/mpc85xx.h>
  29 #include <asm/immap_85xx.h>
  30 #include <asm/mmu.h>
  31 #include <asm/ppc_sys.h>
  32 #include <asm/kgdb.h>
  33
  34 #include <syslib/ppc85xx_setup.h>
  35
  36 /* Return the amount of memory */
  37 unsigned long __init
  38 mpc85xx_find_end_of_memory(void)
  39 {
  40         bd_t *binfo;
  41
  42         binfo = (bd_t *) __res;
  43
  44         return binfo->bi_memsize;
  45 }
  46
  47 /* The decrementer counts at the system (internal) clock freq divided by 8 */
  48 void __init
  49 mpc85xx_calibrate_decr(void)
  50 {
  51         bd_t *binfo = (bd_t *) __res;
  52         unsigned int freq, divisor;
  53
  54         /* get the core frequency */
  55         freq = binfo->bi_busfreq;
  56
  57         /* The timebase is updated every 8 bus clocks, HID0[SEL_TBCLK] = 0 */
  58         divisor = 8;
  59         tb_ticks_per_jiffy = freq / divisor / HZ;
  60         tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
  61
  62         /* Set the time base to zero */
  63         mtspr(SPRN_TBWL, 0);
  64         mtspr(SPRN_TBWU, 0);
  65
  66         /* Clear any pending timer interrupts */
  67         mtspr(SPRN_TSR, TSR_ENW | TSR_WIS | TSR_DIS | TSR_FIS);
  68
  69         /* Enable decrementer interrupt */
  70         mtspr(SPRN_TCR, TCR_DIE);
  71 }
  72
  73 #ifdef CONFIG_SERIAL_8250
  74 void __init
  75 mpc85xx_early_serial_map(void)
  76 {
  77 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
  78         struct uart_port serial_req;
  79 #endif
  80         struct plat_serial8250_port *pdata;
  81         bd_t *binfo = (bd_t *) __res;
  82         pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(MPC85xx_DUART);
  83
  84         /* Setup serial port access */
  85         pdata[0].uartclk = binfo->bi_busfreq;
  86         pdata[0].mapbase += binfo->bi_immr_base;
  87         pdata[0].membase = ioremap(pdata[0].mapbase, MPC85xx_UART0_SIZE);
  88
  89 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
  90         memset(&serial_req, 0, sizeof (serial_req));
  91         serial_req.iotype = SERIAL_IO_MEM;
  92         serial_req.mapbase = pdata[0].mapbase;
  93         serial_req.membase = pdata[0].membase;
  94         serial_req.regshift = 0;
  95
  96         gen550_init(0, &serial_req);
  97 #endif
  98
  99         pdata[1].uartclk = binfo->bi_busfreq;
 100         pdata[1].mapbase += binfo->bi_immr_base;
 101         pdata[1].membase = ioremap(pdata[1].mapbase, MPC85xx_UART0_SIZE);
 102
 103 #if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
 104         /* Assume gen550_init() doesn't modify serial_req */
 105         serial_req.mapbase = pdata[1].mapbase;
 106         serial_req.membase = pdata[1].membase;
 107
 108         gen550_init(1, &serial_req);
 109 #endif
 110 }
 111 #endif
 112
 113 void
 114 mpc85xx_restart(char *cmd)
 115 {
 116         local_irq_disable();
 117         abort();
 118 }
 119
 120 void
 121 mpc85xx_power_off(void)
 122 {
 123         local_irq_disable();
 124         for(;;);
 125 }
 126
 127 void
 128 mpc85xx_halt(void)
 129 {
 130         local_irq_disable();
 131         for(;;);
 132 }
 133
 134 #ifdef CONFIG_PCI
 135 static void __init
 136 mpc85xx_setup_pci1(struct pci_controller *hose)
 137 {
 138         volatile struct ccsr_pci *pci;
 139         volatile struct ccsr_guts *guts;
 140         unsigned short temps;
 141         bd_t *binfo = (bd_t *) __res;
 142
 143         pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI1_OFFSET,
 144                     MPC85xx_PCI1_SIZE);
 145
 146         guts = ioremap(binfo->bi_immr_base + MPC85xx_GUTS_OFFSET,
 147                     MPC85xx_GUTS_SIZE);
 148
 149         early_read_config_word(hose, 0, 0, PCI_COMMAND, &temps);
 150         temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 151         early_write_config_word(hose, 0, 0, PCI_COMMAND, temps);
 152
 153 #define PORDEVSR_PCI    (0x00800000)    /* PCI Mode */
 154         if (guts->pordevsr & PORDEVSR_PCI) {
 155                 early_write_config_byte(hose, 0, 0, PCI_LATENCY_TIMER, 0x80);
 156         } else {
 157                 /* PCI-X init */
 158                 temps = PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ
 159                         | PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E;
 160                 early_write_config_word(hose, 0, 0, PCIX_COMMAND, temps);
 161         }
 162
 163         /* Disable all windows (except powar0 since its ignored) */
 164         pci->powar1 = 0;
 165         pci->powar2 = 0;
 166         pci->powar3 = 0;
 167         pci->powar4 = 0;
 168         pci->piwar1 = 0;
 169         pci->piwar2 = 0;
 170         pci->piwar3 = 0;
 171
 172         /* Setup Phys:PCI 1:1 outbound mem window @ MPC85XX_PCI1_LOWER_MEM */
 173         pci->potar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff;
 174         pci->potear1 = 0x00000000;
 175         pci->powbar1 = (MPC85XX_PCI1_LOWER_MEM >> 12) & 0x000fffff;
 176         /* Enable, Mem R/W */
 177         pci->powar1 = 0x80044000 |
 178            (__ilog2(MPC85XX_PCI1_UPPER_MEM - MPC85XX_PCI1_LOWER_MEM + 1) - 1);
 179
 180         /* Setup outboud IO windows @ MPC85XX_PCI1_IO_BASE */
 181         pci->potar2 = 0x00000000;
 182         pci->potear2 = 0x00000000;
 183         pci->powbar2 = (MPC85XX_PCI1_IO_BASE >> 12) & 0x000fffff;
 184         /* Enable, IO R/W */
 185         pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI1_IO_SIZE) - 1);
 186
 187         /* Setup 2G inbound Memory Window @ 0 */
 188         pci->pitar1 = 0x00000000;
 189         pci->piwbar1 = 0x00000000;
 190         pci->piwar1 = 0xa0f5501e;       /* Enable, Prefetch, Local
 191                                            Mem, Snoop R/W, 2G */
 192 }
 193
 194
 195 extern int mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin);
 196 extern int mpc85xx_exclude_device(u_char bus, u_char devfn);
 197
 198 #ifdef CONFIG_85xx_PCI2
 199 static void __init
 200 mpc85xx_setup_pci2(struct pci_controller *hose)
 201 {
 202         volatile struct ccsr_pci *pci;
 203         unsigned short temps;
 204         bd_t *binfo = (bd_t *) __res;
 205
 206         pci = ioremap(binfo->bi_immr_base + MPC85xx_PCI2_OFFSET,
 207                     MPC85xx_PCI2_SIZE);
 208
 209         early_read_config_word(hose, hose->bus_offset, 0, PCI_COMMAND, &temps);
 210         temps |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
 211         early_write_config_word(hose, hose->bus_offset, 0, PCI_COMMAND, temps);
 212         early_write_config_byte(hose, hose->bus_offset, 0, PCI_LATENCY_TIMER, 0x80);
 213
 214         /* Disable all windows (except powar0 since its ignored) */
 215         pci->powar1 = 0;
 216         pci->powar2 = 0;
 217         pci->powar3 = 0;
 218         pci->powar4 = 0;
 219         pci->piwar1 = 0;
 220         pci->piwar2 = 0;
 221         pci->piwar3 = 0;
 222
 223         /* Setup Phys:PCI 1:1 outbound mem window @ MPC85XX_PCI2_LOWER_MEM */
 224         pci->potar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff;
 225         pci->potear1 = 0x00000000;
 226         pci->powbar1 = (MPC85XX_PCI2_LOWER_MEM >> 12) & 0x000fffff;
 227         /* Enable, Mem R/W */
 228         pci->powar1 = 0x80044000 |
 229            (__ilog2(MPC85XX_PCI1_UPPER_MEM - MPC85XX_PCI1_LOWER_MEM + 1) - 1);
 230
 231         /* Setup outboud IO windows @ MPC85XX_PCI2_IO_BASE */
 232         pci->potar2 = 0x00000000;
 233         pci->potear2 = 0x00000000;
 234         pci->powbar2 = (MPC85XX_PCI2_IO_BASE >> 12) & 0x000fffff;
 235         /* Enable, IO R/W */
 236         pci->powar2 = 0x80088000 | (__ilog2(MPC85XX_PCI1_IO_SIZE) - 1);
 237
 238         /* Setup 2G inbound Memory Window @ 0 */
 239         pci->pitar1 = 0x00000000;
 240         pci->piwbar1 = 0x00000000;
 241         pci->piwar1 = 0xa0f5501e;       /* Enable, Prefetch, Local
 242                                            Mem, Snoop R/W, 2G */
 243 }
 244 #endif /* CONFIG_85xx_PCI2 */
 245
 246 int mpc85xx_pci1_last_busno = 0;
 247
 248 void __init
 249 mpc85xx_setup_hose(void)
 250 {
 251         struct pci_controller *hose_a;
 252 #ifdef CONFIG_85xx_PCI2
 253         struct pci_controller *hose_b;
 254 #endif
 255         bd_t *binfo = (bd_t *) __res;
 256
 257         hose_a = pcibios_alloc_controller();
 258
 259         if (!hose_a)
 260                 return;
 261
 262         ppc_md.pci_swizzle = common_swizzle;
 263         ppc_md.pci_map_irq = mpc85xx_map_irq;
 264
 265         hose_a->first_busno = 0;
 266         hose_a->bus_offset = 0;
 267         hose_a->last_busno = 0xff;
 268
 269         setup_indirect_pci(hose_a, binfo->bi_immr_base + PCI1_CFG_ADDR_OFFSET,
 270                            binfo->bi_immr_base + PCI1_CFG_DATA_OFFSET);
 271         hose_a->set_cfg_type = 1;
 272
 273         mpc85xx_setup_pci1(hose_a);
 274
 275         hose_a->pci_mem_offset = MPC85XX_PCI1_MEM_OFFSET;
 276         hose_a->mem_space.start = MPC85XX_PCI1_LOWER_MEM;
 277         hose_a->mem_space.end = MPC85XX_PCI1_UPPER_MEM;
 278
 279         hose_a->io_space.start = MPC85XX_PCI1_LOWER_IO;
 280         hose_a->io_space.end = MPC85XX_PCI1_UPPER_IO;
 281         hose_a->io_base_phys = MPC85XX_PCI1_IO_BASE;
 282 #ifdef CONFIG_85xx_PCI2
 283         isa_io_base =
 284                 (unsigned long) ioremap(MPC85XX_PCI1_IO_BASE,
 285                                         MPC85XX_PCI1_IO_SIZE +
 286                                         MPC85XX_PCI2_IO_SIZE);
 287 #else
 288         isa_io_base =
 289                 (unsigned long) ioremap(MPC85XX_PCI1_IO_BASE,
 290                                         MPC85XX_PCI1_IO_SIZE);
 291 #endif
 292         hose_a->io_base_virt = (void *) isa_io_base;
 293
 294         /* setup resources */
 295         pci_init_resource(&hose_a->mem_resources[0],
 296                         MPC85XX_PCI1_LOWER_MEM,
 297                         MPC85XX_PCI1_UPPER_MEM,
 298                         IORESOURCE_MEM, "PCI1 host bridge");
 299
 300         pci_init_resource(&hose_a->io_resource,
 301                         MPC85XX_PCI1_LOWER_IO,
 302                         MPC85XX_PCI1_UPPER_IO,
 303                         IORESOURCE_IO, "PCI1 host bridge");
 304
 305         ppc_md.pci_exclude_device = mpc85xx_exclude_device;
 306
 307         hose_a->last_busno = pciauto_bus_scan(hose_a, hose_a->first_busno);
 308
 309 #ifdef CONFIG_85xx_PCI2
 310         hose_b = pcibios_alloc_controller();
 311
 312         if (!hose_b)
 313                 return;
 314
 315         hose_b->bus_offset = hose_a->last_busno + 1;
 316         hose_b->first_busno = hose_a->last_busno + 1;
 317         hose_b->last_busno = 0xff;
 318
 319         setup_indirect_pci(hose_b, binfo->bi_immr_base + PCI2_CFG_ADDR_OFFSET,
 320                            binfo->bi_immr_base + PCI2_CFG_DATA_OFFSET);
 321         hose_b->set_cfg_type = 1;
 322
 323         mpc85xx_setup_pci2(hose_b);
 324
 325         hose_b->pci_mem_offset = MPC85XX_PCI2_MEM_OFFSET;
 326         hose_b->mem_space.start = MPC85XX_PCI2_LOWER_MEM;
 327         hose_b->mem_space.end = MPC85XX_PCI2_UPPER_MEM;
 328
 329         hose_b->io_space.start = MPC85XX_PCI2_LOWER_IO;
 330         hose_b->io_space.end = MPC85XX_PCI2_UPPER_IO;
 331         hose_b->io_base_phys = MPC85XX_PCI2_IO_BASE;
 332         hose_b->io_base_virt = (void *) isa_io_base + MPC85XX_PCI1_IO_SIZE;
 333
 334         /* setup resources */
 335         pci_init_resource(&hose_b->mem_resources[0],
 336                         MPC85XX_PCI2_LOWER_MEM,
 337                         MPC85XX_PCI2_UPPER_MEM,
 338                         IORESOURCE_MEM, "PCI2 host bridge");
 339
 340         pci_init_resource(&hose_b->io_resource,
 341                         MPC85XX_PCI2_LOWER_IO,
 342                         MPC85XX_PCI2_UPPER_IO,
 343                         IORESOURCE_IO, "PCI2 host bridge");
 344
 345         hose_b->last_busno = pciauto_bus_scan(hose_b, hose_b->first_busno);
 346
 347         /* let board code know what the last bus number was on PCI1 */
 348         mpc85xx_pci1_last_busno = hose_a->last_busno;
 349 #endif
 350         return;
 351 }
 352 #endif /* CONFIG_PCI */
 353
 354