arch/ppc/syslib/xilinx_pic.c

   1 /*
   2  * arch/ppc/syslib/xilinx_pic.c
   3  *
   4  * Interrupt controller driver for Xilinx Virtex-II Pro.
   5  *
   6  * Author: MontaVista Software, Inc.
   7  *         source@mvista.com
   8  *
   9  * 2002-2004 (c) MontaVista Software, Inc. This file is licensed under
  10  * the terms of the GNU General Public License version 2. This program
  11  * is licensed "as is" without any warranty of any kind, whether express
  12  * or implied.
  13  */
  14
  15 #include <linux/init.h>
  16 #include <linux/irq.h>
  17 #include <asm/io.h>
  18 #include <asm/xparameters.h>
  19 #include <asm/ibm4xx.h>
  20
  21 /* No one else should require these constants, so define them locally here. */
  22 #define ISR 0                   /* Interrupt Status Register */
  23 #define IPR 1                   /* Interrupt Pending Register */
  24 #define IER 2                   /* Interrupt Enable Register */
  25 #define IAR 3                   /* Interrupt Acknowledge Register */
  26 #define SIE 4                   /* Set Interrupt Enable bits */
  27 #define CIE 5                   /* Clear Interrupt Enable bits */
  28 #define IVR 6                   /* Interrupt Vector Register */
  29 #define MER 7                   /* Master Enable Register */
  30
  31 #if XPAR_XINTC_USE_DCR == 0
  32 static volatile u32 *intc;
  33 #define intc_out_be32(addr, mask)     out_be32((addr), (mask))
  34 #define intc_in_be32(addr)            in_be32((addr))
  35 #else
  36 #define intc    XPAR_INTC_0_BASEADDR
  37 #define intc_out_be32(addr, mask)     mtdcr((addr), (mask))
  38 #define intc_in_be32(addr)            mfdcr((addr))
  39 #endif
  40
  41 static void
  42 xilinx_intc_enable(unsigned int irq)
  43 {
  44         unsigned long mask = (0x00000001 << (irq & 31));
  45         pr_debug("enable: %d\n", irq);
  46         intc_out_be32(intc + SIE, mask);
  47 }
  48
  49 static void
  50 xilinx_intc_disable(unsigned int irq)
  51 {
  52         unsigned long mask = (0x00000001 << (irq & 31));
  53         pr_debug("disable: %d\n", irq);
  54         intc_out_be32(intc + CIE, mask);
  55 }
  56
  57 static void
  58 xilinx_intc_disable_and_ack(unsigned int irq)
  59 {
  60         unsigned long mask = (0x00000001 << (irq & 31));
  61         pr_debug("disable_and_ack: %d\n", irq);
  62         intc_out_be32(intc + CIE, mask);
  63         if (!(irq_desc[irq].status & IRQ_LEVEL))
  64                 intc_out_be32(intc + IAR, mask);        /* ack edge triggered intr */
  65 }
  66
  67 static void
  68 xilinx_intc_end(unsigned int irq)
  69 {
  70         unsigned long mask = (0x00000001 << (irq & 31));
  71
  72         pr_debug("end: %d\n", irq);
  73         if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
  74                 intc_out_be32(intc + SIE, mask);
  75                 /* ack level sensitive intr */
  76                 if (irq_desc[irq].status & IRQ_LEVEL)
  77                         intc_out_be32(intc + IAR, mask);
  78         }
  79 }
  80
  81 static struct hw_interrupt_type xilinx_intc = {
  82         .typename = "Xilinx Interrupt Controller",
  83         .enable = xilinx_intc_enable,
  84         .disable = xilinx_intc_disable,
  85         .ack = xilinx_intc_disable_and_ack,
  86         .end = xilinx_intc_end,
  87 };
  88
  89 int
  90 xilinx_pic_get_irq(struct pt_regs *regs)
  91 {
  92         int irq;
  93
  94         /*
  95          * NOTE: This function is the one that needs to be improved in
  96          * order to handle multiple interrupt controllers.  It currently
  97          * is hardcoded to check for interrupts only on the first INTC.
  98          */
  99
 100         irq = intc_in_be32(intc + IVR);
 101         if (irq != -1)
 102                 irq = irq;
 103
 104         pr_debug("get_irq: %d\n", irq);
 105
 106         return (irq);
 107 }
 108
 109 void __init
 110 ppc4xx_pic_init(void)
 111 {
 112         int i;
 113
 114         /*
 115          * NOTE: The assumption here is that NR_IRQS is 32 or less
 116          * (NR_IRQS is 32 for PowerPC 405 cores by default).
 117          */
 118 #if (NR_IRQS > 32)
 119 #error NR_IRQS > 32 not supported
 120 #endif
 121
 122 #if XPAR_XINTC_USE_DCR == 0
 123         intc = ioremap(XPAR_INTC_0_BASEADDR, 32);
 124
 125         printk(KERN_INFO "Xilinx INTC #0 at 0x%08lX mapped to 0x%08lX\n",
 126                (unsigned long) XPAR_INTC_0_BASEADDR, (unsigned long) intc);
 127 #else
 128         printk(KERN_INFO "Xilinx INTC #0 at 0x%08lX (DCR)\n",
 129                (unsigned long) XPAR_INTC_0_BASEADDR);
 130 #endif
 131
 132         /*
 133          * Disable all external interrupts until they are
 134          * explicity requested.
 135          */
 136         intc_out_be32(intc + IER, 0);
 137
 138         /* Acknowledge any pending interrupts just in case. */
 139         intc_out_be32(intc + IAR, ~(u32) 0);
 140
 141         /* Turn on the Master Enable. */
 142         intc_out_be32(intc + MER, 0x3UL);
 143
 144         ppc_md.get_irq = xilinx_pic_get_irq;
 145
 146         for (i = 0; i < NR_IRQS; ++i) {
 147                 irq_desc[i].handler = &xilinx_intc;
 148
 149                 if (XPAR_INTC_0_KIND_OF_INTR & (0x00000001 << i))
 150                         irq_desc[i].status &= ~IRQ_LEVEL;
 151                 else
 152                         irq_desc[i].status |= IRQ_LEVEL;
 153         }
 154 }