arch/riscv/include/asm/hwcap.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Copied from arch/arm64/include/asm/hwcap.h
   4  *
   5  * Copyright (C) 2012 ARM Ltd.
   6  * Copyright (C) 2017 SiFive
   7  */
   8 #ifndef _ASM_RISCV_HWCAP_H
   9 #define _ASM_RISCV_HWCAP_H
  10
  11 #include <linux/bits.h>
  12 #include <uapi/asm/hwcap.h>
  13
  14 #ifndef __ASSEMBLY__
  15 #include <linux/jump_label.h>
  16 /*
  17  * This yields a mask that user programs can use to figure out what
  18  * instruction set this cpu supports.
  19  */
  20 #define ELF_HWCAP               (elf_hwcap)
  21
  22 enum {
  23         CAP_HWCAP = 1,
  24 };
  25
  26 extern unsigned long elf_hwcap;
  27
  28 #define RISCV_ISA_EXT_a         ('a' - 'a')
  29 #define RISCV_ISA_EXT_c         ('c' - 'a')
  30 #define RISCV_ISA_EXT_d         ('d' - 'a')
  31 #define RISCV_ISA_EXT_f         ('f' - 'a')
  32 #define RISCV_ISA_EXT_h         ('h' - 'a')
  33 #define RISCV_ISA_EXT_i         ('i' - 'a')
  34 #define RISCV_ISA_EXT_m         ('m' - 'a')
  35 #define RISCV_ISA_EXT_s         ('s' - 'a')
  36 #define RISCV_ISA_EXT_u         ('u' - 'a')
  37
  38 /*
  39  * Increse this to higher value as kernel support more ISA extensions.
  40  */
  41 #define RISCV_ISA_EXT_MAX       64
  42 #define RISCV_ISA_EXT_NAME_LEN_MAX 32
  43
  44 /* The base ID for multi-letter ISA extensions */
  45 #define RISCV_ISA_EXT_BASE 26
  46
  47 /*
  48  * This enum represent the logical ID for each multi-letter RISC-V ISA extension.
  49  * The logical ID should start from RISCV_ISA_EXT_BASE and must not exceed
  50  * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter
  51  * extensions while all the multi-letter extensions should define the next
  52  * available logical extension id.
  53  */
  54 enum riscv_isa_ext_id {
  55         RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,
  56         RISCV_ISA_EXT_SVPBMT,
  57         RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,
  58 };
  59
  60 /*
  61  * This enum represents the logical ID for each RISC-V ISA extension static
  62  * keys. We can use static key to optimize code path if some ISA extensions
  63  * are available.
  64  */
  65 enum riscv_isa_ext_key {
  66         RISCV_ISA_EXT_KEY_FPU,          /* For 'F' and 'D' */
  67         RISCV_ISA_EXT_KEY_MAX,
  68 };
  69
  70 struct riscv_isa_ext_data {
  71         /* Name of the extension displayed to userspace via /proc/cpuinfo */
  72         char uprop[RISCV_ISA_EXT_NAME_LEN_MAX];
  73         /* The logical ISA extension ID */
  74         unsigned int isa_ext_id;
  75 };
  76
  77 extern struct static_key_false riscv_isa_ext_keys[RISCV_ISA_EXT_KEY_MAX];
  78
  79 static __always_inline int riscv_isa_ext2key(int num)
  80 {
  81         switch (num) {
  82         case RISCV_ISA_EXT_f:
  83                 return RISCV_ISA_EXT_KEY_FPU;
  84         case RISCV_ISA_EXT_d:
  85                 return RISCV_ISA_EXT_KEY_FPU;
  86         default:
  87                 return -EINVAL;
  88         }
  89 }
  90
  91 unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
  92
  93 #define riscv_isa_extension_mask(ext) BIT_MASK(RISCV_ISA_EXT_##ext)
  94
  95 bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, int bit);
  96 #define riscv_isa_extension_available(isa_bitmap, ext)  \
  97         __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
  98
  99 #endif
 100
 101 #endif /* _ASM_RISCV_HWCAP_H */