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2 * Copyright (C) 2012 Regents of the University of California
3 * Copyright (C) 2017 SiFive
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation, version 2.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #ifndef _ASM_RISCV_MMU_CONTEXT_H
16 #define _ASM_RISCV_MMU_CONTEXT_H
18 #include <linux/mm_types.h>
19 #include <asm-generic/mm_hooks.h>
22 #include <linux/sched.h>
23 #include <asm/tlbflush.h>
24 #include <asm/cacheflush.h>
26 static inline void enter_lazy_tlb(struct mm_struct
*mm
,
27 struct task_struct
*task
)
31 /* Initialize context-related info for a new mm_struct */
32 static inline int init_new_context(struct task_struct
*task
,
38 static inline void destroy_context(struct mm_struct
*mm
)
42 static inline pgd_t
*current_pgdir(void)
44 return pfn_to_virt(csr_read(sptbr
) & SPTBR_PPN
);
47 static inline void set_pgdir(pgd_t
*pgd
)
49 csr_write(sptbr
, virt_to_pfn(pgd
) | SPTBR_MODE
);
53 * When necessary, performs a deferred icache flush for the given MM context,
54 * on the local CPU. RISC-V has no direct mechanism for instruction cache
55 * shoot downs, so instead we send an IPI that informs the remote harts they
56 * need to flush their local instruction caches. To avoid pathologically slow
57 * behavior in a common case (a bunch of single-hart processes on a many-hart
58 * machine, ie 'make -j') we avoid the IPIs for harts that are not currently
59 * executing a MM context and instead schedule a deferred local instruction
60 * cache flush to be performed before execution resumes on each hart. This
61 * actually performs that local instruction cache flush, which implicitly only
62 * refers to the current hart.
64 static inline void flush_icache_deferred(struct mm_struct
*mm
)
67 unsigned int cpu
= smp_processor_id();
68 cpumask_t
*mask
= &mm
->context
.icache_stale_mask
;
70 if (cpumask_test_cpu(cpu
, mask
)) {
71 cpumask_clear_cpu(cpu
, mask
);
73 * Ensure the remote hart's writes are visible to this hart.
74 * This pairs with a barrier in flush_icache_mm.
77 local_flush_icache_all();
82 static inline void switch_mm(struct mm_struct
*prev
,
83 struct mm_struct
*next
, struct task_struct
*task
)
85 if (likely(prev
!= next
)) {
87 * Mark the current MM context as inactive, and the next as
88 * active. This is at least used by the icache flushing
89 * routines in order to determine who should
91 unsigned int cpu
= smp_processor_id();
93 cpumask_clear_cpu(cpu
, mm_cpumask(prev
));
94 cpumask_set_cpu(cpu
, mm_cpumask(next
));
97 local_flush_tlb_all();
99 flush_icache_deferred(next
);
103 static inline void activate_mm(struct mm_struct
*prev
,
104 struct mm_struct
*next
)
106 switch_mm(prev
, next
, NULL
);
109 static inline void deactivate_mm(struct task_struct
*task
,
110 struct mm_struct
*mm
)
114 #endif /* _ASM_RISCV_MMU_CONTEXT_H */