arch/s390/include/asm/mmu_context.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*
   3  *  S390 version
   4  *
   5  *  Derived from "include/asm-i386/mmu_context.h"
   6  */
   7
   8 #ifndef __S390_MMU_CONTEXT_H
   9 #define __S390_MMU_CONTEXT_H
  10
  11 #include <asm/pgalloc.h>
  12 #include <linux/uaccess.h>
  13 #include <linux/mm_types.h>
  14 #include <asm/tlbflush.h>
  15 #include <asm/ctl_reg.h>
  16 #include <asm-generic/mm_hooks.h>
  17
  18 static inline int init_new_context(struct task_struct *tsk,
  19                                    struct mm_struct *mm)
  20 {
  21         spin_lock_init(&mm->context.lock);
  22         INIT_LIST_HEAD(&mm->context.pgtable_list);
  23         INIT_LIST_HEAD(&mm->context.gmap_list);
  24         cpumask_clear(&mm->context.cpu_attach_mask);
  25         atomic_set(&mm->context.flush_count, 0);
  26         mm->context.gmap_asce = 0;
  27         mm->context.flush_mm = 0;
  28 #ifdef CONFIG_PGSTE
  29         mm->context.alloc_pgste = page_table_allocate_pgste ||
  30                 test_thread_flag(TIF_PGSTE) ||
  31                 current->mm->context.alloc_pgste;
  32         mm->context.has_pgste = 0;
  33         mm->context.use_skey = 0;
  34         mm->context.use_cmma = 0;
  35 #endif
  36         switch (mm->context.asce_limit) {
  37         case _REGION2_SIZE:
  38                 /*
  39                  * forked 3-level task, fall through to set new asce with new
  40                  * mm->pgd
  41                  */
  42         case 0:
  43                 /* context created by exec, set asce limit to 4TB */
  44                 mm->context.asce_limit = STACK_TOP_MAX;
  45                 mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
  46                                    _ASCE_USER_BITS | _ASCE_TYPE_REGION3;
  47                 /* pgd_alloc() did not account this pud */
  48                 mm_inc_nr_puds(mm);
  49                 break;
  50         case -PAGE_SIZE:
  51                 /* forked 5-level task, set new asce with new_mm->pgd */
  52                 mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
  53                         _ASCE_USER_BITS | _ASCE_TYPE_REGION1;
  54                 break;
  55         case _REGION1_SIZE:
  56                 /* forked 4-level task, set new asce with new mm->pgd */
  57                 mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
  58                                    _ASCE_USER_BITS | _ASCE_TYPE_REGION2;
  59                 break;
  60         case _REGION3_SIZE:
  61                 /* forked 2-level compat task, set new asce with new mm->pgd */
  62                 mm->context.asce = __pa(mm->pgd) | _ASCE_TABLE_LENGTH |
  63                                    _ASCE_USER_BITS | _ASCE_TYPE_SEGMENT;
  64                 /* pgd_alloc() did not account this pmd */
  65                 mm_inc_nr_pmds(mm);
  66         }
  67         crst_table_init((unsigned long *) mm->pgd, pgd_entry_type(mm));
  68         return 0;
  69 }
  70
  71 #define destroy_context(mm)             do { } while (0)
  72
  73 static inline void set_user_asce(struct mm_struct *mm)
  74 {
  75         S390_lowcore.user_asce = mm->context.asce;
  76         __ctl_load(S390_lowcore.user_asce, 1, 1);
  77         clear_cpu_flag(CIF_ASCE_PRIMARY);
  78 }
  79
  80 static inline void clear_user_asce(void)
  81 {
  82         S390_lowcore.user_asce = S390_lowcore.kernel_asce;
  83         __ctl_load(S390_lowcore.kernel_asce, 1, 1);
  84         set_cpu_flag(CIF_ASCE_PRIMARY);
  85 }
  86
  87 mm_segment_t enable_sacf_uaccess(void);
  88 void disable_sacf_uaccess(mm_segment_t old_fs);
  89
  90 static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
  91                              struct task_struct *tsk)
  92 {
  93         int cpu = smp_processor_id();
  94
  95         if (prev == next)
  96                 return;
  97         S390_lowcore.user_asce = next->context.asce;
  98         cpumask_set_cpu(cpu, &next->context.cpu_attach_mask);
  99         /* Clear previous user-ASCE from CR1 and CR7 */
 100         if (!test_cpu_flag(CIF_ASCE_PRIMARY)) {
 101                 __ctl_load(S390_lowcore.kernel_asce, 1, 1);
 102                 set_cpu_flag(CIF_ASCE_PRIMARY);
 103         }
 104         if (test_cpu_flag(CIF_ASCE_SECONDARY)) {
 105                 __ctl_load(S390_lowcore.vdso_asce, 7, 7);
 106                 clear_cpu_flag(CIF_ASCE_SECONDARY);
 107         }
 108         cpumask_clear_cpu(cpu, &prev->context.cpu_attach_mask);
 109 }
 110
 111 #define finish_arch_post_lock_switch finish_arch_post_lock_switch
 112 static inline void finish_arch_post_lock_switch(void)
 113 {
 114         struct task_struct *tsk = current;
 115         struct mm_struct *mm = tsk->mm;
 116
 117         if (mm) {
 118                 preempt_disable();
 119                 while (atomic_read(&mm->context.flush_count))
 120                         cpu_relax();
 121                 cpumask_set_cpu(smp_processor_id(), mm_cpumask(mm));
 122                 __tlb_flush_mm_lazy(mm);
 123                 preempt_enable();
 124         }
 125         set_fs(current->thread.mm_segment);
 126 }
 127
 128 #define enter_lazy_tlb(mm,tsk)  do { } while (0)
 129 #define deactivate_mm(tsk,mm)   do { } while (0)
 130
 131 static inline void activate_mm(struct mm_struct *prev,
 132                                struct mm_struct *next)
 133 {
 134         switch_mm(prev, next, current);
 135         cpumask_set_cpu(smp_processor_id(), mm_cpumask(next));
 136         set_user_asce(next);
 137 }
 138
 139 #endif /* __S390_MMU_CONTEXT_H */