arch/s390/include/asm/processor.h

   1 /*
   2  *  include/asm-s390/processor.h
   3  *
   4  *  S390 version
   5  *    Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
   6  *    Author(s): Hartmut Penner (hp@de.ibm.com),
   7  *               Martin Schwidefsky (schwidefsky@de.ibm.com)
   8  *
   9  *  Derived from "include/asm-i386/processor.h"
  10  *    Copyright (C) 1994, Linus Torvalds
  11  */
  12
  13 #ifndef __ASM_S390_PROCESSOR_H
  14 #define __ASM_S390_PROCESSOR_H
  15
  16 #include <linux/linkage.h>
  17 #include <linux/irqflags.h>
  18 #include <asm/cpu.h>
  19 #include <asm/page.h>
  20 #include <asm/ptrace.h>
  21 #include <asm/setup.h>
  22
  23 /*
  24  * Default implementation of macro that returns current
  25  * instruction pointer ("program counter").
  26  */
  27 #define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
  28
  29 static inline void get_cpu_id(struct cpuid *ptr)
  30 {
  31         asm volatile("stidp %0" : "=Q" (*ptr));
  32 }
  33
  34 extern void s390_adjust_jiffies(void);
  35 extern const struct seq_operations cpuinfo_op;
  36 extern int sysctl_ieee_emulation_warnings;
  37
  38 /*
  39  * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
  40  */
  41 #ifndef CONFIG_64BIT
  42
  43 #define TASK_SIZE               (1UL << 31)
  44 #define TASK_UNMAPPED_BASE      (1UL << 30)
  45
  46 #else /* CONFIG_64BIT */
  47
  48 #define TASK_SIZE_OF(tsk)       ((tsk)->mm->context.asce_limit)
  49 #define TASK_UNMAPPED_BASE      (test_thread_flag(TIF_31BIT) ? \
  50                                         (1UL << 30) : (1UL << 41))
  51 #define TASK_SIZE               TASK_SIZE_OF(current)
  52
  53 #endif /* CONFIG_64BIT */
  54
  55 #ifndef CONFIG_64BIT
  56 #define STACK_TOP               (1UL << 31)
  57 #define STACK_TOP_MAX           (1UL << 31)
  58 #else /* CONFIG_64BIT */
  59 #define STACK_TOP               (1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
  60 #define STACK_TOP_MAX           (1UL << 42)
  61 #endif /* CONFIG_64BIT */
  62
  63 #define HAVE_ARCH_PICK_MMAP_LAYOUT
  64
  65 typedef struct {
  66         __u32 ar4;
  67 } mm_segment_t;
  68
  69 /*
  70  * Thread structure
  71  */
  72 struct thread_struct {
  73         s390_fp_regs fp_regs;
  74         unsigned int  acrs[NUM_ACRS];
  75         unsigned long ksp;              /* kernel stack pointer             */
  76         mm_segment_t mm_segment;
  77         unsigned long gmap_addr;        /* address of last gmap fault. */
  78         struct per_regs per_user;       /* User specified PER registers */
  79         struct per_event per_event;     /* Cause of the last PER trap */
  80         /* pfault_wait is used to block the process on a pfault event */
  81         unsigned long pfault_wait;
  82         struct list_head list;
  83 };
  84
  85 typedef struct thread_struct thread_struct;
  86
  87 /*
  88  * Stack layout of a C stack frame.
  89  */
  90 #ifndef __PACK_STACK
  91 struct stack_frame {
  92         unsigned long back_chain;
  93         unsigned long empty1[5];
  94         unsigned long gprs[10];
  95         unsigned int  empty2[8];
  96 };
  97 #else
  98 struct stack_frame {
  99         unsigned long empty1[5];
 100         unsigned int  empty2[8];
 101         unsigned long gprs[10];
 102         unsigned long back_chain;
 103 };
 104 #endif
 105
 106 #define ARCH_MIN_TASKALIGN      8
 107
 108 #define INIT_THREAD {                                                   \
 109         .ksp = sizeof(init_stack) + (unsigned long) &init_stack,        \
 110 }
 111
 112 /*
 113  * Do necessary setup to start up a new thread.
 114  */
 115 #define start_thread(regs, new_psw, new_stackp) do {                    \
 116         regs->psw.mask  = psw_user_bits | PSW_MASK_EA | PSW_MASK_BA;    \
 117         regs->psw.addr  = new_psw | PSW_ADDR_AMODE;                     \
 118         regs->gprs[15]  = new_stackp;                                   \
 119 } while (0)
 120
 121 #define start_thread31(regs, new_psw, new_stackp) do {                  \
 122         regs->psw.mask  = psw_user_bits | PSW_MASK_BA;                  \
 123         regs->psw.addr  = new_psw | PSW_ADDR_AMODE;                     \
 124         regs->gprs[15]  = new_stackp;                                   \
 125         crst_table_downgrade(current->mm, 1UL << 31);                   \
 126 } while (0)
 127
 128 /* Forward declaration, a strange C thing */
 129 struct task_struct;
 130 struct mm_struct;
 131 struct seq_file;
 132
 133 /* Free all resources held by a thread. */
 134 extern void release_thread(struct task_struct *);
 135 extern int kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
 136
 137 /* Prepare to copy thread state - unlazy all lazy status */
 138 #define prepare_to_copy(tsk)    do { } while (0)
 139
 140 /*
 141  * Return saved PC of a blocked thread.
 142  */
 143 extern unsigned long thread_saved_pc(struct task_struct *t);
 144
 145 extern void show_code(struct pt_regs *regs);
 146
 147 unsigned long get_wchan(struct task_struct *p);
 148 #define task_pt_regs(tsk) ((struct pt_regs *) \
 149         (task_stack_page(tsk) + THREAD_SIZE) - 1)
 150 #define KSTK_EIP(tsk)   (task_pt_regs(tsk)->psw.addr)
 151 #define KSTK_ESP(tsk)   (task_pt_regs(tsk)->gprs[15])
 152
 153 static inline unsigned short stap(void)
 154 {
 155         unsigned short cpu_address;
 156
 157         asm volatile("stap %0" : "=m" (cpu_address));
 158         return cpu_address;
 159 }
 160
 161 /*
 162  * Give up the time slice of the virtual PU.
 163  */
 164 static inline void cpu_relax(void)
 165 {
 166         if (MACHINE_HAS_DIAG44)
 167                 asm volatile("diag 0,0,68");
 168         barrier();
 169 }
 170
 171 static inline void psw_set_key(unsigned int key)
 172 {
 173         asm volatile("spka 0(%0)" : : "d" (key));
 174 }
 175
 176 /*
 177  * Set PSW to specified value.
 178  */
 179 static inline void __load_psw(psw_t psw)
 180 {
 181 #ifndef CONFIG_64BIT
 182         asm volatile("lpsw  %0" : : "Q" (psw) : "cc");
 183 #else
 184         asm volatile("lpswe %0" : : "Q" (psw) : "cc");
 185 #endif
 186 }
 187
 188 /*
 189  * Set PSW mask to specified value, while leaving the
 190  * PSW addr pointing to the next instruction.
 191  */
 192 static inline void __load_psw_mask (unsigned long mask)
 193 {
 194         unsigned long addr;
 195         psw_t psw;
 196
 197         psw.mask = mask;
 198
 199 #ifndef CONFIG_64BIT
 200         asm volatile(
 201                 "       basr    %0,0\n"
 202                 "0:     ahi     %0,1f-0b\n"
 203                 "       st      %0,%O1+4(%R1)\n"
 204                 "       lpsw    %1\n"
 205                 "1:"
 206                 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
 207 #else /* CONFIG_64BIT */
 208         asm volatile(
 209                 "       larl    %0,1f\n"
 210                 "       stg     %0,%O1+8(%R1)\n"
 211                 "       lpswe   %1\n"
 212                 "1:"
 213                 : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
 214 #endif /* CONFIG_64BIT */
 215 }
 216
 217 /*
 218  * Rewind PSW instruction address by specified number of bytes.
 219  */
 220 static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
 221 {
 222 #ifndef CONFIG_64BIT
 223         if (psw.addr & PSW_ADDR_AMODE)
 224                 /* 31 bit mode */
 225                 return (psw.addr - ilc) | PSW_ADDR_AMODE;
 226         /* 24 bit mode */
 227         return (psw.addr - ilc) & ((1UL << 24) - 1);
 228 #else
 229         unsigned long mask;
 230
 231         mask = (psw.mask & PSW_MASK_EA) ? -1UL :
 232                (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
 233                                           (1UL << 24) - 1;
 234         return (psw.addr - ilc) & mask;
 235 #endif
 236 }
 237
 238 /*
 239  * Function to drop a processor into disabled wait state
 240  */
 241 static inline void __noreturn disabled_wait(unsigned long code)
 242 {
 243         unsigned long ctl_buf;
 244         psw_t dw_psw;
 245
 246         dw_psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
 247         dw_psw.addr = code;
 248         /*
 249          * Store status and then load disabled wait psw,
 250          * the processor is dead afterwards
 251          */
 252 #ifndef CONFIG_64BIT
 253         asm volatile(
 254                 "       stctl   0,0,0(%2)\n"
 255                 "       ni      0(%2),0xef\n"   /* switch off protection */
 256                 "       lctl    0,0,0(%2)\n"
 257                 "       stpt    0xd8\n"         /* store timer */
 258                 "       stckc   0xe0\n"         /* store clock comparator */
 259                 "       stpx    0x108\n"        /* store prefix register */
 260                 "       stam    0,15,0x120\n"   /* store access registers */
 261                 "       std     0,0x160\n"      /* store f0 */
 262                 "       std     2,0x168\n"      /* store f2 */
 263                 "       std     4,0x170\n"      /* store f4 */
 264                 "       std     6,0x178\n"      /* store f6 */
 265                 "       stm     0,15,0x180\n"   /* store general registers */
 266                 "       stctl   0,15,0x1c0\n"   /* store control registers */
 267                 "       oi      0x1c0,0x10\n"   /* fake protection bit */
 268                 "       lpsw    0(%1)"
 269                 : "=m" (ctl_buf)
 270                 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc");
 271 #else /* CONFIG_64BIT */
 272         asm volatile(
 273                 "       stctg   0,0,0(%2)\n"
 274                 "       ni      4(%2),0xef\n"   /* switch off protection */
 275                 "       lctlg   0,0,0(%2)\n"
 276                 "       lghi    1,0x1000\n"
 277                 "       stpt    0x328(1)\n"     /* store timer */
 278                 "       stckc   0x330(1)\n"     /* store clock comparator */
 279                 "       stpx    0x318(1)\n"     /* store prefix register */
 280                 "       stam    0,15,0x340(1)\n"/* store access registers */
 281                 "       stfpc   0x31c(1)\n"     /* store fpu control */
 282                 "       std     0,0x200(1)\n"   /* store f0 */
 283                 "       std     1,0x208(1)\n"   /* store f1 */
 284                 "       std     2,0x210(1)\n"   /* store f2 */
 285                 "       std     3,0x218(1)\n"   /* store f3 */
 286                 "       std     4,0x220(1)\n"   /* store f4 */
 287                 "       std     5,0x228(1)\n"   /* store f5 */
 288                 "       std     6,0x230(1)\n"   /* store f6 */
 289                 "       std     7,0x238(1)\n"   /* store f7 */
 290                 "       std     8,0x240(1)\n"   /* store f8 */
 291                 "       std     9,0x248(1)\n"   /* store f9 */
 292                 "       std     10,0x250(1)\n"  /* store f10 */
 293                 "       std     11,0x258(1)\n"  /* store f11 */
 294                 "       std     12,0x260(1)\n"  /* store f12 */
 295                 "       std     13,0x268(1)\n"  /* store f13 */
 296                 "       std     14,0x270(1)\n"  /* store f14 */
 297                 "       std     15,0x278(1)\n"  /* store f15 */
 298                 "       stmg    0,15,0x280(1)\n"/* store general registers */
 299                 "       stctg   0,15,0x380(1)\n"/* store control registers */
 300                 "       oi      0x384(1),0x10\n"/* fake protection bit */
 301                 "       lpswe   0(%1)"
 302                 : "=m" (ctl_buf)
 303                 : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1");
 304 #endif /* CONFIG_64BIT */
 305         while (1);
 306 }
 307
 308 /*
 309  * Use to set psw mask except for the first byte which
 310  * won't be changed by this function.
 311  */
 312 static inline void
 313 __set_psw_mask(unsigned long mask)
 314 {
 315         __load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8)));
 316 }
 317
 318 #define local_mcck_enable() \
 319         __set_psw_mask(psw_kernel_bits | PSW_MASK_DAT | PSW_MASK_MCHECK)
 320 #define local_mcck_disable() \
 321         __set_psw_mask(psw_kernel_bits | PSW_MASK_DAT)
 322
 323 /*
 324  * Basic Machine Check/Program Check Handler.
 325  */
 326
 327 extern void s390_base_mcck_handler(void);
 328 extern void s390_base_pgm_handler(void);
 329 extern void s390_base_ext_handler(void);
 330
 331 extern void (*s390_base_mcck_handler_fn)(void);
 332 extern void (*s390_base_pgm_handler_fn)(void);
 333 extern void (*s390_base_ext_handler_fn)(void);
 334
 335 #define ARCH_LOW_ADDRESS_LIMIT  0x7fffffffUL
 336
 337 /*
 338  * Helper macro for exception table entries
 339  */
 340 #ifndef CONFIG_64BIT
 341 #define EX_TABLE(_fault,_target)                        \
 342         ".section __ex_table,\"a\"\n"                   \
 343         "       .align 4\n"                             \
 344         "       .long  " #_fault "," #_target "\n"      \
 345         ".previous\n"
 346 #else
 347 #define EX_TABLE(_fault,_target)                        \
 348         ".section __ex_table,\"a\"\n"                   \
 349         "       .align 8\n"                             \
 350         "       .quad  " #_fault "," #_target "\n"      \
 351         ".previous\n"
 352 #endif
 353
 354 #endif                                 /* __ASM_S390_PROCESSOR_H           */