arch/s390/include/asm/sigp.h

   1 /*
   2  *  Routines and structures for signalling other processors.
   3  *
   4  *    Copyright IBM Corp. 1999,2010
   5  *    Author(s): Denis Joseph Barrow,
   6  *               Martin Schwidefsky <schwidefsky@de.ibm.com>,
   7  *               Heiko Carstens <heiko.carstens@de.ibm.com>,
   8  */
   9
  10 #ifndef __ASM_SIGP_H
  11 #define __ASM_SIGP_H
  12
  13 #include <asm/system.h>
  14
  15 /* Get real cpu address from logical cpu number. */
  16 extern unsigned short __cpu_logical_map[];
  17
  18 static inline int cpu_logical_map(int cpu)
  19 {
  20 #ifdef CONFIG_SMP
  21         return __cpu_logical_map[cpu];
  22 #else
  23         return stap();
  24 #endif
  25 }
  26
  27 enum {
  28         sigp_unassigned=0x0,
  29         sigp_sense,
  30         sigp_external_call,
  31         sigp_emergency_signal,
  32         sigp_start,
  33         sigp_stop,
  34         sigp_restart,
  35         sigp_unassigned1,
  36         sigp_unassigned2,
  37         sigp_stop_and_store_status,
  38         sigp_unassigned3,
  39         sigp_initial_cpu_reset,
  40         sigp_cpu_reset,
  41         sigp_set_prefix,
  42         sigp_store_status_at_address,
  43         sigp_store_extended_status_at_address
  44 };
  45
  46 enum {
  47         sigp_order_code_accepted=0,
  48         sigp_status_stored,
  49         sigp_busy,
  50         sigp_not_operational
  51 };
  52
  53 /*
  54  * Definitions for external call.
  55  */
  56 enum {
  57         ec_schedule = 0,
  58         ec_call_function,
  59         ec_call_function_single,
  60         ec_bit_last
  61 };
  62
  63 /*
  64  * Signal processor.
  65  */
  66 static inline int raw_sigp(u16 cpu, int order)
  67 {
  68         register unsigned long reg1 asm ("1") = 0;
  69         int ccode;
  70
  71         asm volatile(
  72                 "       sigp    %1,%2,0(%3)\n"
  73                 "       ipm     %0\n"
  74                 "       srl     %0,28\n"
  75                 :       "=d"    (ccode)
  76                 : "d" (reg1), "d" (cpu),
  77                   "a" (order) : "cc" , "memory");
  78         return ccode;
  79 }
  80
  81 /*
  82  * Signal processor with parameter.
  83  */
  84 static inline int raw_sigp_p(u32 parameter, u16 cpu, int order)
  85 {
  86         register unsigned int reg1 asm ("1") = parameter;
  87         int ccode;
  88
  89         asm volatile(
  90                 "       sigp    %1,%2,0(%3)\n"
  91                 "       ipm     %0\n"
  92                 "       srl     %0,28\n"
  93                 : "=d" (ccode)
  94                 : "d" (reg1), "d" (cpu),
  95                   "a" (order) : "cc" , "memory");
  96         return ccode;
  97 }
  98
  99 /*
 100  * Signal processor with parameter and return status.
 101  */
 102 static inline int raw_sigp_ps(u32 *status, u32 parm, u16 cpu, int order)
 103 {
 104         register unsigned int reg1 asm ("1") = parm;
 105         int ccode;
 106
 107         asm volatile(
 108                 "       sigp    %1,%2,0(%3)\n"
 109                 "       ipm     %0\n"
 110                 "       srl     %0,28\n"
 111                 : "=d" (ccode), "+d" (reg1)
 112                 : "d" (cpu), "a" (order)
 113                 : "cc" , "memory");
 114         *status = reg1;
 115         return ccode;
 116 }
 117
 118 static inline int sigp(int cpu, int order)
 119 {
 120         return raw_sigp(cpu_logical_map(cpu), order);
 121 }
 122
 123 static inline int sigp_p(u32 parameter, int cpu, int order)
 124 {
 125         return raw_sigp_p(parameter, cpu_logical_map(cpu), order);
 126 }
 127
 128 static inline int sigp_ps(u32 *status, u32 parm, int cpu, int order)
 129 {
 130         return raw_sigp_ps(status, parm, cpu_logical_map(cpu), order);
 131 }
 132
 133 #endif /* __ASM_SIGP_H */