arch/s390/include/asm/spinlock.h

   1 /*
   2  *  S390 version
   3  *    Copyright IBM Corp. 1999
   4  *    Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com)
   5  *
   6  *  Derived from "include/asm-i386/spinlock.h"
   7  */
   8
   9 #ifndef __ASM_SPINLOCK_H
  10 #define __ASM_SPINLOCK_H
  11
  12 #include <linux/smp.h>
  13 #include <asm/atomic_ops.h>
  14 #include <asm/barrier.h>
  15 #include <asm/processor.h>
  16
  17 #define SPINLOCK_LOCKVAL (S390_lowcore.spinlock_lockval)
  18
  19 extern int spin_retry;
  20
  21 #ifndef CONFIG_SMP
  22 static inline bool arch_vcpu_is_preempted(int cpu) { return false; }
  23 #else
  24 bool arch_vcpu_is_preempted(int cpu);
  25 #endif
  26
  27 #define vcpu_is_preempted arch_vcpu_is_preempted
  28
  29 /*
  30  * Simple spin lock operations.  There are two variants, one clears IRQ's
  31  * on the local processor, one does not.
  32  *
  33  * We make no fairness assumptions. They have a cost.
  34  *
  35  * (the type definitions are in asm/spinlock_types.h)
  36  */
  37
  38 void arch_lock_relax(int cpu);
  39 void arch_spin_relax(arch_spinlock_t *lock);
  40
  41 void arch_spin_lock_wait(arch_spinlock_t *);
  42 int arch_spin_trylock_retry(arch_spinlock_t *);
  43 void arch_spin_lock_setup(int cpu);
  44
  45 static inline u32 arch_spin_lockval(int cpu)
  46 {
  47         return cpu + 1;
  48 }
  49
  50 static inline int arch_spin_value_unlocked(arch_spinlock_t lock)
  51 {
  52         return lock.lock == 0;
  53 }
  54
  55 static inline int arch_spin_is_locked(arch_spinlock_t *lp)
  56 {
  57         return READ_ONCE(lp->lock) != 0;
  58 }
  59
  60 static inline int arch_spin_trylock_once(arch_spinlock_t *lp)
  61 {
  62         barrier();
  63         return likely(__atomic_cmpxchg_bool(&lp->lock, 0, SPINLOCK_LOCKVAL));
  64 }
  65
  66 static inline void arch_spin_lock(arch_spinlock_t *lp)
  67 {
  68         if (!arch_spin_trylock_once(lp))
  69                 arch_spin_lock_wait(lp);
  70 }
  71
  72 static inline void arch_spin_lock_flags(arch_spinlock_t *lp,
  73                                         unsigned long flags)
  74 {
  75         if (!arch_spin_trylock_once(lp))
  76                 arch_spin_lock_wait(lp);
  77 }
  78
  79 static inline int arch_spin_trylock(arch_spinlock_t *lp)
  80 {
  81         if (!arch_spin_trylock_once(lp))
  82                 return arch_spin_trylock_retry(lp);
  83         return 1;
  84 }
  85
  86 static inline void arch_spin_unlock(arch_spinlock_t *lp)
  87 {
  88         typecheck(int, lp->lock);
  89         asm volatile(
  90 #ifdef CONFIG_HAVE_MARCH_ZEC12_FEATURES
  91                 "       .long   0xb2fa0070\n"   /* NIAI 7 */
  92 #endif
  93                 "       sth     %1,%0\n"
  94                 : "=Q" (((unsigned short *) &lp->lock)[1])
  95                 : "d" (0) : "cc", "memory");
  96 }
  97
  98 /*
  99  * Read-write spinlocks, allowing multiple readers
 100  * but only one writer.
 101  *
 102  * NOTE! it is quite common to have readers in interrupts
 103  * but no interrupt writers. For those circumstances we
 104  * can "mix" irq-safe locks - any writer needs to get a
 105  * irq-safe write-lock, but readers can get non-irqsafe
 106  * read-locks.
 107  */
 108
 109 /**
 110  * read_can_lock - would read_trylock() succeed?
 111  * @lock: the rwlock in question.
 112  */
 113 #define arch_read_can_lock(x) ((int)(x)->lock >= 0)
 114
 115 /**
 116  * write_can_lock - would write_trylock() succeed?
 117  * @lock: the rwlock in question.
 118  */
 119 #define arch_write_can_lock(x) ((x)->lock == 0)
 120
 121 extern int _raw_read_trylock_retry(arch_rwlock_t *lp);
 122 extern int _raw_write_trylock_retry(arch_rwlock_t *lp);
 123
 124 #define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
 125 #define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
 126
 127 static inline int arch_read_trylock_once(arch_rwlock_t *rw)
 128 {
 129         int old = ACCESS_ONCE(rw->lock);
 130         return likely(old >= 0 &&
 131                       __atomic_cmpxchg_bool(&rw->lock, old, old + 1));
 132 }
 133
 134 static inline int arch_write_trylock_once(arch_rwlock_t *rw)
 135 {
 136         int old = ACCESS_ONCE(rw->lock);
 137         return likely(old == 0 &&
 138                       __atomic_cmpxchg_bool(&rw->lock, 0, 0x80000000));
 139 }
 140
 141 #ifdef CONFIG_HAVE_MARCH_Z196_FEATURES
 142
 143 #define __RAW_OP_OR     "lao"
 144 #define __RAW_OP_AND    "lan"
 145 #define __RAW_OP_ADD    "laa"
 146
 147 #define __RAW_LOCK(ptr, op_val, op_string)              \
 148 ({                                                      \
 149         int old_val;                                    \
 150                                                         \
 151         typecheck(int *, ptr);                          \
 152         asm volatile(                                   \
 153                 op_string "     %0,%2,%1\n"             \
 154                 "bcr    14,0\n"                         \
 155                 : "=d" (old_val), "+Q" (*ptr)           \
 156                 : "d" (op_val)                          \
 157                 : "cc", "memory");                      \
 158         old_val;                                        \
 159 })
 160
 161 #define __RAW_UNLOCK(ptr, op_val, op_string)            \
 162 ({                                                      \
 163         int old_val;                                    \
 164                                                         \
 165         typecheck(int *, ptr);                          \
 166         asm volatile(                                   \
 167                 op_string "     %0,%2,%1\n"             \
 168                 : "=d" (old_val), "+Q" (*ptr)           \
 169                 : "d" (op_val)                          \
 170                 : "cc", "memory");                      \
 171         old_val;                                        \
 172 })
 173
 174 extern void _raw_read_lock_wait(arch_rwlock_t *lp);
 175 extern void _raw_write_lock_wait(arch_rwlock_t *lp, int prev);
 176
 177 static inline void arch_read_lock(arch_rwlock_t *rw)
 178 {
 179         int old;
 180
 181         old = __RAW_LOCK(&rw->lock, 1, __RAW_OP_ADD);
 182         if (old < 0)
 183                 _raw_read_lock_wait(rw);
 184 }
 185
 186 static inline void arch_read_unlock(arch_rwlock_t *rw)
 187 {
 188         __RAW_UNLOCK(&rw->lock, -1, __RAW_OP_ADD);
 189 }
 190
 191 static inline void arch_write_lock(arch_rwlock_t *rw)
 192 {
 193         int old;
 194
 195         old = __RAW_LOCK(&rw->lock, 0x80000000, __RAW_OP_OR);
 196         if (old != 0)
 197                 _raw_write_lock_wait(rw, old);
 198         rw->owner = SPINLOCK_LOCKVAL;
 199 }
 200
 201 static inline void arch_write_unlock(arch_rwlock_t *rw)
 202 {
 203         rw->owner = 0;
 204         __RAW_UNLOCK(&rw->lock, 0x7fffffff, __RAW_OP_AND);
 205 }
 206
 207 #else /* CONFIG_HAVE_MARCH_Z196_FEATURES */
 208
 209 extern void _raw_read_lock_wait(arch_rwlock_t *lp);
 210 extern void _raw_write_lock_wait(arch_rwlock_t *lp);
 211
 212 static inline void arch_read_lock(arch_rwlock_t *rw)
 213 {
 214         if (!arch_read_trylock_once(rw))
 215                 _raw_read_lock_wait(rw);
 216 }
 217
 218 static inline void arch_read_unlock(arch_rwlock_t *rw)
 219 {
 220         int old;
 221
 222         do {
 223                 old = ACCESS_ONCE(rw->lock);
 224         } while (!__atomic_cmpxchg_bool(&rw->lock, old, old - 1));
 225 }
 226
 227 static inline void arch_write_lock(arch_rwlock_t *rw)
 228 {
 229         if (!arch_write_trylock_once(rw))
 230                 _raw_write_lock_wait(rw);
 231         rw->owner = SPINLOCK_LOCKVAL;
 232 }
 233
 234 static inline void arch_write_unlock(arch_rwlock_t *rw)
 235 {
 236         typecheck(int, rw->lock);
 237
 238         rw->owner = 0;
 239         asm volatile(
 240                 "st     %1,%0\n"
 241                 : "+Q" (rw->lock)
 242                 : "d" (0)
 243                 : "cc", "memory");
 244 }
 245
 246 #endif /* CONFIG_HAVE_MARCH_Z196_FEATURES */
 247
 248 static inline int arch_read_trylock(arch_rwlock_t *rw)
 249 {
 250         if (!arch_read_trylock_once(rw))
 251                 return _raw_read_trylock_retry(rw);
 252         return 1;
 253 }
 254
 255 static inline int arch_write_trylock(arch_rwlock_t *rw)
 256 {
 257         if (!arch_write_trylock_once(rw) && !_raw_write_trylock_retry(rw))
 258                 return 0;
 259         rw->owner = SPINLOCK_LOCKVAL;
 260         return 1;
 261 }
 262
 263 static inline void arch_read_relax(arch_rwlock_t *rw)
 264 {
 265         arch_lock_relax(rw->owner);
 266 }
 267
 268 static inline void arch_write_relax(arch_rwlock_t *rw)
 269 {
 270         arch_lock_relax(rw->owner);
 271 }
 272
 273 #endif /* __ASM_SPINLOCK_H */