]>
git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blob - arch/s390/kernel/dis.c
2 * Disassemble s390 instructions.
4 * Copyright IBM Corp. 2007
5 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
8 #include <linux/sched.h>
9 #include <linux/kernel.h>
10 #include <linux/string.h>
11 #include <linux/errno.h>
12 #include <linux/ptrace.h>
13 #include <linux/timer.h>
15 #include <linux/smp.h>
16 #include <linux/init.h>
17 #include <linux/interrupt.h>
18 #include <linux/delay.h>
19 #include <linux/module.h>
20 #include <linux/kallsyms.h>
21 #include <linux/reboot.h>
22 #include <linux/kprobes.h>
23 #include <linux/kdebug.h>
25 #include <asm/uaccess.h>
28 #include <linux/atomic.h>
29 #include <asm/mathemu.h>
30 #include <asm/cpcmd.h>
31 #include <asm/lowcore.h>
32 #include <asm/debug.h>
36 #define ONELONG "%08lx: "
37 #else /* CONFIG_64BIT */
38 #define ONELONG "%016lx: "
39 #endif /* CONFIG_64BIT */
42 UNUSED
, /* Indicates the end of the operand list */
43 R_8
, /* GPR starting at position 8 */
44 R_12
, /* GPR starting at position 12 */
45 R_16
, /* GPR starting at position 16 */
46 R_20
, /* GPR starting at position 20 */
47 R_24
, /* GPR starting at position 24 */
48 R_28
, /* GPR starting at position 28 */
49 R_32
, /* GPR starting at position 32 */
50 F_8
, /* FPR starting at position 8 */
51 F_12
, /* FPR starting at position 12 */
52 F_16
, /* FPR starting at position 16 */
53 F_20
, /* FPR starting at position 16 */
54 F_24
, /* FPR starting at position 24 */
55 F_28
, /* FPR starting at position 28 */
56 F_32
, /* FPR starting at position 32 */
57 A_8
, /* Access reg. starting at position 8 */
58 A_12
, /* Access reg. starting at position 12 */
59 A_24
, /* Access reg. starting at position 24 */
60 A_28
, /* Access reg. starting at position 28 */
61 C_8
, /* Control reg. starting at position 8 */
62 C_12
, /* Control reg. starting at position 12 */
63 B_16
, /* Base register starting at position 16 */
64 B_32
, /* Base register starting at position 32 */
65 X_12
, /* Index register starting at position 12 */
66 D_20
, /* Displacement starting at position 20 */
67 D_36
, /* Displacement starting at position 36 */
68 D20_20
, /* 20 bit displacement starting at 20 */
69 L4_8
, /* 4 bit length starting at position 8 */
70 L4_12
, /* 4 bit length starting at position 12 */
71 L8_8
, /* 8 bit length starting at position 8 */
72 U4_8
, /* 4 bit unsigned value starting at 8 */
73 U4_12
, /* 4 bit unsigned value starting at 12 */
74 U4_16
, /* 4 bit unsigned value starting at 16 */
75 U4_20
, /* 4 bit unsigned value starting at 20 */
76 U4_24
, /* 4 bit unsigned value starting at 24 */
77 U4_28
, /* 4 bit unsigned value starting at 28 */
78 U4_32
, /* 4 bit unsigned value starting at 32 */
79 U4_36
, /* 4 bit unsigned value starting at 36 */
80 U8_8
, /* 8 bit unsigned value starting at 8 */
81 U8_16
, /* 8 bit unsigned value starting at 16 */
82 U8_24
, /* 8 bit unsigned value starting at 24 */
83 U8_32
, /* 8 bit unsigned value starting at 32 */
84 I8_8
, /* 8 bit signed value starting at 8 */
85 I8_32
, /* 8 bit signed value starting at 32 */
86 J12_12
, /* PC relative offset at 12 */
87 I16_16
, /* 16 bit signed value starting at 16 */
88 I16_32
, /* 32 bit signed value starting at 16 */
89 U16_16
, /* 16 bit unsigned value starting at 16 */
90 U16_32
, /* 32 bit unsigned value starting at 16 */
91 J16_16
, /* PC relative jump offset at 16 */
92 J16_32
, /* PC relative offset at 16 */
93 I24_24
, /* 24 bit signed value starting at 24 */
94 J32_16
, /* PC relative long offset at 16 */
95 I32_16
, /* 32 bit signed value starting at 16 */
96 U32_16
, /* 32 bit unsigned value starting at 16 */
97 M_16
, /* 4 bit optional mask starting at 16 */
98 M_20
, /* 4 bit optional mask starting at 20 */
99 RO_28
, /* optional GPR starting at position 28 */
103 * Enumeration of the different instruction formats.
104 * For details consult the principles of operation.
111 INSTR_RIE_R0IU
, INSTR_RIE_R0UU
, INSTR_RIE_RRP
, INSTR_RIE_RRPU
,
112 INSTR_RIE_RRUUU
, INSTR_RIE_RUPI
, INSTR_RIE_RUPU
, INSTR_RIE_RRI0
,
113 INSTR_RIL_RI
, INSTR_RIL_RP
, INSTR_RIL_RU
, INSTR_RIL_UP
,
114 INSTR_RIS_R0RDU
, INSTR_RIS_R0UU
, INSTR_RIS_RURDI
, INSTR_RIS_RURDU
,
115 INSTR_RI_RI
, INSTR_RI_RP
, INSTR_RI_RU
, INSTR_RI_UP
,
116 INSTR_RRE_00
, INSTR_RRE_0R
, INSTR_RRE_AA
, INSTR_RRE_AR
, INSTR_RRE_F0
,
117 INSTR_RRE_FF
, INSTR_RRE_FR
, INSTR_RRE_R0
, INSTR_RRE_RA
, INSTR_RRE_RF
,
118 INSTR_RRE_RR
, INSTR_RRE_RR_OPT
,
119 INSTR_RRF_0UFF
, INSTR_RRF_F0FF
, INSTR_RRF_F0FF2
, INSTR_RRF_F0FR
,
120 INSTR_RRF_FFRU
, INSTR_RRF_FUFF
, INSTR_RRF_FUFF2
, INSTR_RRF_M0RR
,
121 INSTR_RRF_R0RR
, INSTR_RRF_R0RR2
, INSTR_RRF_RMRR
, INSTR_RRF_RURR
,
122 INSTR_RRF_U0FF
, INSTR_RRF_U0RF
, INSTR_RRF_U0RR
, INSTR_RRF_UUFF
,
123 INSTR_RRF_UUFR
, INSTR_RRF_UURF
,
124 INSTR_RRR_F0FF
, INSTR_RRS_RRRDU
,
125 INSTR_RR_FF
, INSTR_RR_R0
, INSTR_RR_RR
, INSTR_RR_U0
, INSTR_RR_UR
,
126 INSTR_RSE_CCRD
, INSTR_RSE_RRRD
, INSTR_RSE_RURD
,
128 INSTR_RSL_LRDFU
, INSTR_RSL_R0RD
,
129 INSTR_RSY_AARD
, INSTR_RSY_CCRD
, INSTR_RSY_RRRD
, INSTR_RSY_RURD
,
131 INSTR_RS_AARD
, INSTR_RS_CCRD
, INSTR_RS_R0RD
, INSTR_RS_RRRD
,
133 INSTR_RXE_FRRD
, INSTR_RXE_RRRD
,
135 INSTR_RXY_FRRD
, INSTR_RXY_RRRD
, INSTR_RXY_URRD
,
136 INSTR_RX_FRRD
, INSTR_RX_RRRD
, INSTR_RX_URRD
,
137 INSTR_SIL_RDI
, INSTR_SIL_RDU
,
138 INSTR_SIY_IRD
, INSTR_SIY_URD
,
142 INSTR_SSF_RRDRD
, INSTR_SSF_RRDRD2
,
143 INSTR_SS_L0RDRD
, INSTR_SS_LIRDRD
, INSTR_SS_LLRDRD
, INSTR_SS_RRRDRD
,
144 INSTR_SS_RRRDRD2
, INSTR_SS_RRRDRD3
,
145 INSTR_S_00
, INSTR_S_RD
,
148 static const struct s390_operand operands
[] =
150 [UNUSED
] = { 0, 0, 0 },
151 [R_8
] = { 4, 8, OPERAND_GPR
},
152 [R_12
] = { 4, 12, OPERAND_GPR
},
153 [R_16
] = { 4, 16, OPERAND_GPR
},
154 [R_20
] = { 4, 20, OPERAND_GPR
},
155 [R_24
] = { 4, 24, OPERAND_GPR
},
156 [R_28
] = { 4, 28, OPERAND_GPR
},
157 [R_32
] = { 4, 32, OPERAND_GPR
},
158 [F_8
] = { 4, 8, OPERAND_FPR
},
159 [F_12
] = { 4, 12, OPERAND_FPR
},
160 [F_16
] = { 4, 16, OPERAND_FPR
},
161 [F_20
] = { 4, 16, OPERAND_FPR
},
162 [F_24
] = { 4, 24, OPERAND_FPR
},
163 [F_28
] = { 4, 28, OPERAND_FPR
},
164 [F_32
] = { 4, 32, OPERAND_FPR
},
165 [A_8
] = { 4, 8, OPERAND_AR
},
166 [A_12
] = { 4, 12, OPERAND_AR
},
167 [A_24
] = { 4, 24, OPERAND_AR
},
168 [A_28
] = { 4, 28, OPERAND_AR
},
169 [C_8
] = { 4, 8, OPERAND_CR
},
170 [C_12
] = { 4, 12, OPERAND_CR
},
171 [B_16
] = { 4, 16, OPERAND_BASE
| OPERAND_GPR
},
172 [B_32
] = { 4, 32, OPERAND_BASE
| OPERAND_GPR
},
173 [X_12
] = { 4, 12, OPERAND_INDEX
| OPERAND_GPR
},
174 [D_20
] = { 12, 20, OPERAND_DISP
},
175 [D_36
] = { 12, 36, OPERAND_DISP
},
176 [D20_20
] = { 20, 20, OPERAND_DISP
| OPERAND_SIGNED
},
177 [L4_8
] = { 4, 8, OPERAND_LENGTH
},
178 [L4_12
] = { 4, 12, OPERAND_LENGTH
},
179 [L8_8
] = { 8, 8, OPERAND_LENGTH
},
180 [U4_8
] = { 4, 8, 0 },
181 [U4_12
] = { 4, 12, 0 },
182 [U4_16
] = { 4, 16, 0 },
183 [U4_20
] = { 4, 20, 0 },
184 [U4_24
] = { 4, 24, 0 },
185 [U4_28
] = { 4, 28, 0 },
186 [U4_32
] = { 4, 32, 0 },
187 [U4_36
] = { 4, 36, 0 },
188 [U8_8
] = { 8, 8, 0 },
189 [U8_16
] = { 8, 16, 0 },
190 [U8_24
] = { 8, 24, 0 },
191 [U8_32
] = { 8, 32, 0 },
192 [J12_12
] = { 12, 12, OPERAND_PCREL
},
193 [I16_16
] = { 16, 16, OPERAND_SIGNED
},
194 [U16_16
] = { 16, 16, 0 },
195 [U16_32
] = { 16, 32, 0 },
196 [J16_16
] = { 16, 16, OPERAND_PCREL
},
197 [J16_32
] = { 16, 32, OPERAND_PCREL
},
198 [I16_32
] = { 16, 32, OPERAND_SIGNED
},
199 [I24_24
] = { 24, 24, OPERAND_SIGNED
},
200 [J32_16
] = { 32, 16, OPERAND_PCREL
},
201 [I32_16
] = { 32, 16, OPERAND_SIGNED
},
202 [U32_16
] = { 32, 16, 0 },
203 [M_16
] = { 4, 16, 0 },
204 [M_20
] = { 4, 20, 0 },
205 [RO_28
] = { 4, 28, OPERAND_GPR
}
208 static const unsigned char formats
[][7] = {
209 [INSTR_E
] = { 0xff, 0,0,0,0,0,0 },
210 [INSTR_IE_UU
] = { 0xff, U4_24
,U4_28
,0,0,0,0 },
211 [INSTR_MII_UPI
] = { 0xff, U4_8
,J12_12
,I24_24
},
212 [INSTR_RIE_R0IU
] = { 0xff, R_8
,I16_16
,U4_32
,0,0,0 },
213 [INSTR_RIE_R0UU
] = { 0xff, R_8
,U16_16
,U4_32
,0,0,0 },
214 [INSTR_RIE_RRI0
] = { 0xff, R_8
,R_12
,I16_16
,0,0,0 },
215 [INSTR_RIE_RRPU
] = { 0xff, R_8
,R_12
,U4_32
,J16_16
,0,0 },
216 [INSTR_RIE_RRP
] = { 0xff, R_8
,R_12
,J16_16
,0,0,0 },
217 [INSTR_RIE_RRUUU
] = { 0xff, R_8
,R_12
,U8_16
,U8_24
,U8_32
,0 },
218 [INSTR_RIE_RUPI
] = { 0xff, R_8
,I8_32
,U4_12
,J16_16
,0,0 },
219 [INSTR_RIE_RUPU
] = { 0xff, R_8
,U8_32
,U4_12
,J16_16
,0,0 },
220 [INSTR_RIL_RI
] = { 0x0f, R_8
,I32_16
,0,0,0,0 },
221 [INSTR_RIL_RP
] = { 0x0f, R_8
,J32_16
,0,0,0,0 },
222 [INSTR_RIL_RU
] = { 0x0f, R_8
,U32_16
,0,0,0,0 },
223 [INSTR_RIL_UP
] = { 0x0f, U4_8
,J32_16
,0,0,0,0 },
224 [INSTR_RIS_R0RDU
] = { 0xff, R_8
,U8_32
,D_20
,B_16
,0,0 },
225 [INSTR_RIS_RURDI
] = { 0xff, R_8
,I8_32
,U4_12
,D_20
,B_16
,0 },
226 [INSTR_RIS_RURDU
] = { 0xff, R_8
,U8_32
,U4_12
,D_20
,B_16
,0 },
227 [INSTR_RI_RI
] = { 0x0f, R_8
,I16_16
,0,0,0,0 },
228 [INSTR_RI_RP
] = { 0x0f, R_8
,J16_16
,0,0,0,0 },
229 [INSTR_RI_RU
] = { 0x0f, R_8
,U16_16
,0,0,0,0 },
230 [INSTR_RI_UP
] = { 0x0f, U4_8
,J16_16
,0,0,0,0 },
231 [INSTR_RRE_00
] = { 0xff, 0,0,0,0,0,0 },
232 [INSTR_RRE_0R
] = { 0xff, R_28
,0,0,0,0,0 },
233 [INSTR_RRE_AA
] = { 0xff, A_24
,A_28
,0,0,0,0 },
234 [INSTR_RRE_AR
] = { 0xff, A_24
,R_28
,0,0,0,0 },
235 [INSTR_RRE_F0
] = { 0xff, F_24
,0,0,0,0,0 },
236 [INSTR_RRE_FF
] = { 0xff, F_24
,F_28
,0,0,0,0 },
237 [INSTR_RRE_FR
] = { 0xff, F_24
,R_28
,0,0,0,0 },
238 [INSTR_RRE_R0
] = { 0xff, R_24
,0,0,0,0,0 },
239 [INSTR_RRE_RA
] = { 0xff, R_24
,A_28
,0,0,0,0 },
240 [INSTR_RRE_RF
] = { 0xff, R_24
,F_28
,0,0,0,0 },
241 [INSTR_RRE_RR
] = { 0xff, R_24
,R_28
,0,0,0,0 },
242 [INSTR_RRE_RR_OPT
]= { 0xff, R_24
,RO_28
,0,0,0,0 },
243 [INSTR_RRF_0UFF
] = { 0xff, F_24
,F_28
,U4_20
,0,0,0 },
244 [INSTR_RRF_F0FF2
] = { 0xff, F_24
,F_16
,F_28
,0,0,0 },
245 [INSTR_RRF_F0FF
] = { 0xff, F_16
,F_24
,F_28
,0,0,0 },
246 [INSTR_RRF_F0FR
] = { 0xff, F_24
,F_16
,R_28
,0,0,0 },
247 [INSTR_RRF_FFRU
] = { 0xff, F_24
,F_16
,R_28
,U4_20
,0,0 },
248 [INSTR_RRF_FUFF
] = { 0xff, F_24
,F_16
,F_28
,U4_20
,0,0 },
249 [INSTR_RRF_FUFF2
] = { 0xff, F_24
,F_28
,F_16
,U4_20
,0,0 },
250 [INSTR_RRF_M0RR
] = { 0xff, R_24
,R_28
,M_16
,0,0,0 },
251 [INSTR_RRF_R0RR
] = { 0xff, R_24
,R_16
,R_28
,0,0,0 },
252 [INSTR_RRF_R0RR2
] = { 0xff, R_24
,R_28
,R_16
,0,0,0 },
253 [INSTR_RRF_RMRR
] = { 0xff, R_24
,R_16
,R_28
,M_20
,0,0 },
254 [INSTR_RRF_RURR
] = { 0xff, R_24
,R_28
,R_16
,U4_20
,0,0 },
255 [INSTR_RRF_U0FF
] = { 0xff, F_24
,U4_16
,F_28
,0,0,0 },
256 [INSTR_RRF_U0RF
] = { 0xff, R_24
,U4_16
,F_28
,0,0,0 },
257 [INSTR_RRF_U0RR
] = { 0xff, R_24
,R_28
,U4_16
,0,0,0 },
258 [INSTR_RRF_UUFF
] = { 0xff, F_24
,U4_16
,F_28
,U4_20
,0,0 },
259 [INSTR_RRF_UUFR
] = { 0xff, F_24
,U4_16
,R_28
,U4_20
,0,0 },
260 [INSTR_RRF_UURF
] = { 0xff, R_24
,U4_16
,F_28
,U4_20
,0,0 },
261 [INSTR_RRR_F0FF
] = { 0xff, F_24
,F_28
,F_16
,0,0,0 },
262 [INSTR_RRS_RRRDU
] = { 0xff, R_8
,R_12
,U4_32
,D_20
,B_16
,0 },
263 [INSTR_RR_FF
] = { 0xff, F_8
,F_12
,0,0,0,0 },
264 [INSTR_RR_R0
] = { 0xff, R_8
, 0,0,0,0,0 },
265 [INSTR_RR_RR
] = { 0xff, R_8
,R_12
,0,0,0,0 },
266 [INSTR_RR_U0
] = { 0xff, U8_8
, 0,0,0,0,0 },
267 [INSTR_RR_UR
] = { 0xff, U4_8
,R_12
,0,0,0,0 },
268 [INSTR_RSE_CCRD
] = { 0xff, C_8
,C_12
,D_20
,B_16
,0,0 },
269 [INSTR_RSE_RRRD
] = { 0xff, R_8
,R_12
,D_20
,B_16
,0,0 },
270 [INSTR_RSE_RURD
] = { 0xff, R_8
,U4_12
,D_20
,B_16
,0,0 },
271 [INSTR_RSI_RRP
] = { 0xff, R_8
,R_12
,J16_16
,0,0,0 },
272 [INSTR_RSL_LRDFU
] = { 0xff, F_32
,D_20
,L4_8
,B_16
,U4_36
,0 },
273 [INSTR_RSL_R0RD
] = { 0xff, D_20
,L4_8
,B_16
,0,0,0 },
274 [INSTR_RSY_AARD
] = { 0xff, A_8
,A_12
,D20_20
,B_16
,0,0 },
275 [INSTR_RSY_CCRD
] = { 0xff, C_8
,C_12
,D20_20
,B_16
,0,0 },
276 [INSTR_RSY_RDRM
] = { 0xff, R_8
,D20_20
,B_16
,U4_12
,0,0 },
277 [INSTR_RSY_RRRD
] = { 0xff, R_8
,R_12
,D20_20
,B_16
,0,0 },
278 [INSTR_RSY_RURD
] = { 0xff, R_8
,U4_12
,D20_20
,B_16
,0,0 },
279 [INSTR_RS_AARD
] = { 0xff, A_8
,A_12
,D_20
,B_16
,0,0 },
280 [INSTR_RS_CCRD
] = { 0xff, C_8
,C_12
,D_20
,B_16
,0,0 },
281 [INSTR_RS_R0RD
] = { 0xff, R_8
,D_20
,B_16
,0,0,0 },
282 [INSTR_RS_RRRD
] = { 0xff, R_8
,R_12
,D_20
,B_16
,0,0 },
283 [INSTR_RS_RURD
] = { 0xff, R_8
,U4_12
,D_20
,B_16
,0,0 },
284 [INSTR_RXE_FRRD
] = { 0xff, F_8
,D_20
,X_12
,B_16
,0,0 },
285 [INSTR_RXE_RRRD
] = { 0xff, R_8
,D_20
,X_12
,B_16
,0,0 },
286 [INSTR_RXF_FRRDF
] = { 0xff, F_32
,F_8
,D_20
,X_12
,B_16
,0 },
287 [INSTR_RXY_FRRD
] = { 0xff, F_8
,D20_20
,X_12
,B_16
,0,0 },
288 [INSTR_RXY_RRRD
] = { 0xff, R_8
,D20_20
,X_12
,B_16
,0,0 },
289 [INSTR_RXY_URRD
] = { 0xff, U4_8
,D20_20
,X_12
,B_16
,0,0 },
290 [INSTR_RX_FRRD
] = { 0xff, F_8
,D_20
,X_12
,B_16
,0,0 },
291 [INSTR_RX_RRRD
] = { 0xff, R_8
,D_20
,X_12
,B_16
,0,0 },
292 [INSTR_RX_URRD
] = { 0xff, U4_8
,D_20
,X_12
,B_16
,0,0 },
293 [INSTR_SIL_RDI
] = { 0xff, D_20
,B_16
,I16_32
,0,0,0 },
294 [INSTR_SIL_RDU
] = { 0xff, D_20
,B_16
,U16_32
,0,0,0 },
295 [INSTR_SIY_IRD
] = { 0xff, D20_20
,B_16
,I8_8
,0,0,0 },
296 [INSTR_SIY_URD
] = { 0xff, D20_20
,B_16
,U8_8
,0,0,0 },
297 [INSTR_SI_URD
] = { 0xff, D_20
,B_16
,U8_8
,0,0,0 },
298 [INSTR_SMI_U0RDP
] = { 0xff, U4_8
,J16_32
,D_20
,B_16
,0,0 },
299 [INSTR_SSE_RDRD
] = { 0xff, D_20
,B_16
,D_36
,B_32
,0,0 },
300 [INSTR_SSF_RRDRD
] = { 0x0f, D_20
,B_16
,D_36
,B_32
,R_8
,0 },
301 [INSTR_SSF_RRDRD2
]= { 0x0f, R_8
,D_20
,B_16
,D_36
,B_32
,0 },
302 [INSTR_SS_L0RDRD
] = { 0xff, D_20
,L8_8
,B_16
,D_36
,B_32
,0 },
303 [INSTR_SS_LIRDRD
] = { 0xff, D_20
,L4_8
,B_16
,D_36
,B_32
,U4_12
},
304 [INSTR_SS_LLRDRD
] = { 0xff, D_20
,L4_8
,B_16
,D_36
,L4_12
,B_32
},
305 [INSTR_SS_RRRDRD2
]= { 0xff, R_8
,D_20
,B_16
,R_12
,D_36
,B_32
},
306 [INSTR_SS_RRRDRD3
]= { 0xff, R_8
,R_12
,D_20
,B_16
,D_36
,B_32
},
307 [INSTR_SS_RRRDRD
] = { 0xff, D_20
,R_8
,B_16
,D_36
,B_32
,R_12
},
308 [INSTR_S_00
] = { 0xff, 0,0,0,0,0,0 },
309 [INSTR_S_RD
] = { 0xff, D_20
,B_16
,0,0,0,0 },
386 static char *long_insn_name
[] = {
387 [LONG_INSN_ALGHSIK
] = "alghsik",
388 [LONG_INSN_ALHHHR
] = "alhhhr",
389 [LONG_INSN_ALHHLR
] = "alhhlr",
390 [LONG_INSN_ALHSIK
] = "alhsik",
391 [LONG_INSN_ALSIHN
] = "alsihn",
392 [LONG_INSN_CDFBRA
] = "cdfbra",
393 [LONG_INSN_CDGBRA
] = "cdgbra",
394 [LONG_INSN_CDGTRA
] = "cdgtra",
395 [LONG_INSN_CDLFBR
] = "cdlfbr",
396 [LONG_INSN_CDLFTR
] = "cdlftr",
397 [LONG_INSN_CDLGBR
] = "cdlgbr",
398 [LONG_INSN_CDLGTR
] = "cdlgtr",
399 [LONG_INSN_CEFBRA
] = "cefbra",
400 [LONG_INSN_CEGBRA
] = "cegbra",
401 [LONG_INSN_CELFBR
] = "celfbr",
402 [LONG_INSN_CELGBR
] = "celgbr",
403 [LONG_INSN_CFDBRA
] = "cfdbra",
404 [LONG_INSN_CFEBRA
] = "cfebra",
405 [LONG_INSN_CFXBRA
] = "cfxbra",
406 [LONG_INSN_CGDBRA
] = "cgdbra",
407 [LONG_INSN_CGDTRA
] = "cgdtra",
408 [LONG_INSN_CGEBRA
] = "cgebra",
409 [LONG_INSN_CGXBRA
] = "cgxbra",
410 [LONG_INSN_CGXTRA
] = "cgxtra",
411 [LONG_INSN_CLFDBR
] = "clfdbr",
412 [LONG_INSN_CLFDTR
] = "clfdtr",
413 [LONG_INSN_CLFEBR
] = "clfebr",
414 [LONG_INSN_CLFHSI
] = "clfhsi",
415 [LONG_INSN_CLFXBR
] = "clfxbr",
416 [LONG_INSN_CLFXTR
] = "clfxtr",
417 [LONG_INSN_CLGDBR
] = "clgdbr",
418 [LONG_INSN_CLGDTR
] = "clgdtr",
419 [LONG_INSN_CLGEBR
] = "clgebr",
420 [LONG_INSN_CLGFRL
] = "clgfrl",
421 [LONG_INSN_CLGHRL
] = "clghrl",
422 [LONG_INSN_CLGHSI
] = "clghsi",
423 [LONG_INSN_CLGXBR
] = "clgxbr",
424 [LONG_INSN_CLGXTR
] = "clgxtr",
425 [LONG_INSN_CLHHSI
] = "clhhsi",
426 [LONG_INSN_CXFBRA
] = "cxfbra",
427 [LONG_INSN_CXGBRA
] = "cxgbra",
428 [LONG_INSN_CXGTRA
] = "cxgtra",
429 [LONG_INSN_CXLFBR
] = "cxlfbr",
430 [LONG_INSN_CXLFTR
] = "cxlftr",
431 [LONG_INSN_CXLGBR
] = "cxlgbr",
432 [LONG_INSN_CXLGTR
] = "cxlgtr",
433 [LONG_INSN_FIDBRA
] = "fidbra",
434 [LONG_INSN_FIEBRA
] = "fiebra",
435 [LONG_INSN_FIXBRA
] = "fixbra",
436 [LONG_INSN_LDXBRA
] = "ldxbra",
437 [LONG_INSN_LEDBRA
] = "ledbra",
438 [LONG_INSN_LEXBRA
] = "lexbra",
439 [LONG_INSN_LLGFAT
] = "llgfat",
440 [LONG_INSN_LLGFRL
] = "llgfrl",
441 [LONG_INSN_LLGHRL
] = "llghrl",
442 [LONG_INSN_LLGTAT
] = "llgtat",
443 [LONG_INSN_POPCNT
] = "popcnt",
444 [LONG_INSN_RIEMIT
] = "riemit",
445 [LONG_INSN_RINEXT
] = "rinext",
446 [LONG_INSN_RISBGN
] = "risbgn",
447 [LONG_INSN_RISBHG
] = "risbhg",
448 [LONG_INSN_RISBLG
] = "risblg",
449 [LONG_INSN_SLHHHR
] = "slhhhr",
450 [LONG_INSN_SLHHLR
] = "slhhlr",
451 [LONG_INSN_TABORT
] = "tabort",
452 [LONG_INSN_TBEGIN
] = "tbegin",
453 [LONG_INSN_TBEGINC
] = "tbeginc",
454 [LONG_INSN_PCISTG
] = "pcistg",
455 [LONG_INSN_MPCIFC
] = "mpcifc",
456 [LONG_INSN_STPCIFC
] = "stpcifc",
457 [LONG_INSN_PCISTB
] = "pcistb",
460 static struct s390_insn opcode
[] = {
462 { "bprp", 0xc5, INSTR_MII_UPI
},
463 { "bpp", 0xc7, INSTR_SMI_U0RDP
},
464 { "trtr", 0xd0, INSTR_SS_L0RDRD
},
465 { "lmd", 0xef, INSTR_SS_RRRDRD3
},
467 { "spm", 0x04, INSTR_RR_R0
},
468 { "balr", 0x05, INSTR_RR_RR
},
469 { "bctr", 0x06, INSTR_RR_RR
},
470 { "bcr", 0x07, INSTR_RR_UR
},
471 { "svc", 0x0a, INSTR_RR_U0
},
472 { "bsm", 0x0b, INSTR_RR_RR
},
473 { "bassm", 0x0c, INSTR_RR_RR
},
474 { "basr", 0x0d, INSTR_RR_RR
},
475 { "mvcl", 0x0e, INSTR_RR_RR
},
476 { "clcl", 0x0f, INSTR_RR_RR
},
477 { "lpr", 0x10, INSTR_RR_RR
},
478 { "lnr", 0x11, INSTR_RR_RR
},
479 { "ltr", 0x12, INSTR_RR_RR
},
480 { "lcr", 0x13, INSTR_RR_RR
},
481 { "nr", 0x14, INSTR_RR_RR
},
482 { "clr", 0x15, INSTR_RR_RR
},
483 { "or", 0x16, INSTR_RR_RR
},
484 { "xr", 0x17, INSTR_RR_RR
},
485 { "lr", 0x18, INSTR_RR_RR
},
486 { "cr", 0x19, INSTR_RR_RR
},
487 { "ar", 0x1a, INSTR_RR_RR
},
488 { "sr", 0x1b, INSTR_RR_RR
},
489 { "mr", 0x1c, INSTR_RR_RR
},
490 { "dr", 0x1d, INSTR_RR_RR
},
491 { "alr", 0x1e, INSTR_RR_RR
},
492 { "slr", 0x1f, INSTR_RR_RR
},
493 { "lpdr", 0x20, INSTR_RR_FF
},
494 { "lndr", 0x21, INSTR_RR_FF
},
495 { "ltdr", 0x22, INSTR_RR_FF
},
496 { "lcdr", 0x23, INSTR_RR_FF
},
497 { "hdr", 0x24, INSTR_RR_FF
},
498 { "ldxr", 0x25, INSTR_RR_FF
},
499 { "mxr", 0x26, INSTR_RR_FF
},
500 { "mxdr", 0x27, INSTR_RR_FF
},
501 { "ldr", 0x28, INSTR_RR_FF
},
502 { "cdr", 0x29, INSTR_RR_FF
},
503 { "adr", 0x2a, INSTR_RR_FF
},
504 { "sdr", 0x2b, INSTR_RR_FF
},
505 { "mdr", 0x2c, INSTR_RR_FF
},
506 { "ddr", 0x2d, INSTR_RR_FF
},
507 { "awr", 0x2e, INSTR_RR_FF
},
508 { "swr", 0x2f, INSTR_RR_FF
},
509 { "lper", 0x30, INSTR_RR_FF
},
510 { "lner", 0x31, INSTR_RR_FF
},
511 { "lter", 0x32, INSTR_RR_FF
},
512 { "lcer", 0x33, INSTR_RR_FF
},
513 { "her", 0x34, INSTR_RR_FF
},
514 { "ledr", 0x35, INSTR_RR_FF
},
515 { "axr", 0x36, INSTR_RR_FF
},
516 { "sxr", 0x37, INSTR_RR_FF
},
517 { "ler", 0x38, INSTR_RR_FF
},
518 { "cer", 0x39, INSTR_RR_FF
},
519 { "aer", 0x3a, INSTR_RR_FF
},
520 { "ser", 0x3b, INSTR_RR_FF
},
521 { "mder", 0x3c, INSTR_RR_FF
},
522 { "der", 0x3d, INSTR_RR_FF
},
523 { "aur", 0x3e, INSTR_RR_FF
},
524 { "sur", 0x3f, INSTR_RR_FF
},
525 { "sth", 0x40, INSTR_RX_RRRD
},
526 { "la", 0x41, INSTR_RX_RRRD
},
527 { "stc", 0x42, INSTR_RX_RRRD
},
528 { "ic", 0x43, INSTR_RX_RRRD
},
529 { "ex", 0x44, INSTR_RX_RRRD
},
530 { "bal", 0x45, INSTR_RX_RRRD
},
531 { "bct", 0x46, INSTR_RX_RRRD
},
532 { "bc", 0x47, INSTR_RX_URRD
},
533 { "lh", 0x48, INSTR_RX_RRRD
},
534 { "ch", 0x49, INSTR_RX_RRRD
},
535 { "ah", 0x4a, INSTR_RX_RRRD
},
536 { "sh", 0x4b, INSTR_RX_RRRD
},
537 { "mh", 0x4c, INSTR_RX_RRRD
},
538 { "bas", 0x4d, INSTR_RX_RRRD
},
539 { "cvd", 0x4e, INSTR_RX_RRRD
},
540 { "cvb", 0x4f, INSTR_RX_RRRD
},
541 { "st", 0x50, INSTR_RX_RRRD
},
542 { "lae", 0x51, INSTR_RX_RRRD
},
543 { "n", 0x54, INSTR_RX_RRRD
},
544 { "cl", 0x55, INSTR_RX_RRRD
},
545 { "o", 0x56, INSTR_RX_RRRD
},
546 { "x", 0x57, INSTR_RX_RRRD
},
547 { "l", 0x58, INSTR_RX_RRRD
},
548 { "c", 0x59, INSTR_RX_RRRD
},
549 { "a", 0x5a, INSTR_RX_RRRD
},
550 { "s", 0x5b, INSTR_RX_RRRD
},
551 { "m", 0x5c, INSTR_RX_RRRD
},
552 { "d", 0x5d, INSTR_RX_RRRD
},
553 { "al", 0x5e, INSTR_RX_RRRD
},
554 { "sl", 0x5f, INSTR_RX_RRRD
},
555 { "std", 0x60, INSTR_RX_FRRD
},
556 { "mxd", 0x67, INSTR_RX_FRRD
},
557 { "ld", 0x68, INSTR_RX_FRRD
},
558 { "cd", 0x69, INSTR_RX_FRRD
},
559 { "ad", 0x6a, INSTR_RX_FRRD
},
560 { "sd", 0x6b, INSTR_RX_FRRD
},
561 { "md", 0x6c, INSTR_RX_FRRD
},
562 { "dd", 0x6d, INSTR_RX_FRRD
},
563 { "aw", 0x6e, INSTR_RX_FRRD
},
564 { "sw", 0x6f, INSTR_RX_FRRD
},
565 { "ste", 0x70, INSTR_RX_FRRD
},
566 { "ms", 0x71, INSTR_RX_RRRD
},
567 { "le", 0x78, INSTR_RX_FRRD
},
568 { "ce", 0x79, INSTR_RX_FRRD
},
569 { "ae", 0x7a, INSTR_RX_FRRD
},
570 { "se", 0x7b, INSTR_RX_FRRD
},
571 { "mde", 0x7c, INSTR_RX_FRRD
},
572 { "de", 0x7d, INSTR_RX_FRRD
},
573 { "au", 0x7e, INSTR_RX_FRRD
},
574 { "su", 0x7f, INSTR_RX_FRRD
},
575 { "ssm", 0x80, INSTR_S_RD
},
576 { "lpsw", 0x82, INSTR_S_RD
},
577 { "diag", 0x83, INSTR_RS_RRRD
},
578 { "brxh", 0x84, INSTR_RSI_RRP
},
579 { "brxle", 0x85, INSTR_RSI_RRP
},
580 { "bxh", 0x86, INSTR_RS_RRRD
},
581 { "bxle", 0x87, INSTR_RS_RRRD
},
582 { "srl", 0x88, INSTR_RS_R0RD
},
583 { "sll", 0x89, INSTR_RS_R0RD
},
584 { "sra", 0x8a, INSTR_RS_R0RD
},
585 { "sla", 0x8b, INSTR_RS_R0RD
},
586 { "srdl", 0x8c, INSTR_RS_R0RD
},
587 { "sldl", 0x8d, INSTR_RS_R0RD
},
588 { "srda", 0x8e, INSTR_RS_R0RD
},
589 { "slda", 0x8f, INSTR_RS_R0RD
},
590 { "stm", 0x90, INSTR_RS_RRRD
},
591 { "tm", 0x91, INSTR_SI_URD
},
592 { "mvi", 0x92, INSTR_SI_URD
},
593 { "ts", 0x93, INSTR_S_RD
},
594 { "ni", 0x94, INSTR_SI_URD
},
595 { "cli", 0x95, INSTR_SI_URD
},
596 { "oi", 0x96, INSTR_SI_URD
},
597 { "xi", 0x97, INSTR_SI_URD
},
598 { "lm", 0x98, INSTR_RS_RRRD
},
599 { "trace", 0x99, INSTR_RS_RRRD
},
600 { "lam", 0x9a, INSTR_RS_AARD
},
601 { "stam", 0x9b, INSTR_RS_AARD
},
602 { "mvcle", 0xa8, INSTR_RS_RRRD
},
603 { "clcle", 0xa9, INSTR_RS_RRRD
},
604 { "stnsm", 0xac, INSTR_SI_URD
},
605 { "stosm", 0xad, INSTR_SI_URD
},
606 { "sigp", 0xae, INSTR_RS_RRRD
},
607 { "mc", 0xaf, INSTR_SI_URD
},
608 { "lra", 0xb1, INSTR_RX_RRRD
},
609 { "stctl", 0xb6, INSTR_RS_CCRD
},
610 { "lctl", 0xb7, INSTR_RS_CCRD
},
611 { "cs", 0xba, INSTR_RS_RRRD
},
612 { "cds", 0xbb, INSTR_RS_RRRD
},
613 { "clm", 0xbd, INSTR_RS_RURD
},
614 { "stcm", 0xbe, INSTR_RS_RURD
},
615 { "icm", 0xbf, INSTR_RS_RURD
},
616 { "mvn", 0xd1, INSTR_SS_L0RDRD
},
617 { "mvc", 0xd2, INSTR_SS_L0RDRD
},
618 { "mvz", 0xd3, INSTR_SS_L0RDRD
},
619 { "nc", 0xd4, INSTR_SS_L0RDRD
},
620 { "clc", 0xd5, INSTR_SS_L0RDRD
},
621 { "oc", 0xd6, INSTR_SS_L0RDRD
},
622 { "xc", 0xd7, INSTR_SS_L0RDRD
},
623 { "mvck", 0xd9, INSTR_SS_RRRDRD
},
624 { "mvcp", 0xda, INSTR_SS_RRRDRD
},
625 { "mvcs", 0xdb, INSTR_SS_RRRDRD
},
626 { "tr", 0xdc, INSTR_SS_L0RDRD
},
627 { "trt", 0xdd, INSTR_SS_L0RDRD
},
628 { "ed", 0xde, INSTR_SS_L0RDRD
},
629 { "edmk", 0xdf, INSTR_SS_L0RDRD
},
630 { "pku", 0xe1, INSTR_SS_L0RDRD
},
631 { "unpku", 0xe2, INSTR_SS_L0RDRD
},
632 { "mvcin", 0xe8, INSTR_SS_L0RDRD
},
633 { "pka", 0xe9, INSTR_SS_L0RDRD
},
634 { "unpka", 0xea, INSTR_SS_L0RDRD
},
635 { "plo", 0xee, INSTR_SS_RRRDRD2
},
636 { "srp", 0xf0, INSTR_SS_LIRDRD
},
637 { "mvo", 0xf1, INSTR_SS_LLRDRD
},
638 { "pack", 0xf2, INSTR_SS_LLRDRD
},
639 { "unpk", 0xf3, INSTR_SS_LLRDRD
},
640 { "zap", 0xf8, INSTR_SS_LLRDRD
},
641 { "cp", 0xf9, INSTR_SS_LLRDRD
},
642 { "ap", 0xfa, INSTR_SS_LLRDRD
},
643 { "sp", 0xfb, INSTR_SS_LLRDRD
},
644 { "mp", 0xfc, INSTR_SS_LLRDRD
},
645 { "dp", 0xfd, INSTR_SS_LLRDRD
},
646 { "", 0, INSTR_INVALID
}
649 static struct s390_insn opcode_01
[] = {
651 { "ptff", 0x04, INSTR_E
},
652 { "pfpo", 0x0a, INSTR_E
},
653 { "sam64", 0x0e, INSTR_E
},
655 { "pr", 0x01, INSTR_E
},
656 { "upt", 0x02, INSTR_E
},
657 { "sckpf", 0x07, INSTR_E
},
658 { "tam", 0x0b, INSTR_E
},
659 { "sam24", 0x0c, INSTR_E
},
660 { "sam31", 0x0d, INSTR_E
},
661 { "trap2", 0xff, INSTR_E
},
662 { "", 0, INSTR_INVALID
}
665 static struct s390_insn opcode_a5
[] = {
667 { "iihh", 0x00, INSTR_RI_RU
},
668 { "iihl", 0x01, INSTR_RI_RU
},
669 { "iilh", 0x02, INSTR_RI_RU
},
670 { "iill", 0x03, INSTR_RI_RU
},
671 { "nihh", 0x04, INSTR_RI_RU
},
672 { "nihl", 0x05, INSTR_RI_RU
},
673 { "nilh", 0x06, INSTR_RI_RU
},
674 { "nill", 0x07, INSTR_RI_RU
},
675 { "oihh", 0x08, INSTR_RI_RU
},
676 { "oihl", 0x09, INSTR_RI_RU
},
677 { "oilh", 0x0a, INSTR_RI_RU
},
678 { "oill", 0x0b, INSTR_RI_RU
},
679 { "llihh", 0x0c, INSTR_RI_RU
},
680 { "llihl", 0x0d, INSTR_RI_RU
},
681 { "llilh", 0x0e, INSTR_RI_RU
},
682 { "llill", 0x0f, INSTR_RI_RU
},
684 { "", 0, INSTR_INVALID
}
687 static struct s390_insn opcode_a7
[] = {
689 { "tmhh", 0x02, INSTR_RI_RU
},
690 { "tmhl", 0x03, INSTR_RI_RU
},
691 { "brctg", 0x07, INSTR_RI_RP
},
692 { "lghi", 0x09, INSTR_RI_RI
},
693 { "aghi", 0x0b, INSTR_RI_RI
},
694 { "mghi", 0x0d, INSTR_RI_RI
},
695 { "cghi", 0x0f, INSTR_RI_RI
},
697 { "tmlh", 0x00, INSTR_RI_RU
},
698 { "tmll", 0x01, INSTR_RI_RU
},
699 { "brc", 0x04, INSTR_RI_UP
},
700 { "bras", 0x05, INSTR_RI_RP
},
701 { "brct", 0x06, INSTR_RI_RP
},
702 { "lhi", 0x08, INSTR_RI_RI
},
703 { "ahi", 0x0a, INSTR_RI_RI
},
704 { "mhi", 0x0c, INSTR_RI_RI
},
705 { "chi", 0x0e, INSTR_RI_RI
},
706 { "", 0, INSTR_INVALID
}
709 static struct s390_insn opcode_aa
[] = {
711 { { 0, LONG_INSN_RINEXT
}, 0x00, INSTR_RI_RI
},
712 { "rion", 0x01, INSTR_RI_RI
},
713 { "tric", 0x02, INSTR_RI_RI
},
714 { "rioff", 0x03, INSTR_RI_RI
},
715 { { 0, LONG_INSN_RIEMIT
}, 0x04, INSTR_RI_RI
},
717 { "", 0, INSTR_INVALID
}
720 static struct s390_insn opcode_b2
[] = {
722 { "stckf", 0x7c, INSTR_S_RD
},
723 { "lpp", 0x80, INSTR_S_RD
},
724 { "lcctl", 0x84, INSTR_S_RD
},
725 { "lpctl", 0x85, INSTR_S_RD
},
726 { "qsi", 0x86, INSTR_S_RD
},
727 { "lsctl", 0x87, INSTR_S_RD
},
728 { "qctri", 0x8e, INSTR_S_RD
},
729 { "stfle", 0xb0, INSTR_S_RD
},
730 { "lpswe", 0xb2, INSTR_S_RD
},
731 { "srnmb", 0xb8, INSTR_S_RD
},
732 { "srnmt", 0xb9, INSTR_S_RD
},
733 { "lfas", 0xbd, INSTR_S_RD
},
734 { "scctr", 0xe0, INSTR_RRE_RR
},
735 { "spctr", 0xe1, INSTR_RRE_RR
},
736 { "ecctr", 0xe4, INSTR_RRE_RR
},
737 { "epctr", 0xe5, INSTR_RRE_RR
},
738 { "ppa", 0xe8, INSTR_RRF_U0RR
},
739 { "etnd", 0xec, INSTR_RRE_R0
},
740 { "ecpga", 0xed, INSTR_RRE_RR
},
741 { "tend", 0xf8, INSTR_S_00
},
742 { "niai", 0xfa, INSTR_IE_UU
},
743 { { 0, LONG_INSN_TABORT
}, 0xfc, INSTR_S_RD
},
745 { "stidp", 0x02, INSTR_S_RD
},
746 { "sck", 0x04, INSTR_S_RD
},
747 { "stck", 0x05, INSTR_S_RD
},
748 { "sckc", 0x06, INSTR_S_RD
},
749 { "stckc", 0x07, INSTR_S_RD
},
750 { "spt", 0x08, INSTR_S_RD
},
751 { "stpt", 0x09, INSTR_S_RD
},
752 { "spka", 0x0a, INSTR_S_RD
},
753 { "ipk", 0x0b, INSTR_S_00
},
754 { "ptlb", 0x0d, INSTR_S_00
},
755 { "spx", 0x10, INSTR_S_RD
},
756 { "stpx", 0x11, INSTR_S_RD
},
757 { "stap", 0x12, INSTR_S_RD
},
758 { "sie", 0x14, INSTR_S_RD
},
759 { "pc", 0x18, INSTR_S_RD
},
760 { "sac", 0x19, INSTR_S_RD
},
761 { "cfc", 0x1a, INSTR_S_RD
},
762 { "servc", 0x20, INSTR_RRE_RR
},
763 { "ipte", 0x21, INSTR_RRE_RR
},
764 { "ipm", 0x22, INSTR_RRE_R0
},
765 { "ivsk", 0x23, INSTR_RRE_RR
},
766 { "iac", 0x24, INSTR_RRE_R0
},
767 { "ssar", 0x25, INSTR_RRE_R0
},
768 { "epar", 0x26, INSTR_RRE_R0
},
769 { "esar", 0x27, INSTR_RRE_R0
},
770 { "pt", 0x28, INSTR_RRE_RR
},
771 { "iske", 0x29, INSTR_RRE_RR
},
772 { "rrbe", 0x2a, INSTR_RRE_RR
},
773 { "sske", 0x2b, INSTR_RRF_M0RR
},
774 { "tb", 0x2c, INSTR_RRE_0R
},
775 { "dxr", 0x2d, INSTR_RRE_FF
},
776 { "pgin", 0x2e, INSTR_RRE_RR
},
777 { "pgout", 0x2f, INSTR_RRE_RR
},
778 { "csch", 0x30, INSTR_S_00
},
779 { "hsch", 0x31, INSTR_S_00
},
780 { "msch", 0x32, INSTR_S_RD
},
781 { "ssch", 0x33, INSTR_S_RD
},
782 { "stsch", 0x34, INSTR_S_RD
},
783 { "tsch", 0x35, INSTR_S_RD
},
784 { "tpi", 0x36, INSTR_S_RD
},
785 { "sal", 0x37, INSTR_S_00
},
786 { "rsch", 0x38, INSTR_S_00
},
787 { "stcrw", 0x39, INSTR_S_RD
},
788 { "stcps", 0x3a, INSTR_S_RD
},
789 { "rchp", 0x3b, INSTR_S_00
},
790 { "schm", 0x3c, INSTR_S_00
},
791 { "bakr", 0x40, INSTR_RRE_RR
},
792 { "cksm", 0x41, INSTR_RRE_RR
},
793 { "sqdr", 0x44, INSTR_RRE_FF
},
794 { "sqer", 0x45, INSTR_RRE_FF
},
795 { "stura", 0x46, INSTR_RRE_RR
},
796 { "msta", 0x47, INSTR_RRE_R0
},
797 { "palb", 0x48, INSTR_RRE_00
},
798 { "ereg", 0x49, INSTR_RRE_RR
},
799 { "esta", 0x4a, INSTR_RRE_RR
},
800 { "lura", 0x4b, INSTR_RRE_RR
},
801 { "tar", 0x4c, INSTR_RRE_AR
},
802 { "cpya", 0x4d, INSTR_RRE_AA
},
803 { "sar", 0x4e, INSTR_RRE_AR
},
804 { "ear", 0x4f, INSTR_RRE_RA
},
805 { "csp", 0x50, INSTR_RRE_RR
},
806 { "msr", 0x52, INSTR_RRE_RR
},
807 { "mvpg", 0x54, INSTR_RRE_RR
},
808 { "mvst", 0x55, INSTR_RRE_RR
},
809 { "cuse", 0x57, INSTR_RRE_RR
},
810 { "bsg", 0x58, INSTR_RRE_RR
},
811 { "bsa", 0x5a, INSTR_RRE_RR
},
812 { "clst", 0x5d, INSTR_RRE_RR
},
813 { "srst", 0x5e, INSTR_RRE_RR
},
814 { "cmpsc", 0x63, INSTR_RRE_RR
},
815 { "siga", 0x74, INSTR_S_RD
},
816 { "xsch", 0x76, INSTR_S_00
},
817 { "rp", 0x77, INSTR_S_RD
},
818 { "stcke", 0x78, INSTR_S_RD
},
819 { "sacf", 0x79, INSTR_S_RD
},
820 { "stsi", 0x7d, INSTR_S_RD
},
821 { "srnm", 0x99, INSTR_S_RD
},
822 { "stfpc", 0x9c, INSTR_S_RD
},
823 { "lfpc", 0x9d, INSTR_S_RD
},
824 { "tre", 0xa5, INSTR_RRE_RR
},
825 { "cuutf", 0xa6, INSTR_RRF_M0RR
},
826 { "cutfu", 0xa7, INSTR_RRF_M0RR
},
827 { "stfl", 0xb1, INSTR_S_RD
},
828 { "trap4", 0xff, INSTR_S_RD
},
829 { "", 0, INSTR_INVALID
}
832 static struct s390_insn opcode_b3
[] = {
834 { "maylr", 0x38, INSTR_RRF_F0FF
},
835 { "mylr", 0x39, INSTR_RRF_F0FF
},
836 { "mayr", 0x3a, INSTR_RRF_F0FF
},
837 { "myr", 0x3b, INSTR_RRF_F0FF
},
838 { "mayhr", 0x3c, INSTR_RRF_F0FF
},
839 { "myhr", 0x3d, INSTR_RRF_F0FF
},
840 { "lpdfr", 0x70, INSTR_RRE_FF
},
841 { "lndfr", 0x71, INSTR_RRE_FF
},
842 { "cpsdr", 0x72, INSTR_RRF_F0FF2
},
843 { "lcdfr", 0x73, INSTR_RRE_FF
},
844 { "sfasr", 0x85, INSTR_RRE_R0
},
845 { { 0, LONG_INSN_CELFBR
}, 0x90, INSTR_RRF_UUFR
},
846 { { 0, LONG_INSN_CDLFBR
}, 0x91, INSTR_RRF_UUFR
},
847 { { 0, LONG_INSN_CXLFBR
}, 0x92, INSTR_RRF_UURF
},
848 { { 0, LONG_INSN_CEFBRA
}, 0x94, INSTR_RRF_UUFR
},
849 { { 0, LONG_INSN_CDFBRA
}, 0x95, INSTR_RRF_UUFR
},
850 { { 0, LONG_INSN_CXFBRA
}, 0x96, INSTR_RRF_UURF
},
851 { { 0, LONG_INSN_CFEBRA
}, 0x98, INSTR_RRF_UURF
},
852 { { 0, LONG_INSN_CFDBRA
}, 0x99, INSTR_RRF_UURF
},
853 { { 0, LONG_INSN_CFXBRA
}, 0x9a, INSTR_RRF_UUFR
},
854 { { 0, LONG_INSN_CLFEBR
}, 0x9c, INSTR_RRF_UURF
},
855 { { 0, LONG_INSN_CLFDBR
}, 0x9d, INSTR_RRF_UURF
},
856 { { 0, LONG_INSN_CLFXBR
}, 0x9e, INSTR_RRF_UUFR
},
857 { { 0, LONG_INSN_CELGBR
}, 0xa0, INSTR_RRF_UUFR
},
858 { { 0, LONG_INSN_CDLGBR
}, 0xa1, INSTR_RRF_UUFR
},
859 { { 0, LONG_INSN_CXLGBR
}, 0xa2, INSTR_RRF_UURF
},
860 { { 0, LONG_INSN_CEGBRA
}, 0xa4, INSTR_RRF_UUFR
},
861 { { 0, LONG_INSN_CDGBRA
}, 0xa5, INSTR_RRF_UUFR
},
862 { { 0, LONG_INSN_CXGBRA
}, 0xa6, INSTR_RRF_UURF
},
863 { { 0, LONG_INSN_CGEBRA
}, 0xa8, INSTR_RRF_UURF
},
864 { { 0, LONG_INSN_CGDBRA
}, 0xa9, INSTR_RRF_UURF
},
865 { { 0, LONG_INSN_CGXBRA
}, 0xaa, INSTR_RRF_UUFR
},
866 { { 0, LONG_INSN_CLGEBR
}, 0xac, INSTR_RRF_UURF
},
867 { { 0, LONG_INSN_CLGDBR
}, 0xad, INSTR_RRF_UURF
},
868 { { 0, LONG_INSN_CLGXBR
}, 0xae, INSTR_RRF_UUFR
},
869 { "ldgr", 0xc1, INSTR_RRE_FR
},
870 { "cegr", 0xc4, INSTR_RRE_FR
},
871 { "cdgr", 0xc5, INSTR_RRE_FR
},
872 { "cxgr", 0xc6, INSTR_RRE_FR
},
873 { "cger", 0xc8, INSTR_RRF_U0RF
},
874 { "cgdr", 0xc9, INSTR_RRF_U0RF
},
875 { "cgxr", 0xca, INSTR_RRF_U0RF
},
876 { "lgdr", 0xcd, INSTR_RRE_RF
},
877 { "mdtra", 0xd0, INSTR_RRF_FUFF2
},
878 { "ddtra", 0xd1, INSTR_RRF_FUFF2
},
879 { "adtra", 0xd2, INSTR_RRF_FUFF2
},
880 { "sdtra", 0xd3, INSTR_RRF_FUFF2
},
881 { "ldetr", 0xd4, INSTR_RRF_0UFF
},
882 { "ledtr", 0xd5, INSTR_RRF_UUFF
},
883 { "ltdtr", 0xd6, INSTR_RRE_FF
},
884 { "fidtr", 0xd7, INSTR_RRF_UUFF
},
885 { "mxtra", 0xd8, INSTR_RRF_FUFF2
},
886 { "dxtra", 0xd9, INSTR_RRF_FUFF2
},
887 { "axtra", 0xda, INSTR_RRF_FUFF2
},
888 { "sxtra", 0xdb, INSTR_RRF_FUFF2
},
889 { "lxdtr", 0xdc, INSTR_RRF_0UFF
},
890 { "ldxtr", 0xdd, INSTR_RRF_UUFF
},
891 { "ltxtr", 0xde, INSTR_RRE_FF
},
892 { "fixtr", 0xdf, INSTR_RRF_UUFF
},
893 { "kdtr", 0xe0, INSTR_RRE_FF
},
894 { { 0, LONG_INSN_CGDTRA
}, 0xe1, INSTR_RRF_UURF
},
895 { "cudtr", 0xe2, INSTR_RRE_RF
},
896 { "csdtr", 0xe3, INSTR_RRE_RF
},
897 { "cdtr", 0xe4, INSTR_RRE_FF
},
898 { "eedtr", 0xe5, INSTR_RRE_RF
},
899 { "esdtr", 0xe7, INSTR_RRE_RF
},
900 { "kxtr", 0xe8, INSTR_RRE_FF
},
901 { { 0, LONG_INSN_CGXTRA
}, 0xe9, INSTR_RRF_UUFR
},
902 { "cuxtr", 0xea, INSTR_RRE_RF
},
903 { "csxtr", 0xeb, INSTR_RRE_RF
},
904 { "cxtr", 0xec, INSTR_RRE_FF
},
905 { "eextr", 0xed, INSTR_RRE_RF
},
906 { "esxtr", 0xef, INSTR_RRE_RF
},
907 { { 0, LONG_INSN_CDGTRA
}, 0xf1, INSTR_RRF_UUFR
},
908 { "cdutr", 0xf2, INSTR_RRE_FR
},
909 { "cdstr", 0xf3, INSTR_RRE_FR
},
910 { "cedtr", 0xf4, INSTR_RRE_FF
},
911 { "qadtr", 0xf5, INSTR_RRF_FUFF
},
912 { "iedtr", 0xf6, INSTR_RRF_F0FR
},
913 { "rrdtr", 0xf7, INSTR_RRF_FFRU
},
914 { { 0, LONG_INSN_CXGTRA
}, 0xf9, INSTR_RRF_UURF
},
915 { "cxutr", 0xfa, INSTR_RRE_FR
},
916 { "cxstr", 0xfb, INSTR_RRE_FR
},
917 { "cextr", 0xfc, INSTR_RRE_FF
},
918 { "qaxtr", 0xfd, INSTR_RRF_FUFF
},
919 { "iextr", 0xfe, INSTR_RRF_F0FR
},
920 { "rrxtr", 0xff, INSTR_RRF_FFRU
},
922 { "lpebr", 0x00, INSTR_RRE_FF
},
923 { "lnebr", 0x01, INSTR_RRE_FF
},
924 { "ltebr", 0x02, INSTR_RRE_FF
},
925 { "lcebr", 0x03, INSTR_RRE_FF
},
926 { "ldebr", 0x04, INSTR_RRE_FF
},
927 { "lxdbr", 0x05, INSTR_RRE_FF
},
928 { "lxebr", 0x06, INSTR_RRE_FF
},
929 { "mxdbr", 0x07, INSTR_RRE_FF
},
930 { "kebr", 0x08, INSTR_RRE_FF
},
931 { "cebr", 0x09, INSTR_RRE_FF
},
932 { "aebr", 0x0a, INSTR_RRE_FF
},
933 { "sebr", 0x0b, INSTR_RRE_FF
},
934 { "mdebr", 0x0c, INSTR_RRE_FF
},
935 { "debr", 0x0d, INSTR_RRE_FF
},
936 { "maebr", 0x0e, INSTR_RRF_F0FF
},
937 { "msebr", 0x0f, INSTR_RRF_F0FF
},
938 { "lpdbr", 0x10, INSTR_RRE_FF
},
939 { "lndbr", 0x11, INSTR_RRE_FF
},
940 { "ltdbr", 0x12, INSTR_RRE_FF
},
941 { "lcdbr", 0x13, INSTR_RRE_FF
},
942 { "sqebr", 0x14, INSTR_RRE_FF
},
943 { "sqdbr", 0x15, INSTR_RRE_FF
},
944 { "sqxbr", 0x16, INSTR_RRE_FF
},
945 { "meebr", 0x17, INSTR_RRE_FF
},
946 { "kdbr", 0x18, INSTR_RRE_FF
},
947 { "cdbr", 0x19, INSTR_RRE_FF
},
948 { "adbr", 0x1a, INSTR_RRE_FF
},
949 { "sdbr", 0x1b, INSTR_RRE_FF
},
950 { "mdbr", 0x1c, INSTR_RRE_FF
},
951 { "ddbr", 0x1d, INSTR_RRE_FF
},
952 { "madbr", 0x1e, INSTR_RRF_F0FF
},
953 { "msdbr", 0x1f, INSTR_RRF_F0FF
},
954 { "lder", 0x24, INSTR_RRE_FF
},
955 { "lxdr", 0x25, INSTR_RRE_FF
},
956 { "lxer", 0x26, INSTR_RRE_FF
},
957 { "maer", 0x2e, INSTR_RRF_F0FF
},
958 { "mser", 0x2f, INSTR_RRF_F0FF
},
959 { "sqxr", 0x36, INSTR_RRE_FF
},
960 { "meer", 0x37, INSTR_RRE_FF
},
961 { "madr", 0x3e, INSTR_RRF_F0FF
},
962 { "msdr", 0x3f, INSTR_RRF_F0FF
},
963 { "lpxbr", 0x40, INSTR_RRE_FF
},
964 { "lnxbr", 0x41, INSTR_RRE_FF
},
965 { "ltxbr", 0x42, INSTR_RRE_FF
},
966 { "lcxbr", 0x43, INSTR_RRE_FF
},
967 { { 0, LONG_INSN_LEDBRA
}, 0x44, INSTR_RRF_UUFF
},
968 { { 0, LONG_INSN_LDXBRA
}, 0x45, INSTR_RRF_UUFF
},
969 { { 0, LONG_INSN_LEXBRA
}, 0x46, INSTR_RRF_UUFF
},
970 { { 0, LONG_INSN_FIXBRA
}, 0x47, INSTR_RRF_UUFF
},
971 { "kxbr", 0x48, INSTR_RRE_FF
},
972 { "cxbr", 0x49, INSTR_RRE_FF
},
973 { "axbr", 0x4a, INSTR_RRE_FF
},
974 { "sxbr", 0x4b, INSTR_RRE_FF
},
975 { "mxbr", 0x4c, INSTR_RRE_FF
},
976 { "dxbr", 0x4d, INSTR_RRE_FF
},
977 { "tbedr", 0x50, INSTR_RRF_U0FF
},
978 { "tbdr", 0x51, INSTR_RRF_U0FF
},
979 { "diebr", 0x53, INSTR_RRF_FUFF
},
980 { { 0, LONG_INSN_FIEBRA
}, 0x57, INSTR_RRF_UUFF
},
981 { "thder", 0x58, INSTR_RRE_FF
},
982 { "thdr", 0x59, INSTR_RRE_FF
},
983 { "didbr", 0x5b, INSTR_RRF_FUFF
},
984 { { 0, LONG_INSN_FIDBRA
}, 0x5f, INSTR_RRF_UUFF
},
985 { "lpxr", 0x60, INSTR_RRE_FF
},
986 { "lnxr", 0x61, INSTR_RRE_FF
},
987 { "ltxr", 0x62, INSTR_RRE_FF
},
988 { "lcxr", 0x63, INSTR_RRE_FF
},
989 { "lxr", 0x65, INSTR_RRE_FF
},
990 { "lexr", 0x66, INSTR_RRE_FF
},
991 { "fixr", 0x67, INSTR_RRE_FF
},
992 { "cxr", 0x69, INSTR_RRE_FF
},
993 { "lzer", 0x74, INSTR_RRE_F0
},
994 { "lzdr", 0x75, INSTR_RRE_F0
},
995 { "lzxr", 0x76, INSTR_RRE_F0
},
996 { "fier", 0x77, INSTR_RRE_FF
},
997 { "fidr", 0x7f, INSTR_RRE_FF
},
998 { "sfpc", 0x84, INSTR_RRE_RR_OPT
},
999 { "efpc", 0x8c, INSTR_RRE_RR_OPT
},
1000 { "cefbr", 0x94, INSTR_RRE_RF
},
1001 { "cdfbr", 0x95, INSTR_RRE_RF
},
1002 { "cxfbr", 0x96, INSTR_RRE_RF
},
1003 { "cfebr", 0x98, INSTR_RRF_U0RF
},
1004 { "cfdbr", 0x99, INSTR_RRF_U0RF
},
1005 { "cfxbr", 0x9a, INSTR_RRF_U0RF
},
1006 { "cefr", 0xb4, INSTR_RRE_FR
},
1007 { "cdfr", 0xb5, INSTR_RRE_FR
},
1008 { "cxfr", 0xb6, INSTR_RRE_FR
},
1009 { "cfer", 0xb8, INSTR_RRF_U0RF
},
1010 { "cfdr", 0xb9, INSTR_RRF_U0RF
},
1011 { "cfxr", 0xba, INSTR_RRF_U0RF
},
1012 { "", 0, INSTR_INVALID
}
1015 static struct s390_insn opcode_b9
[] = {
1017 { "lpgr", 0x00, INSTR_RRE_RR
},
1018 { "lngr", 0x01, INSTR_RRE_RR
},
1019 { "ltgr", 0x02, INSTR_RRE_RR
},
1020 { "lcgr", 0x03, INSTR_RRE_RR
},
1021 { "lgr", 0x04, INSTR_RRE_RR
},
1022 { "lurag", 0x05, INSTR_RRE_RR
},
1023 { "lgbr", 0x06, INSTR_RRE_RR
},
1024 { "lghr", 0x07, INSTR_RRE_RR
},
1025 { "agr", 0x08, INSTR_RRE_RR
},
1026 { "sgr", 0x09, INSTR_RRE_RR
},
1027 { "algr", 0x0a, INSTR_RRE_RR
},
1028 { "slgr", 0x0b, INSTR_RRE_RR
},
1029 { "msgr", 0x0c, INSTR_RRE_RR
},
1030 { "dsgr", 0x0d, INSTR_RRE_RR
},
1031 { "eregg", 0x0e, INSTR_RRE_RR
},
1032 { "lrvgr", 0x0f, INSTR_RRE_RR
},
1033 { "lpgfr", 0x10, INSTR_RRE_RR
},
1034 { "lngfr", 0x11, INSTR_RRE_RR
},
1035 { "ltgfr", 0x12, INSTR_RRE_RR
},
1036 { "lcgfr", 0x13, INSTR_RRE_RR
},
1037 { "lgfr", 0x14, INSTR_RRE_RR
},
1038 { "llgfr", 0x16, INSTR_RRE_RR
},
1039 { "llgtr", 0x17, INSTR_RRE_RR
},
1040 { "agfr", 0x18, INSTR_RRE_RR
},
1041 { "sgfr", 0x19, INSTR_RRE_RR
},
1042 { "algfr", 0x1a, INSTR_RRE_RR
},
1043 { "slgfr", 0x1b, INSTR_RRE_RR
},
1044 { "msgfr", 0x1c, INSTR_RRE_RR
},
1045 { "dsgfr", 0x1d, INSTR_RRE_RR
},
1046 { "cgr", 0x20, INSTR_RRE_RR
},
1047 { "clgr", 0x21, INSTR_RRE_RR
},
1048 { "sturg", 0x25, INSTR_RRE_RR
},
1049 { "lbr", 0x26, INSTR_RRE_RR
},
1050 { "lhr", 0x27, INSTR_RRE_RR
},
1051 { "cgfr", 0x30, INSTR_RRE_RR
},
1052 { "clgfr", 0x31, INSTR_RRE_RR
},
1053 { "cfdtr", 0x41, INSTR_RRF_UURF
},
1054 { { 0, LONG_INSN_CLGDTR
}, 0x42, INSTR_RRF_UURF
},
1055 { { 0, LONG_INSN_CLFDTR
}, 0x43, INSTR_RRF_UURF
},
1056 { "bctgr", 0x46, INSTR_RRE_RR
},
1057 { "cfxtr", 0x49, INSTR_RRF_UURF
},
1058 { { 0, LONG_INSN_CLGXTR
}, 0x4a, INSTR_RRF_UUFR
},
1059 { { 0, LONG_INSN_CLFXTR
}, 0x4b, INSTR_RRF_UUFR
},
1060 { "cdftr", 0x51, INSTR_RRF_UUFR
},
1061 { { 0, LONG_INSN_CDLGTR
}, 0x52, INSTR_RRF_UUFR
},
1062 { { 0, LONG_INSN_CDLFTR
}, 0x53, INSTR_RRF_UUFR
},
1063 { "cxftr", 0x59, INSTR_RRF_UURF
},
1064 { { 0, LONG_INSN_CXLGTR
}, 0x5a, INSTR_RRF_UURF
},
1065 { { 0, LONG_INSN_CXLFTR
}, 0x5b, INSTR_RRF_UUFR
},
1066 { "cgrt", 0x60, INSTR_RRF_U0RR
},
1067 { "clgrt", 0x61, INSTR_RRF_U0RR
},
1068 { "crt", 0x72, INSTR_RRF_U0RR
},
1069 { "clrt", 0x73, INSTR_RRF_U0RR
},
1070 { "ngr", 0x80, INSTR_RRE_RR
},
1071 { "ogr", 0x81, INSTR_RRE_RR
},
1072 { "xgr", 0x82, INSTR_RRE_RR
},
1073 { "flogr", 0x83, INSTR_RRE_RR
},
1074 { "llgcr", 0x84, INSTR_RRE_RR
},
1075 { "llghr", 0x85, INSTR_RRE_RR
},
1076 { "mlgr", 0x86, INSTR_RRE_RR
},
1077 { "dlgr", 0x87, INSTR_RRE_RR
},
1078 { "alcgr", 0x88, INSTR_RRE_RR
},
1079 { "slbgr", 0x89, INSTR_RRE_RR
},
1080 { "cspg", 0x8a, INSTR_RRE_RR
},
1081 { "idte", 0x8e, INSTR_RRF_R0RR
},
1082 { "crdte", 0x8f, INSTR_RRF_RMRR
},
1083 { "llcr", 0x94, INSTR_RRE_RR
},
1084 { "llhr", 0x95, INSTR_RRE_RR
},
1085 { "esea", 0x9d, INSTR_RRE_R0
},
1086 { "ptf", 0xa2, INSTR_RRE_R0
},
1087 { "lptea", 0xaa, INSTR_RRF_RURR
},
1088 { "rrbm", 0xae, INSTR_RRE_RR
},
1089 { "pfmf", 0xaf, INSTR_RRE_RR
},
1090 { "cu14", 0xb0, INSTR_RRF_M0RR
},
1091 { "cu24", 0xb1, INSTR_RRF_M0RR
},
1092 { "cu41", 0xb2, INSTR_RRE_RR
},
1093 { "cu42", 0xb3, INSTR_RRE_RR
},
1094 { "trtre", 0xbd, INSTR_RRF_M0RR
},
1095 { "srstu", 0xbe, INSTR_RRE_RR
},
1096 { "trte", 0xbf, INSTR_RRF_M0RR
},
1097 { "ahhhr", 0xc8, INSTR_RRF_R0RR2
},
1098 { "shhhr", 0xc9, INSTR_RRF_R0RR2
},
1099 { { 0, LONG_INSN_ALHHHR
}, 0xca, INSTR_RRF_R0RR2
},
1100 { { 0, LONG_INSN_SLHHHR
}, 0xcb, INSTR_RRF_R0RR2
},
1101 { "chhr", 0xcd, INSTR_RRE_RR
},
1102 { "clhhr", 0xcf, INSTR_RRE_RR
},
1103 { { 0, LONG_INSN_PCISTG
}, 0xd0, INSTR_RRE_RR
},
1104 { "pcilg", 0xd2, INSTR_RRE_RR
},
1105 { "rpcit", 0xd3, INSTR_RRE_RR
},
1106 { "ahhlr", 0xd8, INSTR_RRF_R0RR2
},
1107 { "shhlr", 0xd9, INSTR_RRF_R0RR2
},
1108 { { 0, LONG_INSN_ALHHLR
}, 0xda, INSTR_RRF_R0RR2
},
1109 { { 0, LONG_INSN_SLHHLR
}, 0xdb, INSTR_RRF_R0RR2
},
1110 { "chlr", 0xdd, INSTR_RRE_RR
},
1111 { "clhlr", 0xdf, INSTR_RRE_RR
},
1112 { { 0, LONG_INSN_POPCNT
}, 0xe1, INSTR_RRE_RR
},
1113 { "locgr", 0xe2, INSTR_RRF_M0RR
},
1114 { "ngrk", 0xe4, INSTR_RRF_R0RR2
},
1115 { "ogrk", 0xe6, INSTR_RRF_R0RR2
},
1116 { "xgrk", 0xe7, INSTR_RRF_R0RR2
},
1117 { "agrk", 0xe8, INSTR_RRF_R0RR2
},
1118 { "sgrk", 0xe9, INSTR_RRF_R0RR2
},
1119 { "algrk", 0xea, INSTR_RRF_R0RR2
},
1120 { "slgrk", 0xeb, INSTR_RRF_R0RR2
},
1121 { "locr", 0xf2, INSTR_RRF_M0RR
},
1122 { "nrk", 0xf4, INSTR_RRF_R0RR2
},
1123 { "ork", 0xf6, INSTR_RRF_R0RR2
},
1124 { "xrk", 0xf7, INSTR_RRF_R0RR2
},
1125 { "ark", 0xf8, INSTR_RRF_R0RR2
},
1126 { "srk", 0xf9, INSTR_RRF_R0RR2
},
1127 { "alrk", 0xfa, INSTR_RRF_R0RR2
},
1128 { "slrk", 0xfb, INSTR_RRF_R0RR2
},
1130 { "kmac", 0x1e, INSTR_RRE_RR
},
1131 { "lrvr", 0x1f, INSTR_RRE_RR
},
1132 { "km", 0x2e, INSTR_RRE_RR
},
1133 { "kmc", 0x2f, INSTR_RRE_RR
},
1134 { "kimd", 0x3e, INSTR_RRE_RR
},
1135 { "klmd", 0x3f, INSTR_RRE_RR
},
1136 { "epsw", 0x8d, INSTR_RRE_RR
},
1137 { "trtt", 0x90, INSTR_RRF_M0RR
},
1138 { "trto", 0x91, INSTR_RRF_M0RR
},
1139 { "trot", 0x92, INSTR_RRF_M0RR
},
1140 { "troo", 0x93, INSTR_RRF_M0RR
},
1141 { "mlr", 0x96, INSTR_RRE_RR
},
1142 { "dlr", 0x97, INSTR_RRE_RR
},
1143 { "alcr", 0x98, INSTR_RRE_RR
},
1144 { "slbr", 0x99, INSTR_RRE_RR
},
1145 { "", 0, INSTR_INVALID
}
1148 static struct s390_insn opcode_c0
[] = {
1150 { "lgfi", 0x01, INSTR_RIL_RI
},
1151 { "xihf", 0x06, INSTR_RIL_RU
},
1152 { "xilf", 0x07, INSTR_RIL_RU
},
1153 { "iihf", 0x08, INSTR_RIL_RU
},
1154 { "iilf", 0x09, INSTR_RIL_RU
},
1155 { "nihf", 0x0a, INSTR_RIL_RU
},
1156 { "nilf", 0x0b, INSTR_RIL_RU
},
1157 { "oihf", 0x0c, INSTR_RIL_RU
},
1158 { "oilf", 0x0d, INSTR_RIL_RU
},
1159 { "llihf", 0x0e, INSTR_RIL_RU
},
1160 { "llilf", 0x0f, INSTR_RIL_RU
},
1162 { "larl", 0x00, INSTR_RIL_RP
},
1163 { "brcl", 0x04, INSTR_RIL_UP
},
1164 { "brasl", 0x05, INSTR_RIL_RP
},
1165 { "", 0, INSTR_INVALID
}
1168 static struct s390_insn opcode_c2
[] = {
1170 { "msgfi", 0x00, INSTR_RIL_RI
},
1171 { "msfi", 0x01, INSTR_RIL_RI
},
1172 { "slgfi", 0x04, INSTR_RIL_RU
},
1173 { "slfi", 0x05, INSTR_RIL_RU
},
1174 { "agfi", 0x08, INSTR_RIL_RI
},
1175 { "afi", 0x09, INSTR_RIL_RI
},
1176 { "algfi", 0x0a, INSTR_RIL_RU
},
1177 { "alfi", 0x0b, INSTR_RIL_RU
},
1178 { "cgfi", 0x0c, INSTR_RIL_RI
},
1179 { "cfi", 0x0d, INSTR_RIL_RI
},
1180 { "clgfi", 0x0e, INSTR_RIL_RU
},
1181 { "clfi", 0x0f, INSTR_RIL_RU
},
1183 { "", 0, INSTR_INVALID
}
1186 static struct s390_insn opcode_c4
[] = {
1188 { "llhrl", 0x02, INSTR_RIL_RP
},
1189 { "lghrl", 0x04, INSTR_RIL_RP
},
1190 { "lhrl", 0x05, INSTR_RIL_RP
},
1191 { { 0, LONG_INSN_LLGHRL
}, 0x06, INSTR_RIL_RP
},
1192 { "sthrl", 0x07, INSTR_RIL_RP
},
1193 { "lgrl", 0x08, INSTR_RIL_RP
},
1194 { "stgrl", 0x0b, INSTR_RIL_RP
},
1195 { "lgfrl", 0x0c, INSTR_RIL_RP
},
1196 { "lrl", 0x0d, INSTR_RIL_RP
},
1197 { { 0, LONG_INSN_LLGFRL
}, 0x0e, INSTR_RIL_RP
},
1198 { "strl", 0x0f, INSTR_RIL_RP
},
1200 { "", 0, INSTR_INVALID
}
1203 static struct s390_insn opcode_c6
[] = {
1205 { "exrl", 0x00, INSTR_RIL_RP
},
1206 { "pfdrl", 0x02, INSTR_RIL_UP
},
1207 { "cghrl", 0x04, INSTR_RIL_RP
},
1208 { "chrl", 0x05, INSTR_RIL_RP
},
1209 { { 0, LONG_INSN_CLGHRL
}, 0x06, INSTR_RIL_RP
},
1210 { "clhrl", 0x07, INSTR_RIL_RP
},
1211 { "cgrl", 0x08, INSTR_RIL_RP
},
1212 { "clgrl", 0x0a, INSTR_RIL_RP
},
1213 { "cgfrl", 0x0c, INSTR_RIL_RP
},
1214 { "crl", 0x0d, INSTR_RIL_RP
},
1215 { { 0, LONG_INSN_CLGFRL
}, 0x0e, INSTR_RIL_RP
},
1216 { "clrl", 0x0f, INSTR_RIL_RP
},
1218 { "", 0, INSTR_INVALID
}
1221 static struct s390_insn opcode_c8
[] = {
1223 { "mvcos", 0x00, INSTR_SSF_RRDRD
},
1224 { "ectg", 0x01, INSTR_SSF_RRDRD
},
1225 { "csst", 0x02, INSTR_SSF_RRDRD
},
1226 { "lpd", 0x04, INSTR_SSF_RRDRD2
},
1227 { "lpdg", 0x05, INSTR_SSF_RRDRD2
},
1229 { "", 0, INSTR_INVALID
}
1232 static struct s390_insn opcode_cc
[] = {
1234 { "brcth", 0x06, INSTR_RIL_RP
},
1235 { "aih", 0x08, INSTR_RIL_RI
},
1236 { "alsih", 0x0a, INSTR_RIL_RI
},
1237 { { 0, LONG_INSN_ALSIHN
}, 0x0b, INSTR_RIL_RI
},
1238 { "cih", 0x0d, INSTR_RIL_RI
},
1239 { "clih", 0x0f, INSTR_RIL_RI
},
1241 { "", 0, INSTR_INVALID
}
1244 static struct s390_insn opcode_e3
[] = {
1246 { "ltg", 0x02, INSTR_RXY_RRRD
},
1247 { "lrag", 0x03, INSTR_RXY_RRRD
},
1248 { "lg", 0x04, INSTR_RXY_RRRD
},
1249 { "cvby", 0x06, INSTR_RXY_RRRD
},
1250 { "ag", 0x08, INSTR_RXY_RRRD
},
1251 { "sg", 0x09, INSTR_RXY_RRRD
},
1252 { "alg", 0x0a, INSTR_RXY_RRRD
},
1253 { "slg", 0x0b, INSTR_RXY_RRRD
},
1254 { "msg", 0x0c, INSTR_RXY_RRRD
},
1255 { "dsg", 0x0d, INSTR_RXY_RRRD
},
1256 { "cvbg", 0x0e, INSTR_RXY_RRRD
},
1257 { "lrvg", 0x0f, INSTR_RXY_RRRD
},
1258 { "lt", 0x12, INSTR_RXY_RRRD
},
1259 { "lray", 0x13, INSTR_RXY_RRRD
},
1260 { "lgf", 0x14, INSTR_RXY_RRRD
},
1261 { "lgh", 0x15, INSTR_RXY_RRRD
},
1262 { "llgf", 0x16, INSTR_RXY_RRRD
},
1263 { "llgt", 0x17, INSTR_RXY_RRRD
},
1264 { "agf", 0x18, INSTR_RXY_RRRD
},
1265 { "sgf", 0x19, INSTR_RXY_RRRD
},
1266 { "algf", 0x1a, INSTR_RXY_RRRD
},
1267 { "slgf", 0x1b, INSTR_RXY_RRRD
},
1268 { "msgf", 0x1c, INSTR_RXY_RRRD
},
1269 { "dsgf", 0x1d, INSTR_RXY_RRRD
},
1270 { "cg", 0x20, INSTR_RXY_RRRD
},
1271 { "clg", 0x21, INSTR_RXY_RRRD
},
1272 { "stg", 0x24, INSTR_RXY_RRRD
},
1273 { "ntstg", 0x25, INSTR_RXY_RRRD
},
1274 { "cvdy", 0x26, INSTR_RXY_RRRD
},
1275 { "cvdg", 0x2e, INSTR_RXY_RRRD
},
1276 { "strvg", 0x2f, INSTR_RXY_RRRD
},
1277 { "cgf", 0x30, INSTR_RXY_RRRD
},
1278 { "clgf", 0x31, INSTR_RXY_RRRD
},
1279 { "ltgf", 0x32, INSTR_RXY_RRRD
},
1280 { "cgh", 0x34, INSTR_RXY_RRRD
},
1281 { "pfd", 0x36, INSTR_RXY_URRD
},
1282 { "strvh", 0x3f, INSTR_RXY_RRRD
},
1283 { "bctg", 0x46, INSTR_RXY_RRRD
},
1284 { "sty", 0x50, INSTR_RXY_RRRD
},
1285 { "msy", 0x51, INSTR_RXY_RRRD
},
1286 { "ny", 0x54, INSTR_RXY_RRRD
},
1287 { "cly", 0x55, INSTR_RXY_RRRD
},
1288 { "oy", 0x56, INSTR_RXY_RRRD
},
1289 { "xy", 0x57, INSTR_RXY_RRRD
},
1290 { "ly", 0x58, INSTR_RXY_RRRD
},
1291 { "cy", 0x59, INSTR_RXY_RRRD
},
1292 { "ay", 0x5a, INSTR_RXY_RRRD
},
1293 { "sy", 0x5b, INSTR_RXY_RRRD
},
1294 { "mfy", 0x5c, INSTR_RXY_RRRD
},
1295 { "aly", 0x5e, INSTR_RXY_RRRD
},
1296 { "sly", 0x5f, INSTR_RXY_RRRD
},
1297 { "sthy", 0x70, INSTR_RXY_RRRD
},
1298 { "lay", 0x71, INSTR_RXY_RRRD
},
1299 { "stcy", 0x72, INSTR_RXY_RRRD
},
1300 { "icy", 0x73, INSTR_RXY_RRRD
},
1301 { "laey", 0x75, INSTR_RXY_RRRD
},
1302 { "lb", 0x76, INSTR_RXY_RRRD
},
1303 { "lgb", 0x77, INSTR_RXY_RRRD
},
1304 { "lhy", 0x78, INSTR_RXY_RRRD
},
1305 { "chy", 0x79, INSTR_RXY_RRRD
},
1306 { "ahy", 0x7a, INSTR_RXY_RRRD
},
1307 { "shy", 0x7b, INSTR_RXY_RRRD
},
1308 { "mhy", 0x7c, INSTR_RXY_RRRD
},
1309 { "ng", 0x80, INSTR_RXY_RRRD
},
1310 { "og", 0x81, INSTR_RXY_RRRD
},
1311 { "xg", 0x82, INSTR_RXY_RRRD
},
1312 { "lgat", 0x85, INSTR_RXY_RRRD
},
1313 { "mlg", 0x86, INSTR_RXY_RRRD
},
1314 { "dlg", 0x87, INSTR_RXY_RRRD
},
1315 { "alcg", 0x88, INSTR_RXY_RRRD
},
1316 { "slbg", 0x89, INSTR_RXY_RRRD
},
1317 { "stpq", 0x8e, INSTR_RXY_RRRD
},
1318 { "lpq", 0x8f, INSTR_RXY_RRRD
},
1319 { "llgc", 0x90, INSTR_RXY_RRRD
},
1320 { "llgh", 0x91, INSTR_RXY_RRRD
},
1321 { "llc", 0x94, INSTR_RXY_RRRD
},
1322 { "llh", 0x95, INSTR_RXY_RRRD
},
1323 { { 0, LONG_INSN_LLGTAT
}, 0x9c, INSTR_RXY_RRRD
},
1324 { { 0, LONG_INSN_LLGFAT
}, 0x9d, INSTR_RXY_RRRD
},
1325 { "lat", 0x9f, INSTR_RXY_RRRD
},
1326 { "lbh", 0xc0, INSTR_RXY_RRRD
},
1327 { "llch", 0xc2, INSTR_RXY_RRRD
},
1328 { "stch", 0xc3, INSTR_RXY_RRRD
},
1329 { "lhh", 0xc4, INSTR_RXY_RRRD
},
1330 { "llhh", 0xc6, INSTR_RXY_RRRD
},
1331 { "sthh", 0xc7, INSTR_RXY_RRRD
},
1332 { "lfhat", 0xc8, INSTR_RXY_RRRD
},
1333 { "lfh", 0xca, INSTR_RXY_RRRD
},
1334 { "stfh", 0xcb, INSTR_RXY_RRRD
},
1335 { "chf", 0xcd, INSTR_RXY_RRRD
},
1336 { "clhf", 0xcf, INSTR_RXY_RRRD
},
1337 { { 0, LONG_INSN_MPCIFC
}, 0xd0, INSTR_RXY_RRRD
},
1338 { { 0, LONG_INSN_STPCIFC
}, 0xd4, INSTR_RXY_RRRD
},
1340 { "lrv", 0x1e, INSTR_RXY_RRRD
},
1341 { "lrvh", 0x1f, INSTR_RXY_RRRD
},
1342 { "strv", 0x3e, INSTR_RXY_RRRD
},
1343 { "ml", 0x96, INSTR_RXY_RRRD
},
1344 { "dl", 0x97, INSTR_RXY_RRRD
},
1345 { "alc", 0x98, INSTR_RXY_RRRD
},
1346 { "slb", 0x99, INSTR_RXY_RRRD
},
1347 { "", 0, INSTR_INVALID
}
1350 static struct s390_insn opcode_e5
[] = {
1352 { "strag", 0x02, INSTR_SSE_RDRD
},
1353 { "mvhhi", 0x44, INSTR_SIL_RDI
},
1354 { "mvghi", 0x48, INSTR_SIL_RDI
},
1355 { "mvhi", 0x4c, INSTR_SIL_RDI
},
1356 { "chhsi", 0x54, INSTR_SIL_RDI
},
1357 { { 0, LONG_INSN_CLHHSI
}, 0x55, INSTR_SIL_RDU
},
1358 { "cghsi", 0x58, INSTR_SIL_RDI
},
1359 { { 0, LONG_INSN_CLGHSI
}, 0x59, INSTR_SIL_RDU
},
1360 { "chsi", 0x5c, INSTR_SIL_RDI
},
1361 { { 0, LONG_INSN_CLFHSI
}, 0x5d, INSTR_SIL_RDU
},
1362 { { 0, LONG_INSN_TBEGIN
}, 0x60, INSTR_SIL_RDU
},
1363 { { 0, LONG_INSN_TBEGINC
}, 0x61, INSTR_SIL_RDU
},
1365 { "lasp", 0x00, INSTR_SSE_RDRD
},
1366 { "tprot", 0x01, INSTR_SSE_RDRD
},
1367 { "mvcsk", 0x0e, INSTR_SSE_RDRD
},
1368 { "mvcdk", 0x0f, INSTR_SSE_RDRD
},
1369 { "", 0, INSTR_INVALID
}
1372 static struct s390_insn opcode_eb
[] = {
1374 { "lmg", 0x04, INSTR_RSY_RRRD
},
1375 { "srag", 0x0a, INSTR_RSY_RRRD
},
1376 { "slag", 0x0b, INSTR_RSY_RRRD
},
1377 { "srlg", 0x0c, INSTR_RSY_RRRD
},
1378 { "sllg", 0x0d, INSTR_RSY_RRRD
},
1379 { "tracg", 0x0f, INSTR_RSY_RRRD
},
1380 { "csy", 0x14, INSTR_RSY_RRRD
},
1381 { "rllg", 0x1c, INSTR_RSY_RRRD
},
1382 { "clmh", 0x20, INSTR_RSY_RURD
},
1383 { "clmy", 0x21, INSTR_RSY_RURD
},
1384 { "clt", 0x23, INSTR_RSY_RURD
},
1385 { "stmg", 0x24, INSTR_RSY_RRRD
},
1386 { "stctg", 0x25, INSTR_RSY_CCRD
},
1387 { "stmh", 0x26, INSTR_RSY_RRRD
},
1388 { "clgt", 0x2b, INSTR_RSY_RURD
},
1389 { "stcmh", 0x2c, INSTR_RSY_RURD
},
1390 { "stcmy", 0x2d, INSTR_RSY_RURD
},
1391 { "lctlg", 0x2f, INSTR_RSY_CCRD
},
1392 { "csg", 0x30, INSTR_RSY_RRRD
},
1393 { "cdsy", 0x31, INSTR_RSY_RRRD
},
1394 { "cdsg", 0x3e, INSTR_RSY_RRRD
},
1395 { "bxhg", 0x44, INSTR_RSY_RRRD
},
1396 { "bxleg", 0x45, INSTR_RSY_RRRD
},
1397 { "ecag", 0x4c, INSTR_RSY_RRRD
},
1398 { "tmy", 0x51, INSTR_SIY_URD
},
1399 { "mviy", 0x52, INSTR_SIY_URD
},
1400 { "niy", 0x54, INSTR_SIY_URD
},
1401 { "cliy", 0x55, INSTR_SIY_URD
},
1402 { "oiy", 0x56, INSTR_SIY_URD
},
1403 { "xiy", 0x57, INSTR_SIY_URD
},
1404 { "asi", 0x6a, INSTR_SIY_IRD
},
1405 { "alsi", 0x6e, INSTR_SIY_IRD
},
1406 { "agsi", 0x7a, INSTR_SIY_IRD
},
1407 { "algsi", 0x7e, INSTR_SIY_IRD
},
1408 { "icmh", 0x80, INSTR_RSY_RURD
},
1409 { "icmy", 0x81, INSTR_RSY_RURD
},
1410 { "clclu", 0x8f, INSTR_RSY_RRRD
},
1411 { "stmy", 0x90, INSTR_RSY_RRRD
},
1412 { "lmh", 0x96, INSTR_RSY_RRRD
},
1413 { "lmy", 0x98, INSTR_RSY_RRRD
},
1414 { "lamy", 0x9a, INSTR_RSY_AARD
},
1415 { "stamy", 0x9b, INSTR_RSY_AARD
},
1416 { { 0, LONG_INSN_PCISTB
}, 0xd0, INSTR_RSY_RRRD
},
1417 { "sic", 0xd1, INSTR_RSY_RRRD
},
1418 { "srak", 0xdc, INSTR_RSY_RRRD
},
1419 { "slak", 0xdd, INSTR_RSY_RRRD
},
1420 { "srlk", 0xde, INSTR_RSY_RRRD
},
1421 { "sllk", 0xdf, INSTR_RSY_RRRD
},
1422 { "locg", 0xe2, INSTR_RSY_RDRM
},
1423 { "stocg", 0xe3, INSTR_RSY_RDRM
},
1424 { "lang", 0xe4, INSTR_RSY_RRRD
},
1425 { "laog", 0xe6, INSTR_RSY_RRRD
},
1426 { "laxg", 0xe7, INSTR_RSY_RRRD
},
1427 { "laag", 0xe8, INSTR_RSY_RRRD
},
1428 { "laalg", 0xea, INSTR_RSY_RRRD
},
1429 { "loc", 0xf2, INSTR_RSY_RDRM
},
1430 { "stoc", 0xf3, INSTR_RSY_RDRM
},
1431 { "lan", 0xf4, INSTR_RSY_RRRD
},
1432 { "lao", 0xf6, INSTR_RSY_RRRD
},
1433 { "lax", 0xf7, INSTR_RSY_RRRD
},
1434 { "laa", 0xf8, INSTR_RSY_RRRD
},
1435 { "laal", 0xfa, INSTR_RSY_RRRD
},
1436 { "lric", 0x60, INSTR_RSY_RDRM
},
1437 { "stric", 0x61, INSTR_RSY_RDRM
},
1438 { "mric", 0x62, INSTR_RSY_RDRM
},
1440 { "rll", 0x1d, INSTR_RSY_RRRD
},
1441 { "mvclu", 0x8e, INSTR_RSY_RRRD
},
1442 { "tp", 0xc0, INSTR_RSL_R0RD
},
1443 { "", 0, INSTR_INVALID
}
1446 static struct s390_insn opcode_ec
[] = {
1448 { "brxhg", 0x44, INSTR_RIE_RRP
},
1449 { "brxlg", 0x45, INSTR_RIE_RRP
},
1450 { { 0, LONG_INSN_RISBLG
}, 0x51, INSTR_RIE_RRUUU
},
1451 { "rnsbg", 0x54, INSTR_RIE_RRUUU
},
1452 { "risbg", 0x55, INSTR_RIE_RRUUU
},
1453 { "rosbg", 0x56, INSTR_RIE_RRUUU
},
1454 { "rxsbg", 0x57, INSTR_RIE_RRUUU
},
1455 { { 0, LONG_INSN_RISBGN
}, 0x59, INSTR_RIE_RRUUU
},
1456 { { 0, LONG_INSN_RISBHG
}, 0x5D, INSTR_RIE_RRUUU
},
1457 { "cgrj", 0x64, INSTR_RIE_RRPU
},
1458 { "clgrj", 0x65, INSTR_RIE_RRPU
},
1459 { "cgit", 0x70, INSTR_RIE_R0IU
},
1460 { "clgit", 0x71, INSTR_RIE_R0UU
},
1461 { "cit", 0x72, INSTR_RIE_R0IU
},
1462 { "clfit", 0x73, INSTR_RIE_R0UU
},
1463 { "crj", 0x76, INSTR_RIE_RRPU
},
1464 { "clrj", 0x77, INSTR_RIE_RRPU
},
1465 { "cgij", 0x7c, INSTR_RIE_RUPI
},
1466 { "clgij", 0x7d, INSTR_RIE_RUPU
},
1467 { "cij", 0x7e, INSTR_RIE_RUPI
},
1468 { "clij", 0x7f, INSTR_RIE_RUPU
},
1469 { "ahik", 0xd8, INSTR_RIE_RRI0
},
1470 { "aghik", 0xd9, INSTR_RIE_RRI0
},
1471 { { 0, LONG_INSN_ALHSIK
}, 0xda, INSTR_RIE_RRI0
},
1472 { { 0, LONG_INSN_ALGHSIK
}, 0xdb, INSTR_RIE_RRI0
},
1473 { "cgrb", 0xe4, INSTR_RRS_RRRDU
},
1474 { "clgrb", 0xe5, INSTR_RRS_RRRDU
},
1475 { "crb", 0xf6, INSTR_RRS_RRRDU
},
1476 { "clrb", 0xf7, INSTR_RRS_RRRDU
},
1477 { "cgib", 0xfc, INSTR_RIS_RURDI
},
1478 { "clgib", 0xfd, INSTR_RIS_RURDU
},
1479 { "cib", 0xfe, INSTR_RIS_RURDI
},
1480 { "clib", 0xff, INSTR_RIS_RURDU
},
1482 { "", 0, INSTR_INVALID
}
1485 static struct s390_insn opcode_ed
[] = {
1487 { "mayl", 0x38, INSTR_RXF_FRRDF
},
1488 { "myl", 0x39, INSTR_RXF_FRRDF
},
1489 { "may", 0x3a, INSTR_RXF_FRRDF
},
1490 { "my", 0x3b, INSTR_RXF_FRRDF
},
1491 { "mayh", 0x3c, INSTR_RXF_FRRDF
},
1492 { "myh", 0x3d, INSTR_RXF_FRRDF
},
1493 { "sldt", 0x40, INSTR_RXF_FRRDF
},
1494 { "srdt", 0x41, INSTR_RXF_FRRDF
},
1495 { "slxt", 0x48, INSTR_RXF_FRRDF
},
1496 { "srxt", 0x49, INSTR_RXF_FRRDF
},
1497 { "tdcet", 0x50, INSTR_RXE_FRRD
},
1498 { "tdget", 0x51, INSTR_RXE_FRRD
},
1499 { "tdcdt", 0x54, INSTR_RXE_FRRD
},
1500 { "tdgdt", 0x55, INSTR_RXE_FRRD
},
1501 { "tdcxt", 0x58, INSTR_RXE_FRRD
},
1502 { "tdgxt", 0x59, INSTR_RXE_FRRD
},
1503 { "ley", 0x64, INSTR_RXY_FRRD
},
1504 { "ldy", 0x65, INSTR_RXY_FRRD
},
1505 { "stey", 0x66, INSTR_RXY_FRRD
},
1506 { "stdy", 0x67, INSTR_RXY_FRRD
},
1507 { "czdt", 0xa8, INSTR_RSL_LRDFU
},
1508 { "czxt", 0xa9, INSTR_RSL_LRDFU
},
1509 { "cdzt", 0xaa, INSTR_RSL_LRDFU
},
1510 { "cxzt", 0xab, INSTR_RSL_LRDFU
},
1512 { "ldeb", 0x04, INSTR_RXE_FRRD
},
1513 { "lxdb", 0x05, INSTR_RXE_FRRD
},
1514 { "lxeb", 0x06, INSTR_RXE_FRRD
},
1515 { "mxdb", 0x07, INSTR_RXE_FRRD
},
1516 { "keb", 0x08, INSTR_RXE_FRRD
},
1517 { "ceb", 0x09, INSTR_RXE_FRRD
},
1518 { "aeb", 0x0a, INSTR_RXE_FRRD
},
1519 { "seb", 0x0b, INSTR_RXE_FRRD
},
1520 { "mdeb", 0x0c, INSTR_RXE_FRRD
},
1521 { "deb", 0x0d, INSTR_RXE_FRRD
},
1522 { "maeb", 0x0e, INSTR_RXF_FRRDF
},
1523 { "mseb", 0x0f, INSTR_RXF_FRRDF
},
1524 { "tceb", 0x10, INSTR_RXE_FRRD
},
1525 { "tcdb", 0x11, INSTR_RXE_FRRD
},
1526 { "tcxb", 0x12, INSTR_RXE_FRRD
},
1527 { "sqeb", 0x14, INSTR_RXE_FRRD
},
1528 { "sqdb", 0x15, INSTR_RXE_FRRD
},
1529 { "meeb", 0x17, INSTR_RXE_FRRD
},
1530 { "kdb", 0x18, INSTR_RXE_FRRD
},
1531 { "cdb", 0x19, INSTR_RXE_FRRD
},
1532 { "adb", 0x1a, INSTR_RXE_FRRD
},
1533 { "sdb", 0x1b, INSTR_RXE_FRRD
},
1534 { "mdb", 0x1c, INSTR_RXE_FRRD
},
1535 { "ddb", 0x1d, INSTR_RXE_FRRD
},
1536 { "madb", 0x1e, INSTR_RXF_FRRDF
},
1537 { "msdb", 0x1f, INSTR_RXF_FRRDF
},
1538 { "lde", 0x24, INSTR_RXE_FRRD
},
1539 { "lxd", 0x25, INSTR_RXE_FRRD
},
1540 { "lxe", 0x26, INSTR_RXE_FRRD
},
1541 { "mae", 0x2e, INSTR_RXF_FRRDF
},
1542 { "mse", 0x2f, INSTR_RXF_FRRDF
},
1543 { "sqe", 0x34, INSTR_RXE_FRRD
},
1544 { "sqd", 0x35, INSTR_RXE_FRRD
},
1545 { "mee", 0x37, INSTR_RXE_FRRD
},
1546 { "mad", 0x3e, INSTR_RXF_FRRDF
},
1547 { "msd", 0x3f, INSTR_RXF_FRRDF
},
1548 { "", 0, INSTR_INVALID
}
1551 /* Extracts an operand value from an instruction. */
1552 static unsigned int extract_operand(unsigned char *code
,
1553 const struct s390_operand
*operand
)
1558 /* Extract fragments of the operand byte for byte. */
1559 code
+= operand
->shift
/ 8;
1560 bits
= (operand
->shift
& 7) + operand
->bits
;
1564 val
|= (unsigned int) *code
++;
1568 val
&= ((1U << (operand
->bits
- 1)) << 1) - 1;
1570 /* Check for special long displacement case. */
1571 if (operand
->bits
== 20 && operand
->shift
== 20)
1572 val
= (val
& 0xff) << 12 | (val
& 0xfff00) >> 8;
1574 /* Sign extend value if the operand is signed or pc relative. */
1575 if ((operand
->flags
& (OPERAND_SIGNED
| OPERAND_PCREL
)) &&
1576 (val
& (1U << (operand
->bits
- 1))))
1577 val
|= (-1U << (operand
->bits
- 1)) << 1;
1579 /* Double value if the operand is pc relative. */
1580 if (operand
->flags
& OPERAND_PCREL
)
1583 /* Length x in an instructions has real length x + 1. */
1584 if (operand
->flags
& OPERAND_LENGTH
)
1589 struct s390_insn
*find_insn(unsigned char *code
)
1591 unsigned char opfrag
= code
[1];
1592 unsigned char opmask
;
1593 struct s390_insn
*table
;
1659 while (table
->format
!= INSTR_INVALID
) {
1660 opmask
= formats
[table
->format
][0];
1661 if (table
->opfrag
== (opfrag
& opmask
))
1669 * insn_to_mnemonic - decode an s390 instruction
1670 * @instruction: instruction to decode
1671 * @buf: buffer to fill with mnemonic
1672 * @len: length of buffer
1674 * Decode the instruction at @instruction and store the corresponding
1675 * mnemonic into @buf of length @len.
1676 * @buf is left unchanged if the instruction could not be decoded.
1678 * %0 on success, %-ENOENT if the instruction was not found.
1680 int insn_to_mnemonic(unsigned char *instruction
, char *buf
, unsigned int len
)
1682 struct s390_insn
*insn
;
1684 insn
= find_insn(instruction
);
1687 if (insn
->name
[0] == '\0')
1688 snprintf(buf
, len
, "%s",
1689 long_insn_name
[(int) insn
->name
[1]]);
1691 snprintf(buf
, len
, "%.5s", insn
->name
);
1694 EXPORT_SYMBOL_GPL(insn_to_mnemonic
);
1696 static int print_insn(char *buffer
, unsigned char *code
, unsigned long addr
)
1698 struct s390_insn
*insn
;
1699 const unsigned char *ops
;
1700 const struct s390_operand
*operand
;
1707 insn
= find_insn(code
);
1709 if (insn
->name
[0] == '\0')
1710 ptr
+= sprintf(ptr
, "%s\t",
1711 long_insn_name
[(int) insn
->name
[1]]);
1713 ptr
+= sprintf(ptr
, "%.5s\t", insn
->name
);
1714 /* Extract the operands. */
1716 for (ops
= formats
[insn
->format
] + 1, i
= 0;
1717 *ops
!= 0 && i
< 6; ops
++, i
++) {
1718 operand
= operands
+ *ops
;
1719 value
= extract_operand(code
, operand
);
1720 if ((operand
->flags
& OPERAND_INDEX
) && value
== 0)
1722 if ((operand
->flags
& OPERAND_BASE
) &&
1723 value
== 0 && separator
== '(') {
1728 ptr
+= sprintf(ptr
, "%c", separator
);
1729 if (operand
->flags
& OPERAND_GPR
)
1730 ptr
+= sprintf(ptr
, "%%r%i", value
);
1731 else if (operand
->flags
& OPERAND_FPR
)
1732 ptr
+= sprintf(ptr
, "%%f%i", value
);
1733 else if (operand
->flags
& OPERAND_AR
)
1734 ptr
+= sprintf(ptr
, "%%a%i", value
);
1735 else if (operand
->flags
& OPERAND_CR
)
1736 ptr
+= sprintf(ptr
, "%%c%i", value
);
1737 else if (operand
->flags
& OPERAND_PCREL
)
1738 ptr
+= sprintf(ptr
, "%lx", (signed int) value
1740 else if (operand
->flags
& OPERAND_SIGNED
)
1741 ptr
+= sprintf(ptr
, "%i", value
);
1743 ptr
+= sprintf(ptr
, "%u", value
);
1744 if (operand
->flags
& OPERAND_DISP
)
1746 else if (operand
->flags
& OPERAND_BASE
) {
1747 ptr
+= sprintf(ptr
, ")");
1753 ptr
+= sprintf(ptr
, "unknown");
1754 return (int) (ptr
- buffer
);
1757 void show_code(struct pt_regs
*regs
)
1759 char *mode
= user_mode(regs
) ? "User" : "Krnl";
1760 unsigned char code
[64];
1761 char buffer
[64], *ptr
;
1762 mm_segment_t old_fs
;
1764 int start
, end
, opsize
, hops
, i
;
1766 /* Get a snapshot of the 64 bytes surrounding the fault address. */
1768 set_fs(user_mode(regs
) ? USER_DS
: KERNEL_DS
);
1769 for (start
= 32; start
&& regs
->psw
.addr
>= 34 - start
; start
-= 2) {
1770 addr
= regs
->psw
.addr
- 34 + start
;
1771 if (__copy_from_user(code
+ start
- 2,
1772 (char __user
*) addr
, 2))
1775 for (end
= 32; end
< 64; end
+= 2) {
1776 addr
= regs
->psw
.addr
+ end
- 32;
1777 if (__copy_from_user(code
+ end
,
1778 (char __user
*) addr
, 2))
1782 /* Code snapshot useable ? */
1783 if ((regs
->psw
.addr
& 1) || start
>= end
) {
1784 printk("%s Code: Bad PSW.\n", mode
);
1787 /* Find a starting point for the disassembly. */
1788 while (start
< 32) {
1789 for (i
= 0, hops
= 0; start
+ i
< 32 && hops
< 3; hops
++) {
1790 if (!find_insn(code
+ start
+ i
))
1792 i
+= insn_length(code
[start
+ i
]);
1794 if (start
+ i
== 32)
1795 /* Looks good, sequence ends at PSW. */
1799 /* Decode the instructions. */
1801 ptr
+= sprintf(ptr
, "%s Code:", mode
);
1803 while (start
< end
&& hops
< 8) {
1804 opsize
= insn_length(code
[start
]);
1805 if (start
+ opsize
== 32)
1807 else if (start
== 32)
1811 addr
= regs
->psw
.addr
+ start
- 32;
1812 ptr
+= sprintf(ptr
, ONELONG
, addr
);
1813 if (start
+ opsize
>= end
)
1815 for (i
= 0; i
< opsize
; i
++)
1816 ptr
+= sprintf(ptr
, "%02x", code
[start
+ i
]);
1820 ptr
+= print_insn(ptr
, code
+ start
, addr
);
1824 ptr
+= sprintf(ptr
, "\n ");
1830 void print_fn_code(unsigned char *code
, unsigned long len
)
1832 char buffer
[64], *ptr
;
1837 opsize
= insn_length(*code
);
1840 ptr
+= sprintf(ptr
, "%p: ", code
);
1841 for (i
= 0; i
< opsize
; i
++)
1842 ptr
+= sprintf(ptr
, "%02x", code
[i
]);
1846 ptr
+= print_insn(ptr
, code
, (unsigned long) code
);