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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/hid
[mirror_ubuntu-artful-kernel.git] / arch / s390 / kernel / entry.S
1 /*
2 * S390 low-level entry points.
3 *
4 * Copyright IBM Corp. 1999, 2012
5 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
6 * Hartmut Penner (hp@de.ibm.com),
7 * Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com),
8 * Heiko Carstens <heiko.carstens@de.ibm.com>
9 */
10
11 #include <linux/init.h>
12 #include <linux/linkage.h>
13 #include <asm/processor.h>
14 #include <asm/cache.h>
15 #include <asm/errno.h>
16 #include <asm/ptrace.h>
17 #include <asm/thread_info.h>
18 #include <asm/asm-offsets.h>
19 #include <asm/unistd.h>
20 #include <asm/page.h>
21 #include <asm/sigp.h>
22 #include <asm/irq.h>
23 #include <asm/vx-insn.h>
24 #include <asm/setup.h>
25 #include <asm/nmi.h>
26 #include <asm/export.h>
27
28 __PT_R0 = __PT_GPRS
29 __PT_R1 = __PT_GPRS + 8
30 __PT_R2 = __PT_GPRS + 16
31 __PT_R3 = __PT_GPRS + 24
32 __PT_R4 = __PT_GPRS + 32
33 __PT_R5 = __PT_GPRS + 40
34 __PT_R6 = __PT_GPRS + 48
35 __PT_R7 = __PT_GPRS + 56
36 __PT_R8 = __PT_GPRS + 64
37 __PT_R9 = __PT_GPRS + 72
38 __PT_R10 = __PT_GPRS + 80
39 __PT_R11 = __PT_GPRS + 88
40 __PT_R12 = __PT_GPRS + 96
41 __PT_R13 = __PT_GPRS + 104
42 __PT_R14 = __PT_GPRS + 112
43 __PT_R15 = __PT_GPRS + 120
44
45 STACK_SHIFT = PAGE_SHIFT + THREAD_SIZE_ORDER
46 STACK_SIZE = 1 << STACK_SHIFT
47 STACK_INIT = STACK_SIZE - STACK_FRAME_OVERHEAD - __PT_SIZE
48
49 _TIF_WORK = (_TIF_SIGPENDING | _TIF_NOTIFY_RESUME | _TIF_NEED_RESCHED | \
50 _TIF_UPROBE | _TIF_GUARDED_STORAGE)
51 _TIF_TRACE = (_TIF_SYSCALL_TRACE | _TIF_SYSCALL_AUDIT | _TIF_SECCOMP | \
52 _TIF_SYSCALL_TRACEPOINT)
53 _CIF_WORK = (_CIF_MCCK_PENDING | _CIF_ASCE_PRIMARY | \
54 _CIF_ASCE_SECONDARY | _CIF_FPU)
55 _PIF_WORK = (_PIF_PER_TRAP)
56
57 #define BASED(name) name-cleanup_critical(%r13)
58
59 .macro TRACE_IRQS_ON
60 #ifdef CONFIG_TRACE_IRQFLAGS
61 basr %r2,%r0
62 brasl %r14,trace_hardirqs_on_caller
63 #endif
64 .endm
65
66 .macro TRACE_IRQS_OFF
67 #ifdef CONFIG_TRACE_IRQFLAGS
68 basr %r2,%r0
69 brasl %r14,trace_hardirqs_off_caller
70 #endif
71 .endm
72
73 .macro LOCKDEP_SYS_EXIT
74 #ifdef CONFIG_LOCKDEP
75 tm __PT_PSW+1(%r11),0x01 # returning to user ?
76 jz .+10
77 brasl %r14,lockdep_sys_exit
78 #endif
79 .endm
80
81 .macro CHECK_STACK stacksize,savearea
82 #ifdef CONFIG_CHECK_STACK
83 tml %r15,\stacksize - CONFIG_STACK_GUARD
84 lghi %r14,\savearea
85 jz stack_overflow
86 #endif
87 .endm
88
89 .macro SWITCH_ASYNC savearea,timer
90 tmhh %r8,0x0001 # interrupting from user ?
91 jnz 1f
92 lgr %r14,%r9
93 slg %r14,BASED(.Lcritical_start)
94 clg %r14,BASED(.Lcritical_length)
95 jhe 0f
96 lghi %r11,\savearea # inside critical section, do cleanup
97 brasl %r14,cleanup_critical
98 tmhh %r8,0x0001 # retest problem state after cleanup
99 jnz 1f
100 0: lg %r14,__LC_ASYNC_STACK # are we already on the async stack?
101 slgr %r14,%r15
102 srag %r14,%r14,STACK_SHIFT
103 jnz 2f
104 CHECK_STACK 1<<STACK_SHIFT,\savearea
105 aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
106 j 3f
107 1: UPDATE_VTIME %r14,%r15,\timer
108 2: lg %r15,__LC_ASYNC_STACK # load async stack
109 3: la %r11,STACK_FRAME_OVERHEAD(%r15)
110 .endm
111
112 .macro UPDATE_VTIME w1,w2,enter_timer
113 lg \w1,__LC_EXIT_TIMER
114 lg \w2,__LC_LAST_UPDATE_TIMER
115 slg \w1,\enter_timer
116 slg \w2,__LC_EXIT_TIMER
117 alg \w1,__LC_USER_TIMER
118 alg \w2,__LC_SYSTEM_TIMER
119 stg \w1,__LC_USER_TIMER
120 stg \w2,__LC_SYSTEM_TIMER
121 mvc __LC_LAST_UPDATE_TIMER(8),\enter_timer
122 .endm
123
124 .macro REENABLE_IRQS
125 stg %r8,__LC_RETURN_PSW
126 ni __LC_RETURN_PSW,0xbf
127 ssm __LC_RETURN_PSW
128 .endm
129
130 .macro STCK savearea
131 #ifdef CONFIG_HAVE_MARCH_Z9_109_FEATURES
132 .insn s,0xb27c0000,\savearea # store clock fast
133 #else
134 .insn s,0xb2050000,\savearea # store clock
135 #endif
136 .endm
137
138 /*
139 * The TSTMSK macro generates a test-under-mask instruction by
140 * calculating the memory offset for the specified mask value.
141 * Mask value can be any constant. The macro shifts the mask
142 * value to calculate the memory offset for the test-under-mask
143 * instruction.
144 */
145 .macro TSTMSK addr, mask, size=8, bytepos=0
146 .if (\bytepos < \size) && (\mask >> 8)
147 .if (\mask & 0xff)
148 .error "Mask exceeds byte boundary"
149 .endif
150 TSTMSK \addr, "(\mask >> 8)", \size, "(\bytepos + 1)"
151 .exitm
152 .endif
153 .ifeq \mask
154 .error "Mask must not be zero"
155 .endif
156 off = \size - \bytepos - 1
157 tm off+\addr, \mask
158 .endm
159
160 .section .kprobes.text, "ax"
161 .Ldummy:
162 /*
163 * This nop exists only in order to avoid that __switch_to starts at
164 * the beginning of the kprobes text section. In that case we would
165 * have several symbols at the same address. E.g. objdump would take
166 * an arbitrary symbol name when disassembling this code.
167 * With the added nop in between the __switch_to symbol is unique
168 * again.
169 */
170 nop 0
171
172 /*
173 * Scheduler resume function, called by switch_to
174 * gpr2 = (task_struct *) prev
175 * gpr3 = (task_struct *) next
176 * Returns:
177 * gpr2 = prev
178 */
179 ENTRY(__switch_to)
180 stmg %r6,%r15,__SF_GPRS(%r15) # store gprs of prev task
181 lgr %r1,%r2
182 aghi %r1,__TASK_thread # thread_struct of prev task
183 lg %r5,__TASK_stack(%r3) # start of kernel stack of next
184 stg %r15,__THREAD_ksp(%r1) # store kernel stack of prev
185 lgr %r1,%r3
186 aghi %r1,__TASK_thread # thread_struct of next task
187 lgr %r15,%r5
188 aghi %r15,STACK_INIT # end of kernel stack of next
189 stg %r3,__LC_CURRENT # store task struct of next
190 stg %r15,__LC_KERNEL_STACK # store end of kernel stack
191 lg %r15,__THREAD_ksp(%r1) # load kernel stack of next
192 mvc __LC_CURRENT_PID(4,%r0),__TASK_pid(%r3) # store pid of next
193 lmg %r6,%r15,__SF_GPRS(%r15) # load gprs of next task
194 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_LPP
195 bzr %r14
196 .insn s,0xb2800000,__LC_LPP # set program parameter
197 br %r14
198
199 .L__critical_start:
200
201 #if IS_ENABLED(CONFIG_KVM)
202 /*
203 * sie64a calling convention:
204 * %r2 pointer to sie control block
205 * %r3 guest register save area
206 */
207 ENTRY(sie64a)
208 stmg %r6,%r14,__SF_GPRS(%r15) # save kernel registers
209 stg %r2,__SF_EMPTY(%r15) # save control block pointer
210 stg %r3,__SF_EMPTY+8(%r15) # save guest register save area
211 xc __SF_EMPTY+16(8,%r15),__SF_EMPTY+16(%r15) # reason code = 0
212 TSTMSK __LC_CPU_FLAGS,_CIF_FPU # load guest fp/vx registers ?
213 jno .Lsie_load_guest_gprs
214 brasl %r14,load_fpu_regs # load guest fp/vx regs
215 .Lsie_load_guest_gprs:
216 lmg %r0,%r13,0(%r3) # load guest gprs 0-13
217 lg %r14,__LC_GMAP # get gmap pointer
218 ltgr %r14,%r14
219 jz .Lsie_gmap
220 lctlg %c1,%c1,__GMAP_ASCE(%r14) # load primary asce
221 .Lsie_gmap:
222 lg %r14,__SF_EMPTY(%r15) # get control block pointer
223 oi __SIE_PROG0C+3(%r14),1 # we are going into SIE now
224 tm __SIE_PROG20+3(%r14),3 # last exit...
225 jnz .Lsie_skip
226 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
227 jo .Lsie_skip # exit if fp/vx regs changed
228 sie 0(%r14)
229 .Lsie_skip:
230 ni __SIE_PROG0C+3(%r14),0xfe # no longer in SIE
231 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
232 .Lsie_done:
233 # some program checks are suppressing. C code (e.g. do_protection_exception)
234 # will rewind the PSW by the ILC, which is 4 bytes in case of SIE. Other
235 # instructions between sie64a and .Lsie_done should not cause program
236 # interrupts. So lets use a nop (47 00 00 00) as a landing pad.
237 # See also .Lcleanup_sie
238 .Lrewind_pad:
239 nop 0
240 .globl sie_exit
241 sie_exit:
242 lg %r14,__SF_EMPTY+8(%r15) # load guest register save area
243 stmg %r0,%r13,0(%r14) # save guest gprs 0-13
244 lmg %r6,%r14,__SF_GPRS(%r15) # restore kernel registers
245 lg %r2,__SF_EMPTY+16(%r15) # return exit reason code
246 br %r14
247 .Lsie_fault:
248 lghi %r14,-EFAULT
249 stg %r14,__SF_EMPTY+16(%r15) # set exit reason code
250 j sie_exit
251
252 EX_TABLE(.Lrewind_pad,.Lsie_fault)
253 EX_TABLE(sie_exit,.Lsie_fault)
254 EXPORT_SYMBOL(sie64a)
255 EXPORT_SYMBOL(sie_exit)
256 #endif
257
258 /*
259 * SVC interrupt handler routine. System calls are synchronous events and
260 * are executed with interrupts enabled.
261 */
262
263 ENTRY(system_call)
264 stpt __LC_SYNC_ENTER_TIMER
265 .Lsysc_stmg:
266 stmg %r8,%r15,__LC_SAVE_AREA_SYNC
267 lg %r12,__LC_CURRENT
268 lghi %r13,__TASK_thread
269 lghi %r14,_PIF_SYSCALL
270 .Lsysc_per:
271 lg %r15,__LC_KERNEL_STACK
272 la %r11,STACK_FRAME_OVERHEAD(%r15) # pointer to pt_regs
273 .Lsysc_vtime:
274 UPDATE_VTIME %r8,%r9,__LC_SYNC_ENTER_TIMER
275 stmg %r0,%r7,__PT_R0(%r11)
276 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
277 mvc __PT_PSW(16,%r11),__LC_SVC_OLD_PSW
278 mvc __PT_INT_CODE(4,%r11),__LC_SVC_ILC
279 stg %r14,__PT_FLAGS(%r11)
280 .Lsysc_do_svc:
281 # load address of system call table
282 lg %r10,__THREAD_sysc_table(%r13,%r12)
283 llgh %r8,__PT_INT_CODE+2(%r11)
284 slag %r8,%r8,2 # shift and test for svc 0
285 jnz .Lsysc_nr_ok
286 # svc 0: system call number in %r1
287 llgfr %r1,%r1 # clear high word in r1
288 cghi %r1,NR_syscalls
289 jnl .Lsysc_nr_ok
290 sth %r1,__PT_INT_CODE+2(%r11)
291 slag %r8,%r1,2
292 .Lsysc_nr_ok:
293 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
294 stg %r2,__PT_ORIG_GPR2(%r11)
295 stg %r7,STACK_FRAME_OVERHEAD(%r15)
296 lgf %r9,0(%r8,%r10) # get system call add.
297 TSTMSK __TI_flags(%r12),_TIF_TRACE
298 jnz .Lsysc_tracesys
299 basr %r14,%r9 # call sys_xxxx
300 stg %r2,__PT_R2(%r11) # store return value
301
302 .Lsysc_return:
303 LOCKDEP_SYS_EXIT
304 .Lsysc_tif:
305 TSTMSK __PT_FLAGS(%r11),_PIF_WORK
306 jnz .Lsysc_work
307 TSTMSK __TI_flags(%r12),_TIF_WORK
308 jnz .Lsysc_work # check for work
309 TSTMSK __LC_CPU_FLAGS,_CIF_WORK
310 jnz .Lsysc_work
311 .Lsysc_restore:
312 lg %r14,__LC_VDSO_PER_CPU
313 lmg %r0,%r10,__PT_R0(%r11)
314 mvc __LC_RETURN_PSW(16),__PT_PSW(%r11)
315 stpt __LC_EXIT_TIMER
316 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
317 lmg %r11,%r15,__PT_R11(%r11)
318 lpswe __LC_RETURN_PSW
319 .Lsysc_done:
320
321 #
322 # One of the work bits is on. Find out which one.
323 #
324 .Lsysc_work:
325 TSTMSK __LC_CPU_FLAGS,_CIF_MCCK_PENDING
326 jo .Lsysc_mcck_pending
327 TSTMSK __TI_flags(%r12),_TIF_NEED_RESCHED
328 jo .Lsysc_reschedule
329 #ifdef CONFIG_UPROBES
330 TSTMSK __TI_flags(%r12),_TIF_UPROBE
331 jo .Lsysc_uprobe_notify
332 #endif
333 TSTMSK __TI_flags(%r12),_TIF_GUARDED_STORAGE
334 jo .Lsysc_guarded_storage
335 TSTMSK __PT_FLAGS(%r11),_PIF_PER_TRAP
336 jo .Lsysc_singlestep
337 TSTMSK __TI_flags(%r12),_TIF_SIGPENDING
338 jo .Lsysc_sigpending
339 TSTMSK __TI_flags(%r12),_TIF_NOTIFY_RESUME
340 jo .Lsysc_notify_resume
341 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
342 jo .Lsysc_vxrs
343 TSTMSK __LC_CPU_FLAGS,(_CIF_ASCE_PRIMARY|_CIF_ASCE_SECONDARY)
344 jnz .Lsysc_asce
345 j .Lsysc_return # beware of critical section cleanup
346
347 #
348 # _TIF_NEED_RESCHED is set, call schedule
349 #
350 .Lsysc_reschedule:
351 larl %r14,.Lsysc_return
352 jg schedule
353
354 #
355 # _CIF_MCCK_PENDING is set, call handler
356 #
357 .Lsysc_mcck_pending:
358 larl %r14,.Lsysc_return
359 jg s390_handle_mcck # TIF bit will be cleared by handler
360
361 #
362 # _CIF_ASCE_PRIMARY and/or CIF_ASCE_SECONDARY set, load user space asce
363 #
364 .Lsysc_asce:
365 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_PRIMARY
366 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
367 TSTMSK __LC_CPU_FLAGS,_CIF_ASCE_SECONDARY
368 jz .Lsysc_return
369 larl %r14,.Lsysc_return
370 jg set_fs_fixup
371
372 #
373 # CIF_FPU is set, restore floating-point controls and floating-point registers.
374 #
375 .Lsysc_vxrs:
376 larl %r14,.Lsysc_return
377 jg load_fpu_regs
378
379 #
380 # _TIF_SIGPENDING is set, call do_signal
381 #
382 .Lsysc_sigpending:
383 lgr %r2,%r11 # pass pointer to pt_regs
384 brasl %r14,do_signal
385 TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL
386 jno .Lsysc_return
387 .Lsysc_do_syscall:
388 lghi %r13,__TASK_thread
389 lmg %r2,%r7,__PT_R2(%r11) # load svc arguments
390 lghi %r1,0 # svc 0 returns -ENOSYS
391 j .Lsysc_do_svc
392
393 #
394 # _TIF_NOTIFY_RESUME is set, call do_notify_resume
395 #
396 .Lsysc_notify_resume:
397 lgr %r2,%r11 # pass pointer to pt_regs
398 larl %r14,.Lsysc_return
399 jg do_notify_resume
400
401 #
402 # _TIF_UPROBE is set, call uprobe_notify_resume
403 #
404 #ifdef CONFIG_UPROBES
405 .Lsysc_uprobe_notify:
406 lgr %r2,%r11 # pass pointer to pt_regs
407 larl %r14,.Lsysc_return
408 jg uprobe_notify_resume
409 #endif
410
411 #
412 # _TIF_GUARDED_STORAGE is set, call guarded_storage_load
413 #
414 .Lsysc_guarded_storage:
415 lgr %r2,%r11 # pass pointer to pt_regs
416 larl %r14,.Lsysc_return
417 jg gs_load_bc_cb
418
419 #
420 # _PIF_PER_TRAP is set, call do_per_trap
421 #
422 .Lsysc_singlestep:
423 ni __PT_FLAGS+7(%r11),255-_PIF_PER_TRAP
424 lgr %r2,%r11 # pass pointer to pt_regs
425 larl %r14,.Lsysc_return
426 jg do_per_trap
427
428 #
429 # call tracehook_report_syscall_entry/tracehook_report_syscall_exit before
430 # and after the system call
431 #
432 .Lsysc_tracesys:
433 lgr %r2,%r11 # pass pointer to pt_regs
434 la %r3,0
435 llgh %r0,__PT_INT_CODE+2(%r11)
436 stg %r0,__PT_R2(%r11)
437 brasl %r14,do_syscall_trace_enter
438 lghi %r0,NR_syscalls
439 clgr %r0,%r2
440 jnh .Lsysc_tracenogo
441 sllg %r8,%r2,2
442 lgf %r9,0(%r8,%r10)
443 .Lsysc_tracego:
444 lmg %r3,%r7,__PT_R3(%r11)
445 stg %r7,STACK_FRAME_OVERHEAD(%r15)
446 lg %r2,__PT_ORIG_GPR2(%r11)
447 basr %r14,%r9 # call sys_xxx
448 stg %r2,__PT_R2(%r11) # store return value
449 .Lsysc_tracenogo:
450 TSTMSK __TI_flags(%r12),_TIF_TRACE
451 jz .Lsysc_return
452 lgr %r2,%r11 # pass pointer to pt_regs
453 larl %r14,.Lsysc_return
454 jg do_syscall_trace_exit
455
456 #
457 # a new process exits the kernel with ret_from_fork
458 #
459 ENTRY(ret_from_fork)
460 la %r11,STACK_FRAME_OVERHEAD(%r15)
461 lg %r12,__LC_CURRENT
462 brasl %r14,schedule_tail
463 TRACE_IRQS_ON
464 ssm __LC_SVC_NEW_PSW # reenable interrupts
465 tm __PT_PSW+1(%r11),0x01 # forking a kernel thread ?
466 jne .Lsysc_tracenogo
467 # it's a kernel thread
468 lmg %r9,%r10,__PT_R9(%r11) # load gprs
469 ENTRY(kernel_thread_starter)
470 la %r2,0(%r10)
471 basr %r14,%r9
472 j .Lsysc_tracenogo
473
474 /*
475 * Program check handler routine
476 */
477
478 ENTRY(pgm_check_handler)
479 stpt __LC_SYNC_ENTER_TIMER
480 stmg %r8,%r15,__LC_SAVE_AREA_SYNC
481 lg %r10,__LC_LAST_BREAK
482 lg %r12,__LC_CURRENT
483 larl %r13,cleanup_critical
484 lmg %r8,%r9,__LC_PGM_OLD_PSW
485 tmhh %r8,0x0001 # test problem state bit
486 jnz 2f # -> fault in user space
487 #if IS_ENABLED(CONFIG_KVM)
488 # cleanup critical section for sie64a
489 lgr %r14,%r9
490 slg %r14,BASED(.Lsie_critical_start)
491 clg %r14,BASED(.Lsie_critical_length)
492 jhe 0f
493 brasl %r14,.Lcleanup_sie
494 #endif
495 0: tmhh %r8,0x4000 # PER bit set in old PSW ?
496 jnz 1f # -> enabled, can't be a double fault
497 tm __LC_PGM_ILC+3,0x80 # check for per exception
498 jnz .Lpgm_svcper # -> single stepped svc
499 1: CHECK_STACK STACK_SIZE,__LC_SAVE_AREA_SYNC
500 aghi %r15,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
501 j 4f
502 2: UPDATE_VTIME %r14,%r15,__LC_SYNC_ENTER_TIMER
503 lg %r15,__LC_KERNEL_STACK
504 lgr %r14,%r12
505 aghi %r14,__TASK_thread # pointer to thread_struct
506 lghi %r13,__LC_PGM_TDB
507 tm __LC_PGM_ILC+2,0x02 # check for transaction abort
508 jz 3f
509 mvc __THREAD_trap_tdb(256,%r14),0(%r13)
510 3: stg %r10,__THREAD_last_break(%r14)
511 4: la %r11,STACK_FRAME_OVERHEAD(%r15)
512 stmg %r0,%r7,__PT_R0(%r11)
513 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_SYNC
514 stmg %r8,%r9,__PT_PSW(%r11)
515 mvc __PT_INT_CODE(4,%r11),__LC_PGM_ILC
516 mvc __PT_INT_PARM_LONG(8,%r11),__LC_TRANS_EXC_CODE
517 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
518 stg %r10,__PT_ARGS(%r11)
519 tm __LC_PGM_ILC+3,0x80 # check for per exception
520 jz 5f
521 tmhh %r8,0x0001 # kernel per event ?
522 jz .Lpgm_kprobe
523 oi __PT_FLAGS+7(%r11),_PIF_PER_TRAP
524 mvc __THREAD_per_address(8,%r14),__LC_PER_ADDRESS
525 mvc __THREAD_per_cause(2,%r14),__LC_PER_CODE
526 mvc __THREAD_per_paid(1,%r14),__LC_PER_ACCESS_ID
527 5: REENABLE_IRQS
528 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
529 larl %r1,pgm_check_table
530 llgh %r10,__PT_INT_CODE+2(%r11)
531 nill %r10,0x007f
532 sll %r10,2
533 je .Lpgm_return
534 lgf %r1,0(%r10,%r1) # load address of handler routine
535 lgr %r2,%r11 # pass pointer to pt_regs
536 basr %r14,%r1 # branch to interrupt-handler
537 .Lpgm_return:
538 LOCKDEP_SYS_EXIT
539 tm __PT_PSW+1(%r11),0x01 # returning to user ?
540 jno .Lsysc_restore
541 TSTMSK __PT_FLAGS(%r11),_PIF_SYSCALL
542 jo .Lsysc_do_syscall
543 j .Lsysc_tif
544
545 #
546 # PER event in supervisor state, must be kprobes
547 #
548 .Lpgm_kprobe:
549 REENABLE_IRQS
550 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
551 lgr %r2,%r11 # pass pointer to pt_regs
552 brasl %r14,do_per_trap
553 j .Lpgm_return
554
555 #
556 # single stepped system call
557 #
558 .Lpgm_svcper:
559 mvc __LC_RETURN_PSW(8),__LC_SVC_NEW_PSW
560 lghi %r13,__TASK_thread
561 larl %r14,.Lsysc_per
562 stg %r14,__LC_RETURN_PSW+8
563 lghi %r14,_PIF_SYSCALL | _PIF_PER_TRAP
564 lpswe __LC_RETURN_PSW # branch to .Lsysc_per and enable irqs
565
566 /*
567 * IO interrupt handler routine
568 */
569 ENTRY(io_int_handler)
570 STCK __LC_INT_CLOCK
571 stpt __LC_ASYNC_ENTER_TIMER
572 stmg %r8,%r15,__LC_SAVE_AREA_ASYNC
573 lg %r12,__LC_CURRENT
574 larl %r13,cleanup_critical
575 lmg %r8,%r9,__LC_IO_OLD_PSW
576 SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_ENTER_TIMER
577 stmg %r0,%r7,__PT_R0(%r11)
578 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
579 stmg %r8,%r9,__PT_PSW(%r11)
580 mvc __PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID
581 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
582 TSTMSK __LC_CPU_FLAGS,_CIF_IGNORE_IRQ
583 jo .Lio_restore
584 TRACE_IRQS_OFF
585 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
586 .Lio_loop:
587 lgr %r2,%r11 # pass pointer to pt_regs
588 lghi %r3,IO_INTERRUPT
589 tm __PT_INT_CODE+8(%r11),0x80 # adapter interrupt ?
590 jz .Lio_call
591 lghi %r3,THIN_INTERRUPT
592 .Lio_call:
593 brasl %r14,do_IRQ
594 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_LPAR
595 jz .Lio_return
596 tpi 0
597 jz .Lio_return
598 mvc __PT_INT_CODE(12,%r11),__LC_SUBCHANNEL_ID
599 j .Lio_loop
600 .Lio_return:
601 LOCKDEP_SYS_EXIT
602 TRACE_IRQS_ON
603 .Lio_tif:
604 TSTMSK __TI_flags(%r12),_TIF_WORK
605 jnz .Lio_work # there is work to do (signals etc.)
606 TSTMSK __LC_CPU_FLAGS,_CIF_WORK
607 jnz .Lio_work
608 .Lio_restore:
609 lg %r14,__LC_VDSO_PER_CPU
610 lmg %r0,%r10,__PT_R0(%r11)
611 mvc __LC_RETURN_PSW(16),__PT_PSW(%r11)
612 stpt __LC_EXIT_TIMER
613 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
614 lmg %r11,%r15,__PT_R11(%r11)
615 lpswe __LC_RETURN_PSW
616 .Lio_done:
617
618 #
619 # There is work todo, find out in which context we have been interrupted:
620 # 1) if we return to user space we can do all _TIF_WORK work
621 # 2) if we return to kernel code and kvm is enabled check if we need to
622 # modify the psw to leave SIE
623 # 3) if we return to kernel code and preemptive scheduling is enabled check
624 # the preemption counter and if it is zero call preempt_schedule_irq
625 # Before any work can be done, a switch to the kernel stack is required.
626 #
627 .Lio_work:
628 tm __PT_PSW+1(%r11),0x01 # returning to user ?
629 jo .Lio_work_user # yes -> do resched & signal
630 #ifdef CONFIG_PREEMPT
631 # check for preemptive scheduling
632 icm %r0,15,__LC_PREEMPT_COUNT
633 jnz .Lio_restore # preemption is disabled
634 TSTMSK __TI_flags(%r12),_TIF_NEED_RESCHED
635 jno .Lio_restore
636 # switch to kernel stack
637 lg %r1,__PT_R15(%r11)
638 aghi %r1,-(STACK_FRAME_OVERHEAD + __PT_SIZE)
639 mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
640 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
641 la %r11,STACK_FRAME_OVERHEAD(%r1)
642 lgr %r15,%r1
643 # TRACE_IRQS_ON already done at .Lio_return, call
644 # TRACE_IRQS_OFF to keep things symmetrical
645 TRACE_IRQS_OFF
646 brasl %r14,preempt_schedule_irq
647 j .Lio_return
648 #else
649 j .Lio_restore
650 #endif
651
652 #
653 # Need to do work before returning to userspace, switch to kernel stack
654 #
655 .Lio_work_user:
656 lg %r1,__LC_KERNEL_STACK
657 mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
658 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
659 la %r11,STACK_FRAME_OVERHEAD(%r1)
660 lgr %r15,%r1
661
662 #
663 # One of the work bits is on. Find out which one.
664 #
665 .Lio_work_tif:
666 TSTMSK __LC_CPU_FLAGS,_CIF_MCCK_PENDING
667 jo .Lio_mcck_pending
668 TSTMSK __TI_flags(%r12),_TIF_NEED_RESCHED
669 jo .Lio_reschedule
670 TSTMSK __TI_flags(%r12),_TIF_SIGPENDING
671 jo .Lio_sigpending
672 TSTMSK __TI_flags(%r12),_TIF_NOTIFY_RESUME
673 jo .Lio_notify_resume
674 TSTMSK __TI_flags(%r12),_TIF_GUARDED_STORAGE
675 jo .Lio_guarded_storage
676 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
677 jo .Lio_vxrs
678 TSTMSK __LC_CPU_FLAGS,(_CIF_ASCE_PRIMARY|_CIF_ASCE_SECONDARY)
679 jnz .Lio_asce
680 j .Lio_return # beware of critical section cleanup
681
682 #
683 # _CIF_MCCK_PENDING is set, call handler
684 #
685 .Lio_mcck_pending:
686 # TRACE_IRQS_ON already done at .Lio_return
687 brasl %r14,s390_handle_mcck # TIF bit will be cleared by handler
688 TRACE_IRQS_OFF
689 j .Lio_return
690
691 #
692 # _CIF_ASCE_PRIMARY and/or CIF_ASCE_SECONDARY set, load user space asce
693 #
694 .Lio_asce:
695 ni __LC_CPU_FLAGS+7,255-_CIF_ASCE_PRIMARY
696 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
697 TSTMSK __LC_CPU_FLAGS,_CIF_ASCE_SECONDARY
698 jz .Lio_return
699 larl %r14,.Lio_return
700 jg set_fs_fixup
701
702 #
703 # CIF_FPU is set, restore floating-point controls and floating-point registers.
704 #
705 .Lio_vxrs:
706 larl %r14,.Lio_return
707 jg load_fpu_regs
708
709 #
710 # _TIF_GUARDED_STORAGE is set, call guarded_storage_load
711 #
712 .Lio_guarded_storage:
713 # TRACE_IRQS_ON already done at .Lio_return
714 ssm __LC_SVC_NEW_PSW # reenable interrupts
715 lgr %r2,%r11 # pass pointer to pt_regs
716 brasl %r14,gs_load_bc_cb
717 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
718 TRACE_IRQS_OFF
719 j .Lio_return
720
721 #
722 # _TIF_NEED_RESCHED is set, call schedule
723 #
724 .Lio_reschedule:
725 # TRACE_IRQS_ON already done at .Lio_return
726 ssm __LC_SVC_NEW_PSW # reenable interrupts
727 brasl %r14,schedule # call scheduler
728 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
729 TRACE_IRQS_OFF
730 j .Lio_return
731
732 #
733 # _TIF_SIGPENDING or is set, call do_signal
734 #
735 .Lio_sigpending:
736 # TRACE_IRQS_ON already done at .Lio_return
737 ssm __LC_SVC_NEW_PSW # reenable interrupts
738 lgr %r2,%r11 # pass pointer to pt_regs
739 brasl %r14,do_signal
740 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
741 TRACE_IRQS_OFF
742 j .Lio_return
743
744 #
745 # _TIF_NOTIFY_RESUME or is set, call do_notify_resume
746 #
747 .Lio_notify_resume:
748 # TRACE_IRQS_ON already done at .Lio_return
749 ssm __LC_SVC_NEW_PSW # reenable interrupts
750 lgr %r2,%r11 # pass pointer to pt_regs
751 brasl %r14,do_notify_resume
752 ssm __LC_PGM_NEW_PSW # disable I/O and ext. interrupts
753 TRACE_IRQS_OFF
754 j .Lio_return
755
756 /*
757 * External interrupt handler routine
758 */
759 ENTRY(ext_int_handler)
760 STCK __LC_INT_CLOCK
761 stpt __LC_ASYNC_ENTER_TIMER
762 stmg %r8,%r15,__LC_SAVE_AREA_ASYNC
763 lg %r12,__LC_CURRENT
764 larl %r13,cleanup_critical
765 lmg %r8,%r9,__LC_EXT_OLD_PSW
766 SWITCH_ASYNC __LC_SAVE_AREA_ASYNC,__LC_ASYNC_ENTER_TIMER
767 stmg %r0,%r7,__PT_R0(%r11)
768 mvc __PT_R8(64,%r11),__LC_SAVE_AREA_ASYNC
769 stmg %r8,%r9,__PT_PSW(%r11)
770 lghi %r1,__LC_EXT_PARAMS2
771 mvc __PT_INT_CODE(4,%r11),__LC_EXT_CPU_ADDR
772 mvc __PT_INT_PARM(4,%r11),__LC_EXT_PARAMS
773 mvc __PT_INT_PARM_LONG(8,%r11),0(%r1)
774 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
775 TSTMSK __LC_CPU_FLAGS,_CIF_IGNORE_IRQ
776 jo .Lio_restore
777 TRACE_IRQS_OFF
778 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
779 lgr %r2,%r11 # pass pointer to pt_regs
780 lghi %r3,EXT_INTERRUPT
781 brasl %r14,do_IRQ
782 j .Lio_return
783
784 /*
785 * Load idle PSW. The second "half" of this function is in .Lcleanup_idle.
786 */
787 ENTRY(psw_idle)
788 stg %r3,__SF_EMPTY(%r15)
789 larl %r1,.Lpsw_idle_lpsw+4
790 stg %r1,__SF_EMPTY+8(%r15)
791 #ifdef CONFIG_SMP
792 larl %r1,smp_cpu_mtid
793 llgf %r1,0(%r1)
794 ltgr %r1,%r1
795 jz .Lpsw_idle_stcctm
796 .insn rsy,0xeb0000000017,%r1,5,__SF_EMPTY+16(%r15)
797 .Lpsw_idle_stcctm:
798 #endif
799 oi __LC_CPU_FLAGS+7,_CIF_ENABLED_WAIT
800 STCK __CLOCK_IDLE_ENTER(%r2)
801 stpt __TIMER_IDLE_ENTER(%r2)
802 .Lpsw_idle_lpsw:
803 lpswe __SF_EMPTY(%r15)
804 br %r14
805 .Lpsw_idle_end:
806
807 /*
808 * Store floating-point controls and floating-point or vector register
809 * depending whether the vector facility is available. A critical section
810 * cleanup assures that the registers are stored even if interrupted for
811 * some other work. The CIF_FPU flag is set to trigger a lazy restore
812 * of the register contents at return from io or a system call.
813 */
814 ENTRY(save_fpu_regs)
815 lg %r2,__LC_CURRENT
816 aghi %r2,__TASK_thread
817 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
818 bor %r14
819 stfpc __THREAD_FPU_fpc(%r2)
820 lg %r3,__THREAD_FPU_regs(%r2)
821 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_VX
822 jz .Lsave_fpu_regs_fp # no -> store FP regs
823 VSTM %v0,%v15,0,%r3 # vstm 0,15,0(3)
824 VSTM %v16,%v31,256,%r3 # vstm 16,31,256(3)
825 j .Lsave_fpu_regs_done # -> set CIF_FPU flag
826 .Lsave_fpu_regs_fp:
827 std 0,0(%r3)
828 std 1,8(%r3)
829 std 2,16(%r3)
830 std 3,24(%r3)
831 std 4,32(%r3)
832 std 5,40(%r3)
833 std 6,48(%r3)
834 std 7,56(%r3)
835 std 8,64(%r3)
836 std 9,72(%r3)
837 std 10,80(%r3)
838 std 11,88(%r3)
839 std 12,96(%r3)
840 std 13,104(%r3)
841 std 14,112(%r3)
842 std 15,120(%r3)
843 .Lsave_fpu_regs_done:
844 oi __LC_CPU_FLAGS+7,_CIF_FPU
845 br %r14
846 .Lsave_fpu_regs_end:
847 #if IS_ENABLED(CONFIG_KVM)
848 EXPORT_SYMBOL(save_fpu_regs)
849 #endif
850
851 /*
852 * Load floating-point controls and floating-point or vector registers.
853 * A critical section cleanup assures that the register contents are
854 * loaded even if interrupted for some other work.
855 *
856 * There are special calling conventions to fit into sysc and io return work:
857 * %r15: <kernel stack>
858 * The function requires:
859 * %r4
860 */
861 load_fpu_regs:
862 lg %r4,__LC_CURRENT
863 aghi %r4,__TASK_thread
864 TSTMSK __LC_CPU_FLAGS,_CIF_FPU
865 bnor %r14
866 lfpc __THREAD_FPU_fpc(%r4)
867 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_VX
868 lg %r4,__THREAD_FPU_regs(%r4) # %r4 <- reg save area
869 jz .Lload_fpu_regs_fp # -> no VX, load FP regs
870 VLM %v0,%v15,0,%r4
871 VLM %v16,%v31,256,%r4
872 j .Lload_fpu_regs_done
873 .Lload_fpu_regs_fp:
874 ld 0,0(%r4)
875 ld 1,8(%r4)
876 ld 2,16(%r4)
877 ld 3,24(%r4)
878 ld 4,32(%r4)
879 ld 5,40(%r4)
880 ld 6,48(%r4)
881 ld 7,56(%r4)
882 ld 8,64(%r4)
883 ld 9,72(%r4)
884 ld 10,80(%r4)
885 ld 11,88(%r4)
886 ld 12,96(%r4)
887 ld 13,104(%r4)
888 ld 14,112(%r4)
889 ld 15,120(%r4)
890 .Lload_fpu_regs_done:
891 ni __LC_CPU_FLAGS+7,255-_CIF_FPU
892 br %r14
893 .Lload_fpu_regs_end:
894
895 .L__critical_end:
896
897 /*
898 * Machine check handler routines
899 */
900 ENTRY(mcck_int_handler)
901 STCK __LC_MCCK_CLOCK
902 la %r1,4095 # revalidate r1
903 spt __LC_CPU_TIMER_SAVE_AREA-4095(%r1) # revalidate cpu timer
904 lmg %r0,%r15,__LC_GPREGS_SAVE_AREA-4095(%r1)# revalidate gprs
905 lg %r12,__LC_CURRENT
906 larl %r13,cleanup_critical
907 lmg %r8,%r9,__LC_MCK_OLD_PSW
908 TSTMSK __LC_MCCK_CODE,MCCK_CODE_SYSTEM_DAMAGE
909 jo .Lmcck_panic # yes -> rest of mcck code invalid
910 lghi %r14,__LC_CPU_TIMER_SAVE_AREA
911 mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
912 TSTMSK __LC_MCCK_CODE,MCCK_CODE_CPU_TIMER_VALID
913 jo 3f
914 la %r14,__LC_SYNC_ENTER_TIMER
915 clc 0(8,%r14),__LC_ASYNC_ENTER_TIMER
916 jl 0f
917 la %r14,__LC_ASYNC_ENTER_TIMER
918 0: clc 0(8,%r14),__LC_EXIT_TIMER
919 jl 1f
920 la %r14,__LC_EXIT_TIMER
921 1: clc 0(8,%r14),__LC_LAST_UPDATE_TIMER
922 jl 2f
923 la %r14,__LC_LAST_UPDATE_TIMER
924 2: spt 0(%r14)
925 mvc __LC_MCCK_ENTER_TIMER(8),0(%r14)
926 3: TSTMSK __LC_MCCK_CODE,(MCCK_CODE_PSW_MWP_VALID|MCCK_CODE_PSW_IA_VALID)
927 jno .Lmcck_panic # no -> skip cleanup critical
928 SWITCH_ASYNC __LC_GPREGS_SAVE_AREA+64,__LC_MCCK_ENTER_TIMER
929 .Lmcck_skip:
930 lghi %r14,__LC_GPREGS_SAVE_AREA+64
931 stmg %r0,%r7,__PT_R0(%r11)
932 mvc __PT_R8(64,%r11),0(%r14)
933 stmg %r8,%r9,__PT_PSW(%r11)
934 xc __PT_FLAGS(8,%r11),__PT_FLAGS(%r11)
935 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
936 lgr %r2,%r11 # pass pointer to pt_regs
937 brasl %r14,s390_do_machine_check
938 tm __PT_PSW+1(%r11),0x01 # returning to user ?
939 jno .Lmcck_return
940 lg %r1,__LC_KERNEL_STACK # switch to kernel stack
941 mvc STACK_FRAME_OVERHEAD(__PT_SIZE,%r1),0(%r11)
942 xc __SF_BACKCHAIN(8,%r1),__SF_BACKCHAIN(%r1)
943 la %r11,STACK_FRAME_OVERHEAD(%r1)
944 lgr %r15,%r1
945 ssm __LC_PGM_NEW_PSW # turn dat on, keep irqs off
946 TSTMSK __LC_CPU_FLAGS,_CIF_MCCK_PENDING
947 jno .Lmcck_return
948 TRACE_IRQS_OFF
949 brasl %r14,s390_handle_mcck
950 TRACE_IRQS_ON
951 .Lmcck_return:
952 lg %r14,__LC_VDSO_PER_CPU
953 lmg %r0,%r10,__PT_R0(%r11)
954 mvc __LC_RETURN_MCCK_PSW(16),__PT_PSW(%r11) # move return PSW
955 tm __LC_RETURN_MCCK_PSW+1,0x01 # returning to user ?
956 jno 0f
957 stpt __LC_EXIT_TIMER
958 mvc __VDSO_ECTG_BASE(16,%r14),__LC_EXIT_TIMER
959 0: lmg %r11,%r15,__PT_R11(%r11)
960 lpswe __LC_RETURN_MCCK_PSW
961
962 .Lmcck_panic:
963 lg %r15,__LC_PANIC_STACK
964 la %r11,STACK_FRAME_OVERHEAD(%r15)
965 j .Lmcck_skip
966
967 #
968 # PSW restart interrupt handler
969 #
970 ENTRY(restart_int_handler)
971 TSTMSK __LC_MACHINE_FLAGS,MACHINE_FLAG_LPP
972 jz 0f
973 .insn s,0xb2800000,__LC_LPP
974 0: stg %r15,__LC_SAVE_AREA_RESTART
975 lg %r15,__LC_RESTART_STACK
976 aghi %r15,-__PT_SIZE # create pt_regs on stack
977 xc 0(__PT_SIZE,%r15),0(%r15)
978 stmg %r0,%r14,__PT_R0(%r15)
979 mvc __PT_R15(8,%r15),__LC_SAVE_AREA_RESTART
980 mvc __PT_PSW(16,%r15),__LC_RST_OLD_PSW # store restart old psw
981 aghi %r15,-STACK_FRAME_OVERHEAD # create stack frame on stack
982 xc 0(STACK_FRAME_OVERHEAD,%r15),0(%r15)
983 lg %r1,__LC_RESTART_FN # load fn, parm & source cpu
984 lg %r2,__LC_RESTART_DATA
985 lg %r3,__LC_RESTART_SOURCE
986 ltgr %r3,%r3 # test source cpu address
987 jm 1f # negative -> skip source stop
988 0: sigp %r4,%r3,SIGP_SENSE # sigp sense to source cpu
989 brc 10,0b # wait for status stored
990 1: basr %r14,%r1 # call function
991 stap __SF_EMPTY(%r15) # store cpu address
992 llgh %r3,__SF_EMPTY(%r15)
993 2: sigp %r4,%r3,SIGP_STOP # sigp stop to current cpu
994 brc 2,2b
995 3: j 3b
996
997 .section .kprobes.text, "ax"
998
999 #ifdef CONFIG_CHECK_STACK
1000 /*
1001 * The synchronous or the asynchronous stack overflowed. We are dead.
1002 * No need to properly save the registers, we are going to panic anyway.
1003 * Setup a pt_regs so that show_trace can provide a good call trace.
1004 */
1005 stack_overflow:
1006 lg %r15,__LC_PANIC_STACK # change to panic stack
1007 la %r11,STACK_FRAME_OVERHEAD(%r15)
1008 stmg %r0,%r7,__PT_R0(%r11)
1009 stmg %r8,%r9,__PT_PSW(%r11)
1010 mvc __PT_R8(64,%r11),0(%r14)
1011 stg %r10,__PT_ORIG_GPR2(%r11) # store last break to orig_gpr2
1012 xc __SF_BACKCHAIN(8,%r15),__SF_BACKCHAIN(%r15)
1013 lgr %r2,%r11 # pass pointer to pt_regs
1014 jg kernel_stack_overflow
1015 #endif
1016
1017 cleanup_critical:
1018 #if IS_ENABLED(CONFIG_KVM)
1019 clg %r9,BASED(.Lcleanup_table_sie) # .Lsie_gmap
1020 jl 0f
1021 clg %r9,BASED(.Lcleanup_table_sie+8)# .Lsie_done
1022 jl .Lcleanup_sie
1023 #endif
1024 clg %r9,BASED(.Lcleanup_table) # system_call
1025 jl 0f
1026 clg %r9,BASED(.Lcleanup_table+8) # .Lsysc_do_svc
1027 jl .Lcleanup_system_call
1028 clg %r9,BASED(.Lcleanup_table+16) # .Lsysc_tif
1029 jl 0f
1030 clg %r9,BASED(.Lcleanup_table+24) # .Lsysc_restore
1031 jl .Lcleanup_sysc_tif
1032 clg %r9,BASED(.Lcleanup_table+32) # .Lsysc_done
1033 jl .Lcleanup_sysc_restore
1034 clg %r9,BASED(.Lcleanup_table+40) # .Lio_tif
1035 jl 0f
1036 clg %r9,BASED(.Lcleanup_table+48) # .Lio_restore
1037 jl .Lcleanup_io_tif
1038 clg %r9,BASED(.Lcleanup_table+56) # .Lio_done
1039 jl .Lcleanup_io_restore
1040 clg %r9,BASED(.Lcleanup_table+64) # psw_idle
1041 jl 0f
1042 clg %r9,BASED(.Lcleanup_table+72) # .Lpsw_idle_end
1043 jl .Lcleanup_idle
1044 clg %r9,BASED(.Lcleanup_table+80) # save_fpu_regs
1045 jl 0f
1046 clg %r9,BASED(.Lcleanup_table+88) # .Lsave_fpu_regs_end
1047 jl .Lcleanup_save_fpu_regs
1048 clg %r9,BASED(.Lcleanup_table+96) # load_fpu_regs
1049 jl 0f
1050 clg %r9,BASED(.Lcleanup_table+104) # .Lload_fpu_regs_end
1051 jl .Lcleanup_load_fpu_regs
1052 0: br %r14
1053
1054 .align 8
1055 .Lcleanup_table:
1056 .quad system_call
1057 .quad .Lsysc_do_svc
1058 .quad .Lsysc_tif
1059 .quad .Lsysc_restore
1060 .quad .Lsysc_done
1061 .quad .Lio_tif
1062 .quad .Lio_restore
1063 .quad .Lio_done
1064 .quad psw_idle
1065 .quad .Lpsw_idle_end
1066 .quad save_fpu_regs
1067 .quad .Lsave_fpu_regs_end
1068 .quad load_fpu_regs
1069 .quad .Lload_fpu_regs_end
1070
1071 #if IS_ENABLED(CONFIG_KVM)
1072 .Lcleanup_table_sie:
1073 .quad .Lsie_gmap
1074 .quad .Lsie_done
1075
1076 .Lcleanup_sie:
1077 lg %r9,__SF_EMPTY(%r15) # get control block pointer
1078 ni __SIE_PROG0C+3(%r9),0xfe # no longer in SIE
1079 lctlg %c1,%c1,__LC_USER_ASCE # load primary asce
1080 larl %r9,sie_exit # skip forward to sie_exit
1081 br %r14
1082 #endif
1083
1084 .Lcleanup_system_call:
1085 # check if stpt has been executed
1086 clg %r9,BASED(.Lcleanup_system_call_insn)
1087 jh 0f
1088 mvc __LC_SYNC_ENTER_TIMER(8),__LC_ASYNC_ENTER_TIMER
1089 cghi %r11,__LC_SAVE_AREA_ASYNC
1090 je 0f
1091 mvc __LC_SYNC_ENTER_TIMER(8),__LC_MCCK_ENTER_TIMER
1092 0: # check if stmg has been executed
1093 clg %r9,BASED(.Lcleanup_system_call_insn+8)
1094 jh 0f
1095 mvc __LC_SAVE_AREA_SYNC(64),0(%r11)
1096 0: # check if base register setup + TIF bit load has been done
1097 clg %r9,BASED(.Lcleanup_system_call_insn+16)
1098 jhe 0f
1099 # set up saved register r12 task struct pointer
1100 stg %r12,32(%r11)
1101 # set up saved register r13 __TASK_thread offset
1102 mvc 40(8,%r11),BASED(.Lcleanup_system_call_const)
1103 0: # check if the user time update has been done
1104 clg %r9,BASED(.Lcleanup_system_call_insn+24)
1105 jh 0f
1106 lg %r15,__LC_EXIT_TIMER
1107 slg %r15,__LC_SYNC_ENTER_TIMER
1108 alg %r15,__LC_USER_TIMER
1109 stg %r15,__LC_USER_TIMER
1110 0: # check if the system time update has been done
1111 clg %r9,BASED(.Lcleanup_system_call_insn+32)
1112 jh 0f
1113 lg %r15,__LC_LAST_UPDATE_TIMER
1114 slg %r15,__LC_EXIT_TIMER
1115 alg %r15,__LC_SYSTEM_TIMER
1116 stg %r15,__LC_SYSTEM_TIMER
1117 0: # update accounting time stamp
1118 mvc __LC_LAST_UPDATE_TIMER(8),__LC_SYNC_ENTER_TIMER
1119 # set up saved register r11
1120 lg %r15,__LC_KERNEL_STACK
1121 la %r9,STACK_FRAME_OVERHEAD(%r15)
1122 stg %r9,24(%r11) # r11 pt_regs pointer
1123 # fill pt_regs
1124 mvc __PT_R8(64,%r9),__LC_SAVE_AREA_SYNC
1125 stmg %r0,%r7,__PT_R0(%r9)
1126 mvc __PT_PSW(16,%r9),__LC_SVC_OLD_PSW
1127 mvc __PT_INT_CODE(4,%r9),__LC_SVC_ILC
1128 xc __PT_FLAGS(8,%r9),__PT_FLAGS(%r9)
1129 mvi __PT_FLAGS+7(%r9),_PIF_SYSCALL
1130 # setup saved register r15
1131 stg %r15,56(%r11) # r15 stack pointer
1132 # set new psw address and exit
1133 larl %r9,.Lsysc_do_svc
1134 br %r14
1135 .Lcleanup_system_call_insn:
1136 .quad system_call
1137 .quad .Lsysc_stmg
1138 .quad .Lsysc_per
1139 .quad .Lsysc_vtime+36
1140 .quad .Lsysc_vtime+42
1141 .Lcleanup_system_call_const:
1142 .quad __TASK_thread
1143
1144 .Lcleanup_sysc_tif:
1145 larl %r9,.Lsysc_tif
1146 br %r14
1147
1148 .Lcleanup_sysc_restore:
1149 clg %r9,BASED(.Lcleanup_sysc_restore_insn)
1150 je 0f
1151 lg %r9,24(%r11) # get saved pointer to pt_regs
1152 mvc __LC_RETURN_PSW(16),__PT_PSW(%r9)
1153 mvc 0(64,%r11),__PT_R8(%r9)
1154 lmg %r0,%r7,__PT_R0(%r9)
1155 0: lmg %r8,%r9,__LC_RETURN_PSW
1156 br %r14
1157 .Lcleanup_sysc_restore_insn:
1158 .quad .Lsysc_done - 4
1159
1160 .Lcleanup_io_tif:
1161 larl %r9,.Lio_tif
1162 br %r14
1163
1164 .Lcleanup_io_restore:
1165 clg %r9,BASED(.Lcleanup_io_restore_insn)
1166 je 0f
1167 lg %r9,24(%r11) # get saved r11 pointer to pt_regs
1168 mvc __LC_RETURN_PSW(16),__PT_PSW(%r9)
1169 mvc 0(64,%r11),__PT_R8(%r9)
1170 lmg %r0,%r7,__PT_R0(%r9)
1171 0: lmg %r8,%r9,__LC_RETURN_PSW
1172 br %r14
1173 .Lcleanup_io_restore_insn:
1174 .quad .Lio_done - 4
1175
1176 .Lcleanup_idle:
1177 ni __LC_CPU_FLAGS+7,255-_CIF_ENABLED_WAIT
1178 # copy interrupt clock & cpu timer
1179 mvc __CLOCK_IDLE_EXIT(8,%r2),__LC_INT_CLOCK
1180 mvc __TIMER_IDLE_EXIT(8,%r2),__LC_ASYNC_ENTER_TIMER
1181 cghi %r11,__LC_SAVE_AREA_ASYNC
1182 je 0f
1183 mvc __CLOCK_IDLE_EXIT(8,%r2),__LC_MCCK_CLOCK
1184 mvc __TIMER_IDLE_EXIT(8,%r2),__LC_MCCK_ENTER_TIMER
1185 0: # check if stck & stpt have been executed
1186 clg %r9,BASED(.Lcleanup_idle_insn)
1187 jhe 1f
1188 mvc __CLOCK_IDLE_ENTER(8,%r2),__CLOCK_IDLE_EXIT(%r2)
1189 mvc __TIMER_IDLE_ENTER(8,%r2),__TIMER_IDLE_EXIT(%r2)
1190 1: # calculate idle cycles
1191 #ifdef CONFIG_SMP
1192 clg %r9,BASED(.Lcleanup_idle_insn)
1193 jl 3f
1194 larl %r1,smp_cpu_mtid
1195 llgf %r1,0(%r1)
1196 ltgr %r1,%r1
1197 jz 3f
1198 .insn rsy,0xeb0000000017,%r1,5,__SF_EMPTY+80(%r15)
1199 larl %r3,mt_cycles
1200 ag %r3,__LC_PERCPU_OFFSET
1201 la %r4,__SF_EMPTY+16(%r15)
1202 2: lg %r0,0(%r3)
1203 slg %r0,0(%r4)
1204 alg %r0,64(%r4)
1205 stg %r0,0(%r3)
1206 la %r3,8(%r3)
1207 la %r4,8(%r4)
1208 brct %r1,2b
1209 #endif
1210 3: # account system time going idle
1211 lg %r9,__LC_STEAL_TIMER
1212 alg %r9,__CLOCK_IDLE_ENTER(%r2)
1213 slg %r9,__LC_LAST_UPDATE_CLOCK
1214 stg %r9,__LC_STEAL_TIMER
1215 mvc __LC_LAST_UPDATE_CLOCK(8),__CLOCK_IDLE_EXIT(%r2)
1216 lg %r9,__LC_SYSTEM_TIMER
1217 alg %r9,__LC_LAST_UPDATE_TIMER
1218 slg %r9,__TIMER_IDLE_ENTER(%r2)
1219 stg %r9,__LC_SYSTEM_TIMER
1220 mvc __LC_LAST_UPDATE_TIMER(8),__TIMER_IDLE_EXIT(%r2)
1221 # prepare return psw
1222 nihh %r8,0xfcfd # clear irq & wait state bits
1223 lg %r9,48(%r11) # return from psw_idle
1224 br %r14
1225 .Lcleanup_idle_insn:
1226 .quad .Lpsw_idle_lpsw
1227
1228 .Lcleanup_save_fpu_regs:
1229 larl %r9,save_fpu_regs
1230 br %r14
1231
1232 .Lcleanup_load_fpu_regs:
1233 larl %r9,load_fpu_regs
1234 br %r14
1235
1236 /*
1237 * Integer constants
1238 */
1239 .align 8
1240 .Lcritical_start:
1241 .quad .L__critical_start
1242 .Lcritical_length:
1243 .quad .L__critical_end - .L__critical_start
1244 #if IS_ENABLED(CONFIG_KVM)
1245 .Lsie_critical_start:
1246 .quad .Lsie_gmap
1247 .Lsie_critical_length:
1248 .quad .Lsie_done - .Lsie_gmap
1249 #endif
1250
1251 .section .rodata, "a"
1252 #define SYSCALL(esame,emu) .long esame
1253 .globl sys_call_table
1254 sys_call_table:
1255 #include "syscalls.S"
1256 #undef SYSCALL
1257
1258 #ifdef CONFIG_COMPAT
1259
1260 #define SYSCALL(esame,emu) .long emu
1261 .globl sys_call_table_emu
1262 sys_call_table_emu:
1263 #include "syscalls.S"
1264 #undef SYSCALL
1265 #endif
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