arch/s390/pci/pci_irq.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 #define KMSG_COMPONENT "zpci"
   3 #define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
   4
   5 #include <linux/kernel.h>
   6 #include <linux/irq.h>
   7 #include <linux/kernel_stat.h>
   8 #include <linux/pci.h>
   9 #include <linux/msi.h>
  10 #include <linux/smp.h>
  11
  12 #include <asm/isc.h>
  13 #include <asm/airq.h>
  14
  15 static enum {FLOATING, DIRECTED} irq_delivery;
  16
  17 #define SIC_IRQ_MODE_ALL                0
  18 #define SIC_IRQ_MODE_SINGLE             1
  19 #define SIC_IRQ_MODE_DIRECT             4
  20 #define SIC_IRQ_MODE_D_ALL              16
  21 #define SIC_IRQ_MODE_D_SINGLE           17
  22 #define SIC_IRQ_MODE_SET_CPU            18
  23
  24 /*
  25  * summary bit vector
  26  * FLOATING - summary bit per function
  27  * DIRECTED - summary bit per cpu (only used in fallback path)
  28  */
  29 static struct airq_iv *zpci_sbv;
  30
  31 /*
  32  * interrupt bit vectors
  33  * FLOATING - interrupt bit vector per function
  34  * DIRECTED - interrupt bit vector per cpu
  35  */
  36 static struct airq_iv **zpci_ibv;
  37
  38 /* Modify PCI: Register adapter interruptions */
  39 static int zpci_set_airq(struct zpci_dev *zdev)
  40 {
  41         u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_REG_INT);
  42         struct zpci_fib fib = {0};
  43         u8 status;
  44
  45         fib.fmt0.isc = PCI_ISC;
  46         fib.fmt0.sum = 1;       /* enable summary notifications */
  47         fib.fmt0.noi = airq_iv_end(zdev->aibv);
  48         fib.fmt0.aibv = (unsigned long) zdev->aibv->vector;
  49         fib.fmt0.aibvo = 0;     /* each zdev has its own interrupt vector */
  50         fib.fmt0.aisb = (unsigned long) zpci_sbv->vector + (zdev->aisb/64)*8;
  51         fib.fmt0.aisbo = zdev->aisb & 63;
  52
  53         return zpci_mod_fc(req, &fib, &status) ? -EIO : 0;
  54 }
  55
  56 /* Modify PCI: Unregister adapter interruptions */
  57 static int zpci_clear_airq(struct zpci_dev *zdev)
  58 {
  59         u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_DEREG_INT);
  60         struct zpci_fib fib = {0};
  61         u8 cc, status;
  62
  63         cc = zpci_mod_fc(req, &fib, &status);
  64         if (cc == 3 || (cc == 1 && status == 24))
  65                 /* Function already gone or IRQs already deregistered. */
  66                 cc = 0;
  67
  68         return cc ? -EIO : 0;
  69 }
  70
  71 /* Modify PCI: Register CPU directed interruptions */
  72 static int zpci_set_directed_irq(struct zpci_dev *zdev)
  73 {
  74         u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_REG_INT_D);
  75         struct zpci_fib fib = {0};
  76         u8 status;
  77
  78         fib.fmt = 1;
  79         fib.fmt1.noi = zdev->msi_nr_irqs;
  80         fib.fmt1.dibvo = zdev->msi_first_bit;
  81
  82         return zpci_mod_fc(req, &fib, &status) ? -EIO : 0;
  83 }
  84
  85 /* Modify PCI: Unregister CPU directed interruptions */
  86 static int zpci_clear_directed_irq(struct zpci_dev *zdev)
  87 {
  88         u64 req = ZPCI_CREATE_REQ(zdev->fh, 0, ZPCI_MOD_FC_DEREG_INT_D);
  89         struct zpci_fib fib = {0};
  90         u8 cc, status;
  91
  92         fib.fmt = 1;
  93         cc = zpci_mod_fc(req, &fib, &status);
  94         if (cc == 3 || (cc == 1 && status == 24))
  95                 /* Function already gone or IRQs already deregistered. */
  96                 cc = 0;
  97
  98         return cc ? -EIO : 0;
  99 }
 100
 101 static int zpci_set_irq_affinity(struct irq_data *data, const struct cpumask *dest,
 102                                  bool force)
 103 {
 104         struct msi_desc *entry = irq_get_msi_desc(data->irq);
 105         struct msi_msg msg = entry->msg;
 106
 107         msg.address_lo &= 0xff0000ff;
 108         msg.address_lo |= (cpumask_first(dest) << 8);
 109         pci_write_msi_msg(data->irq, &msg);
 110
 111         return IRQ_SET_MASK_OK;
 112 }
 113
 114 static struct irq_chip zpci_irq_chip = {
 115         .name = "PCI-MSI",
 116         .irq_unmask = pci_msi_unmask_irq,
 117         .irq_mask = pci_msi_mask_irq,
 118         .irq_set_affinity = zpci_set_irq_affinity,
 119 };
 120
 121 static void zpci_handle_cpu_local_irq(bool rescan)
 122 {
 123         struct airq_iv *dibv = zpci_ibv[smp_processor_id()];
 124         unsigned long bit;
 125         int irqs_on = 0;
 126
 127         for (bit = 0;;) {
 128                 /* Scan the directed IRQ bit vector */
 129                 bit = airq_iv_scan(dibv, bit, airq_iv_end(dibv));
 130                 if (bit == -1UL) {
 131                         if (!rescan || irqs_on++)
 132                                 /* End of second scan with interrupts on. */
 133                                 break;
 134                         /* First scan complete, reenable interrupts. */
 135                         if (zpci_set_irq_ctrl(SIC_IRQ_MODE_D_SINGLE, PCI_ISC))
 136                                 break;
 137                         bit = 0;
 138                         continue;
 139                 }
 140                 inc_irq_stat(IRQIO_MSI);
 141                 generic_handle_irq(airq_iv_get_data(dibv, bit));
 142         }
 143 }
 144
 145 struct cpu_irq_data {
 146         call_single_data_t csd;
 147         atomic_t scheduled;
 148 };
 149 static DEFINE_PER_CPU_SHARED_ALIGNED(struct cpu_irq_data, irq_data);
 150
 151 static void zpci_handle_remote_irq(void *data)
 152 {
 153         atomic_t *scheduled = data;
 154
 155         do {
 156                 zpci_handle_cpu_local_irq(false);
 157         } while (atomic_dec_return(scheduled));
 158 }
 159
 160 static void zpci_handle_fallback_irq(void)
 161 {
 162         struct cpu_irq_data *cpu_data;
 163         unsigned long cpu;
 164         int irqs_on = 0;
 165
 166         for (cpu = 0;;) {
 167                 cpu = airq_iv_scan(zpci_sbv, cpu, airq_iv_end(zpci_sbv));
 168                 if (cpu == -1UL) {
 169                         if (irqs_on++)
 170                                 /* End of second scan with interrupts on. */
 171                                 break;
 172                         /* First scan complete, reenable interrupts. */
 173                         if (zpci_set_irq_ctrl(SIC_IRQ_MODE_SINGLE, PCI_ISC))
 174                                 break;
 175                         cpu = 0;
 176                         continue;
 177                 }
 178                 cpu_data = &per_cpu(irq_data, cpu);
 179                 if (atomic_inc_return(&cpu_data->scheduled) > 1)
 180                         continue;
 181
 182                 cpu_data->csd.func = zpci_handle_remote_irq;
 183                 cpu_data->csd.info = &cpu_data->scheduled;
 184                 cpu_data->csd.flags = 0;
 185                 smp_call_function_single_async(cpu, &cpu_data->csd);
 186         }
 187 }
 188
 189 static void zpci_directed_irq_handler(struct airq_struct *airq, bool floating)
 190 {
 191         if (floating) {
 192                 inc_irq_stat(IRQIO_PCF);
 193                 zpci_handle_fallback_irq();
 194         } else {
 195                 inc_irq_stat(IRQIO_PCD);
 196                 zpci_handle_cpu_local_irq(true);
 197         }
 198 }
 199
 200 static void zpci_floating_irq_handler(struct airq_struct *airq, bool floating)
 201 {
 202         unsigned long si, ai;
 203         struct airq_iv *aibv;
 204         int irqs_on = 0;
 205
 206         inc_irq_stat(IRQIO_PCF);
 207         for (si = 0;;) {
 208                 /* Scan adapter summary indicator bit vector */
 209                 si = airq_iv_scan(zpci_sbv, si, airq_iv_end(zpci_sbv));
 210                 if (si == -1UL) {
 211                         if (irqs_on++)
 212                                 /* End of second scan with interrupts on. */
 213                                 break;
 214                         /* First scan complete, reenable interrupts. */
 215                         if (zpci_set_irq_ctrl(SIC_IRQ_MODE_SINGLE, PCI_ISC))
 216                                 break;
 217                         si = 0;
 218                         continue;
 219                 }
 220
 221                 /* Scan the adapter interrupt vector for this device. */
 222                 aibv = zpci_ibv[si];
 223                 for (ai = 0;;) {
 224                         ai = airq_iv_scan(aibv, ai, airq_iv_end(aibv));
 225                         if (ai == -1UL)
 226                                 break;
 227                         inc_irq_stat(IRQIO_MSI);
 228                         airq_iv_lock(aibv, ai);
 229                         generic_handle_irq(airq_iv_get_data(aibv, ai));
 230                         airq_iv_unlock(aibv, ai);
 231                 }
 232         }
 233 }
 234
 235 int arch_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
 236 {
 237         struct zpci_dev *zdev = to_zpci(pdev);
 238         unsigned int hwirq, msi_vecs, cpu;
 239         unsigned long bit;
 240         struct msi_desc *msi;
 241         struct msi_msg msg;
 242         int rc, irq;
 243
 244         zdev->aisb = -1UL;
 245         zdev->msi_first_bit = -1U;
 246         if (type == PCI_CAP_ID_MSI && nvec > 1)
 247                 return 1;
 248         msi_vecs = min_t(unsigned int, nvec, zdev->max_msi);
 249
 250         if (irq_delivery == DIRECTED) {
 251                 /* Allocate cpu vector bits */
 252                 bit = airq_iv_alloc(zpci_ibv[0], msi_vecs);
 253                 if (bit == -1UL)
 254                         return -EIO;
 255         } else {
 256                 /* Allocate adapter summary indicator bit */
 257                 bit = airq_iv_alloc_bit(zpci_sbv);
 258                 if (bit == -1UL)
 259                         return -EIO;
 260                 zdev->aisb = bit;
 261
 262                 /* Create adapter interrupt vector */
 263                 zdev->aibv = airq_iv_create(msi_vecs, AIRQ_IV_DATA | AIRQ_IV_BITLOCK);
 264                 if (!zdev->aibv)
 265                         return -ENOMEM;
 266
 267                 /* Wire up shortcut pointer */
 268                 zpci_ibv[bit] = zdev->aibv;
 269                 /* Each function has its own interrupt vector */
 270                 bit = 0;
 271         }
 272
 273         /* Request MSI interrupts */
 274         hwirq = bit;
 275         for_each_pci_msi_entry(msi, pdev) {
 276                 rc = -EIO;
 277                 if (hwirq - bit >= msi_vecs)
 278                         break;
 279                 irq = __irq_alloc_descs(-1, 0, 1, 0, THIS_MODULE, msi->affinity);
 280                 if (irq < 0)
 281                         return -ENOMEM;
 282                 rc = irq_set_msi_desc(irq, msi);
 283                 if (rc)
 284                         return rc;
 285                 irq_set_chip_and_handler(irq, &zpci_irq_chip,
 286                                          handle_percpu_irq);
 287                 msg.data = hwirq;
 288                 if (irq_delivery == DIRECTED) {
 289                         msg.address_lo = zdev->msi_addr & 0xff0000ff;
 290                         msg.address_lo |= msi->affinity ?
 291                                 (cpumask_first(&msi->affinity->mask) << 8) : 0;
 292                         for_each_possible_cpu(cpu) {
 293                                 airq_iv_set_data(zpci_ibv[cpu], hwirq, irq);
 294                         }
 295                 } else {
 296                         msg.address_lo = zdev->msi_addr & 0xffffffff;
 297                         airq_iv_set_data(zdev->aibv, hwirq, irq);
 298                 }
 299                 msg.address_hi = zdev->msi_addr >> 32;
 300                 pci_write_msi_msg(irq, &msg);
 301                 hwirq++;
 302         }
 303
 304         zdev->msi_first_bit = bit;
 305         zdev->msi_nr_irqs = msi_vecs;
 306
 307         if (irq_delivery == DIRECTED)
 308                 rc = zpci_set_directed_irq(zdev);
 309         else
 310                 rc = zpci_set_airq(zdev);
 311         if (rc)
 312                 return rc;
 313
 314         return (msi_vecs == nvec) ? 0 : msi_vecs;
 315 }
 316
 317 void arch_teardown_msi_irqs(struct pci_dev *pdev)
 318 {
 319         struct zpci_dev *zdev = to_zpci(pdev);
 320         struct msi_desc *msi;
 321         int rc;
 322
 323         /* Disable interrupts */
 324         if (irq_delivery == DIRECTED)
 325                 rc = zpci_clear_directed_irq(zdev);
 326         else
 327                 rc = zpci_clear_airq(zdev);
 328         if (rc)
 329                 return;
 330
 331         /* Release MSI interrupts */
 332         for_each_pci_msi_entry(msi, pdev) {
 333                 if (!msi->irq)
 334                         continue;
 335                 if (msi->msi_attrib.is_msix)
 336                         __pci_msix_desc_mask_irq(msi, 1);
 337                 else
 338                         __pci_msi_desc_mask_irq(msi, 1, 1);
 339                 irq_set_msi_desc(msi->irq, NULL);
 340                 irq_free_desc(msi->irq);
 341                 msi->msg.address_lo = 0;
 342                 msi->msg.address_hi = 0;
 343                 msi->msg.data = 0;
 344                 msi->irq = 0;
 345         }
 346
 347         if (zdev->aisb != -1UL) {
 348                 zpci_ibv[zdev->aisb] = NULL;
 349                 airq_iv_free_bit(zpci_sbv, zdev->aisb);
 350                 zdev->aisb = -1UL;
 351         }
 352         if (zdev->aibv) {
 353                 airq_iv_release(zdev->aibv);
 354                 zdev->aibv = NULL;
 355         }
 356
 357         if ((irq_delivery == DIRECTED) && zdev->msi_first_bit != -1U)
 358                 airq_iv_free(zpci_ibv[0], zdev->msi_first_bit, zdev->msi_nr_irqs);
 359 }
 360
 361 static struct airq_struct zpci_airq = {
 362         .handler = zpci_floating_irq_handler,
 363         .isc = PCI_ISC,
 364 };
 365
 366 static void __init cpu_enable_directed_irq(void *unused)
 367 {
 368         union zpci_sic_iib iib = {{0}};
 369
 370         iib.cdiib.dibv_addr = (u64) zpci_ibv[smp_processor_id()]->vector;
 371
 372         __zpci_set_irq_ctrl(SIC_IRQ_MODE_SET_CPU, 0, &iib);
 373         zpci_set_irq_ctrl(SIC_IRQ_MODE_D_SINGLE, PCI_ISC);
 374 }
 375
 376 static int __init zpci_directed_irq_init(void)
 377 {
 378         union zpci_sic_iib iib = {{0}};
 379         unsigned int cpu;
 380
 381         zpci_sbv = airq_iv_create(num_possible_cpus(), 0);
 382         if (!zpci_sbv)
 383                 return -ENOMEM;
 384
 385         iib.diib.isc = PCI_ISC;
 386         iib.diib.nr_cpus = num_possible_cpus();
 387         iib.diib.disb_addr = (u64) zpci_sbv->vector;
 388         __zpci_set_irq_ctrl(SIC_IRQ_MODE_DIRECT, 0, &iib);
 389
 390         zpci_ibv = kcalloc(num_possible_cpus(), sizeof(*zpci_ibv),
 391                            GFP_KERNEL);
 392         if (!zpci_ibv)
 393                 return -ENOMEM;
 394
 395         for_each_possible_cpu(cpu) {
 396                 /*
 397                  * Per CPU IRQ vectors look the same but bit-allocation
 398                  * is only done on the first vector.
 399                  */
 400                 zpci_ibv[cpu] = airq_iv_create(cache_line_size() * BITS_PER_BYTE,
 401                                                AIRQ_IV_DATA |
 402                                                AIRQ_IV_CACHELINE |
 403                                                (!cpu ? AIRQ_IV_ALLOC : 0));
 404                 if (!zpci_ibv[cpu])
 405                         return -ENOMEM;
 406         }
 407         on_each_cpu(cpu_enable_directed_irq, NULL, 1);
 408
 409         zpci_irq_chip.irq_set_affinity = zpci_set_irq_affinity;
 410
 411         return 0;
 412 }
 413
 414 static int __init zpci_floating_irq_init(void)
 415 {
 416         zpci_ibv = kcalloc(ZPCI_NR_DEVICES, sizeof(*zpci_ibv), GFP_KERNEL);
 417         if (!zpci_ibv)
 418                 return -ENOMEM;
 419
 420         zpci_sbv = airq_iv_create(ZPCI_NR_DEVICES, AIRQ_IV_ALLOC);
 421         if (!zpci_sbv)
 422                 goto out_free;
 423
 424         return 0;
 425
 426 out_free:
 427         kfree(zpci_ibv);
 428         return -ENOMEM;
 429 }
 430
 431 int __init zpci_irq_init(void)
 432 {
 433         int rc;
 434
 435         irq_delivery = sclp.has_dirq ? DIRECTED : FLOATING;
 436         if (s390_pci_force_floating)
 437                 irq_delivery = FLOATING;
 438
 439         if (irq_delivery == DIRECTED)
 440                 zpci_airq.handler = zpci_directed_irq_handler;
 441
 442         rc = register_adapter_interrupt(&zpci_airq);
 443         if (rc)
 444                 goto out;
 445         /* Set summary to 1 to be called every time for the ISC. */
 446         *zpci_airq.lsi_ptr = 1;
 447
 448         switch (irq_delivery) {
 449         case FLOATING:
 450                 rc = zpci_floating_irq_init();
 451                 break;
 452         case DIRECTED:
 453                 rc = zpci_directed_irq_init();
 454                 break;
 455         }
 456
 457         if (rc)
 458                 goto out_airq;
 459
 460         /*
 461          * Enable floating IRQs (with suppression after one IRQ). When using
 462          * directed IRQs this enables the fallback path.
 463          */
 464         zpci_set_irq_ctrl(SIC_IRQ_MODE_SINGLE, PCI_ISC);
 465
 466         return 0;
 467 out_airq:
 468         unregister_adapter_interrupt(&zpci_airq);
 469 out:
 470         return rc;
 471 }
 472
 473 void __init zpci_irq_exit(void)
 474 {
 475         unsigned int cpu;
 476
 477         if (irq_delivery == DIRECTED) {
 478                 for_each_possible_cpu(cpu) {
 479                         airq_iv_release(zpci_ibv[cpu]);
 480                 }
 481         }
 482         kfree(zpci_ibv);
 483         if (zpci_sbv)
 484                 airq_iv_release(zpci_sbv);
 485         unregister_adapter_interrupt(&zpci_airq);
 486 }