arch/sh/boards/board-sh7757lcr.c

   1 /*
   2  * Renesas R0P7757LC0012RL Support.
   3  *
   4  * Copyright (C) 2009 - 2010  Renesas Solutions Corp.
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10
  11 #include <linux/init.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/gpio.h>
  14 #include <linux/irq.h>
  15 #include <linux/regulator/fixed.h>
  16 #include <linux/regulator/machine.h>
  17 #include <linux/spi/spi.h>
  18 #include <linux/spi/flash.h>
  19 #include <linux/io.h>
  20 #include <linux/mmc/host.h>
  21 #include <linux/mmc/sh_mmcif.h>
  22 #include <linux/mmc/sh_mobile_sdhi.h>
  23 #include <linux/sh_eth.h>
  24 #include <linux/sh_intc.h>
  25 #include <linux/usb/renesas_usbhs.h>
  26 #include <cpu/sh7757.h>
  27 #include <asm/heartbeat.h>
  28
  29 static struct resource heartbeat_resource = {
  30         .start  = 0xffec005c,   /* PUDR */
  31         .end    = 0xffec005c,
  32         .flags  = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
  33 };
  34
  35 static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 };
  36
  37 static struct heartbeat_data heartbeat_data = {
  38         .bit_pos        = heartbeat_bit_pos,
  39         .nr_bits        = ARRAY_SIZE(heartbeat_bit_pos),
  40         .flags          = HEARTBEAT_INVERTED,
  41 };
  42
  43 static struct platform_device heartbeat_device = {
  44         .name           = "heartbeat",
  45         .id             = -1,
  46         .dev    = {
  47                 .platform_data  = &heartbeat_data,
  48         },
  49         .num_resources  = 1,
  50         .resource       = &heartbeat_resource,
  51 };
  52
  53 /* Fast Ethernet */
  54 #define GBECONT         0xffc10100
  55 #define GBECONT_RMII1   BIT(17)
  56 #define GBECONT_RMII0   BIT(16)
  57 static void sh7757_eth_set_mdio_gate(void *addr)
  58 {
  59         if (((unsigned long)addr & 0x00000fff) < 0x0800)
  60                 writel(readl(GBECONT) | GBECONT_RMII0, GBECONT);
  61         else
  62                 writel(readl(GBECONT) | GBECONT_RMII1, GBECONT);
  63 }
  64
  65 static struct resource sh_eth0_resources[] = {
  66         {
  67                 .start  = 0xfef00000,
  68                 .end    = 0xfef001ff,
  69                 .flags  = IORESOURCE_MEM,
  70         }, {
  71                 .start  = evt2irq(0xc80),
  72                 .end    = evt2irq(0xc80),
  73                 .flags  = IORESOURCE_IRQ,
  74         },
  75 };
  76
  77 static struct sh_eth_plat_data sh7757_eth0_pdata = {
  78         .phy = 1,
  79         .edmac_endian = EDMAC_LITTLE_ENDIAN,
  80         .register_type = SH_ETH_REG_FAST_SH4,
  81         .set_mdio_gate = sh7757_eth_set_mdio_gate,
  82 };
  83
  84 static struct platform_device sh7757_eth0_device = {
  85         .name           = "sh-eth",
  86         .resource       = sh_eth0_resources,
  87         .id             = 0,
  88         .num_resources  = ARRAY_SIZE(sh_eth0_resources),
  89         .dev            = {
  90                 .platform_data = &sh7757_eth0_pdata,
  91         },
  92 };
  93
  94 static struct resource sh_eth1_resources[] = {
  95         {
  96                 .start  = 0xfef00800,
  97                 .end    = 0xfef009ff,
  98                 .flags  = IORESOURCE_MEM,
  99         }, {
 100                 .start  = evt2irq(0xc80),
 101                 .end    = evt2irq(0xc80),
 102                 .flags  = IORESOURCE_IRQ,
 103         },
 104 };
 105
 106 static struct sh_eth_plat_data sh7757_eth1_pdata = {
 107         .phy = 1,
 108         .edmac_endian = EDMAC_LITTLE_ENDIAN,
 109         .register_type = SH_ETH_REG_FAST_SH4,
 110         .set_mdio_gate = sh7757_eth_set_mdio_gate,
 111 };
 112
 113 static struct platform_device sh7757_eth1_device = {
 114         .name           = "sh-eth",
 115         .resource       = sh_eth1_resources,
 116         .id             = 1,
 117         .num_resources  = ARRAY_SIZE(sh_eth1_resources),
 118         .dev            = {
 119                 .platform_data = &sh7757_eth1_pdata,
 120         },
 121 };
 122
 123 static void sh7757_eth_giga_set_mdio_gate(void *addr)
 124 {
 125         if (((unsigned long)addr & 0x00000fff) < 0x0800) {
 126                 gpio_set_value(GPIO_PTT4, 1);
 127                 writel(readl(GBECONT) & ~GBECONT_RMII0, GBECONT);
 128         } else {
 129                 gpio_set_value(GPIO_PTT4, 0);
 130                 writel(readl(GBECONT) & ~GBECONT_RMII1, GBECONT);
 131         }
 132 }
 133
 134 static struct resource sh_eth_giga0_resources[] = {
 135         {
 136                 .start  = 0xfee00000,
 137                 .end    = 0xfee007ff,
 138                 .flags  = IORESOURCE_MEM,
 139         }, {
 140                 /* TSU */
 141                 .start  = 0xfee01800,
 142                 .end    = 0xfee01fff,
 143                 .flags  = IORESOURCE_MEM,
 144         }, {
 145                 .start  = evt2irq(0x2960),
 146                 .end    = evt2irq(0x2960),
 147                 .flags  = IORESOURCE_IRQ,
 148         },
 149 };
 150
 151 static struct sh_eth_plat_data sh7757_eth_giga0_pdata = {
 152         .phy = 18,
 153         .edmac_endian = EDMAC_LITTLE_ENDIAN,
 154         .register_type = SH_ETH_REG_GIGABIT,
 155         .set_mdio_gate = sh7757_eth_giga_set_mdio_gate,
 156         .phy_interface = PHY_INTERFACE_MODE_RGMII_ID,
 157 };
 158
 159 static struct platform_device sh7757_eth_giga0_device = {
 160         .name           = "sh-eth",
 161         .resource       = sh_eth_giga0_resources,
 162         .id             = 2,
 163         .num_resources  = ARRAY_SIZE(sh_eth_giga0_resources),
 164         .dev            = {
 165                 .platform_data = &sh7757_eth_giga0_pdata,
 166         },
 167 };
 168
 169 static struct resource sh_eth_giga1_resources[] = {
 170         {
 171                 .start  = 0xfee00800,
 172                 .end    = 0xfee00fff,
 173                 .flags  = IORESOURCE_MEM,
 174         }, {
 175                 /* TSU */
 176                 .start  = 0xfee01800,
 177                 .end    = 0xfee01fff,
 178                 .flags  = IORESOURCE_MEM,
 179         }, {
 180                 .start  = evt2irq(0x2980),
 181                 .end    = evt2irq(0x2980),
 182                 .flags  = IORESOURCE_IRQ,
 183         },
 184 };
 185
 186 static struct sh_eth_plat_data sh7757_eth_giga1_pdata = {
 187         .phy = 19,
 188         .edmac_endian = EDMAC_LITTLE_ENDIAN,
 189         .register_type = SH_ETH_REG_GIGABIT,
 190         .set_mdio_gate = sh7757_eth_giga_set_mdio_gate,
 191         .phy_interface = PHY_INTERFACE_MODE_RGMII_ID,
 192 };
 193
 194 static struct platform_device sh7757_eth_giga1_device = {
 195         .name           = "sh-eth",
 196         .resource       = sh_eth_giga1_resources,
 197         .id             = 3,
 198         .num_resources  = ARRAY_SIZE(sh_eth_giga1_resources),
 199         .dev            = {
 200                 .platform_data = &sh7757_eth_giga1_pdata,
 201         },
 202 };
 203
 204 /* Fixed 3.3V regulator to be used by SDHI0, MMCIF */
 205 static struct regulator_consumer_supply fixed3v3_power_consumers[] =
 206 {
 207         REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
 208         REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
 209         REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
 210         REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
 211 };
 212
 213 /* SH_MMCIF */
 214 static struct resource sh_mmcif_resources[] = {
 215         [0] = {
 216                 .start  = 0xffcb0000,
 217                 .end    = 0xffcb00ff,
 218                 .flags  = IORESOURCE_MEM,
 219         },
 220         [1] = {
 221                 .start  = evt2irq(0x1c60),
 222                 .flags  = IORESOURCE_IRQ,
 223         },
 224         [2] = {
 225                 .start  = evt2irq(0x1c80),
 226                 .flags  = IORESOURCE_IRQ,
 227         },
 228 };
 229
 230 static struct sh_mmcif_plat_data sh_mmcif_plat = {
 231         .sup_pclk       = 0x0f,
 232         .caps           = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
 233                           MMC_CAP_NONREMOVABLE,
 234         .ocr            = MMC_VDD_32_33 | MMC_VDD_33_34,
 235         .slave_id_tx    = SHDMA_SLAVE_MMCIF_TX,
 236         .slave_id_rx    = SHDMA_SLAVE_MMCIF_RX,
 237 };
 238
 239 static struct platform_device sh_mmcif_device = {
 240         .name           = "sh_mmcif",
 241         .id             = 0,
 242         .dev            = {
 243                 .platform_data          = &sh_mmcif_plat,
 244         },
 245         .num_resources  = ARRAY_SIZE(sh_mmcif_resources),
 246         .resource       = sh_mmcif_resources,
 247 };
 248
 249 /* SDHI0 */
 250 static struct sh_mobile_sdhi_info sdhi_info = {
 251         .dma_slave_tx   = SHDMA_SLAVE_SDHI_TX,
 252         .dma_slave_rx   = SHDMA_SLAVE_SDHI_RX,
 253         .tmio_caps      = MMC_CAP_SD_HIGHSPEED,
 254 };
 255
 256 static struct resource sdhi_resources[] = {
 257         [0] = {
 258                 .start  = 0xffe50000,
 259                 .end    = 0xffe501ff,
 260                 .flags  = IORESOURCE_MEM,
 261         },
 262         [1] = {
 263                 .start  = evt2irq(0x480),
 264                 .flags  = IORESOURCE_IRQ,
 265         },
 266 };
 267
 268 static struct platform_device sdhi_device = {
 269         .name           = "sh_mobile_sdhi",
 270         .num_resources  = ARRAY_SIZE(sdhi_resources),
 271         .resource       = sdhi_resources,
 272         .id             = 0,
 273         .dev    = {
 274                 .platform_data  = &sdhi_info,
 275         },
 276 };
 277
 278 static int usbhs0_get_id(struct platform_device *pdev)
 279 {
 280         return USBHS_GADGET;
 281 }
 282
 283 static struct renesas_usbhs_platform_info usb0_data = {
 284         .platform_callback = {
 285                 .get_id = usbhs0_get_id,
 286         },
 287         .driver_param = {
 288                 .buswait_bwait = 5,
 289         }
 290 };
 291
 292 static struct resource usb0_resources[] = {
 293         [0] = {
 294                 .start  = 0xfe450000,
 295                 .end    = 0xfe4501ff,
 296                 .flags  = IORESOURCE_MEM,
 297         },
 298         [1] = {
 299                 .start  = evt2irq(0x840),
 300                 .end    = evt2irq(0x840),
 301                 .flags  = IORESOURCE_IRQ,
 302         },
 303 };
 304
 305 static struct platform_device usb0_device = {
 306         .name           = "renesas_usbhs",
 307         .id             = 0,
 308         .dev = {
 309                 .platform_data          = &usb0_data,
 310         },
 311         .num_resources  = ARRAY_SIZE(usb0_resources),
 312         .resource       = usb0_resources,
 313 };
 314
 315 static struct platform_device *sh7757lcr_devices[] __initdata = {
 316         &heartbeat_device,
 317         &sh7757_eth0_device,
 318         &sh7757_eth1_device,
 319         &sh7757_eth_giga0_device,
 320         &sh7757_eth_giga1_device,
 321         &sh_mmcif_device,
 322         &sdhi_device,
 323         &usb0_device,
 324 };
 325
 326 static struct flash_platform_data spi_flash_data = {
 327         .name = "m25p80",
 328         .type = "m25px64",
 329 };
 330
 331 static struct spi_board_info spi_board_info[] = {
 332         {
 333                 .modalias = "m25p80",
 334                 .max_speed_hz = 25000000,
 335                 .bus_num = 0,
 336                 .chip_select = 1,
 337                 .platform_data = &spi_flash_data,
 338         },
 339 };
 340
 341 static int __init sh7757lcr_devices_setup(void)
 342 {
 343         regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
 344                                      ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
 345
 346         /* RGMII (PTA) */
 347         gpio_request(GPIO_FN_ET0_MDC, NULL);
 348         gpio_request(GPIO_FN_ET0_MDIO, NULL);
 349         gpio_request(GPIO_FN_ET1_MDC, NULL);
 350         gpio_request(GPIO_FN_ET1_MDIO, NULL);
 351
 352         /* ONFI (PTB, PTZ) */
 353         gpio_request(GPIO_FN_ON_NRE, NULL);
 354         gpio_request(GPIO_FN_ON_NWE, NULL);
 355         gpio_request(GPIO_FN_ON_NWP, NULL);
 356         gpio_request(GPIO_FN_ON_NCE0, NULL);
 357         gpio_request(GPIO_FN_ON_R_B0, NULL);
 358         gpio_request(GPIO_FN_ON_ALE, NULL);
 359         gpio_request(GPIO_FN_ON_CLE, NULL);
 360
 361         gpio_request(GPIO_FN_ON_DQ7, NULL);
 362         gpio_request(GPIO_FN_ON_DQ6, NULL);
 363         gpio_request(GPIO_FN_ON_DQ5, NULL);
 364         gpio_request(GPIO_FN_ON_DQ4, NULL);
 365         gpio_request(GPIO_FN_ON_DQ3, NULL);
 366         gpio_request(GPIO_FN_ON_DQ2, NULL);
 367         gpio_request(GPIO_FN_ON_DQ1, NULL);
 368         gpio_request(GPIO_FN_ON_DQ0, NULL);
 369
 370         /* IRQ8 to 0 (PTB, PTC) */
 371         gpio_request(GPIO_FN_IRQ8, NULL);
 372         gpio_request(GPIO_FN_IRQ7, NULL);
 373         gpio_request(GPIO_FN_IRQ6, NULL);
 374         gpio_request(GPIO_FN_IRQ5, NULL);
 375         gpio_request(GPIO_FN_IRQ4, NULL);
 376         gpio_request(GPIO_FN_IRQ3, NULL);
 377         gpio_request(GPIO_FN_IRQ2, NULL);
 378         gpio_request(GPIO_FN_IRQ1, NULL);
 379         gpio_request(GPIO_FN_IRQ0, NULL);
 380
 381         /* SPI0 (PTD) */
 382         gpio_request(GPIO_FN_SP0_MOSI, NULL);
 383         gpio_request(GPIO_FN_SP0_MISO, NULL);
 384         gpio_request(GPIO_FN_SP0_SCK, NULL);
 385         gpio_request(GPIO_FN_SP0_SCK_FB, NULL);
 386         gpio_request(GPIO_FN_SP0_SS0, NULL);
 387         gpio_request(GPIO_FN_SP0_SS1, NULL);
 388         gpio_request(GPIO_FN_SP0_SS2, NULL);
 389         gpio_request(GPIO_FN_SP0_SS3, NULL);
 390
 391         /* RMII 0/1 (PTE, PTF) */
 392         gpio_request(GPIO_FN_RMII0_CRS_DV, NULL);
 393         gpio_request(GPIO_FN_RMII0_TXD1, NULL);
 394         gpio_request(GPIO_FN_RMII0_TXD0, NULL);
 395         gpio_request(GPIO_FN_RMII0_TXEN, NULL);
 396         gpio_request(GPIO_FN_RMII0_REFCLK, NULL);
 397         gpio_request(GPIO_FN_RMII0_RXD1, NULL);
 398         gpio_request(GPIO_FN_RMII0_RXD0, NULL);
 399         gpio_request(GPIO_FN_RMII0_RX_ER, NULL);
 400         gpio_request(GPIO_FN_RMII1_CRS_DV, NULL);
 401         gpio_request(GPIO_FN_RMII1_TXD1, NULL);
 402         gpio_request(GPIO_FN_RMII1_TXD0, NULL);
 403         gpio_request(GPIO_FN_RMII1_TXEN, NULL);
 404         gpio_request(GPIO_FN_RMII1_REFCLK, NULL);
 405         gpio_request(GPIO_FN_RMII1_RXD1, NULL);
 406         gpio_request(GPIO_FN_RMII1_RXD0, NULL);
 407         gpio_request(GPIO_FN_RMII1_RX_ER, NULL);
 408
 409         /* eMMC (PTG) */
 410         gpio_request(GPIO_FN_MMCCLK, NULL);
 411         gpio_request(GPIO_FN_MMCCMD, NULL);
 412         gpio_request(GPIO_FN_MMCDAT7, NULL);
 413         gpio_request(GPIO_FN_MMCDAT6, NULL);
 414         gpio_request(GPIO_FN_MMCDAT5, NULL);
 415         gpio_request(GPIO_FN_MMCDAT4, NULL);
 416         gpio_request(GPIO_FN_MMCDAT3, NULL);
 417         gpio_request(GPIO_FN_MMCDAT2, NULL);
 418         gpio_request(GPIO_FN_MMCDAT1, NULL);
 419         gpio_request(GPIO_FN_MMCDAT0, NULL);
 420
 421         /* LPC (PTG, PTH, PTQ, PTU) */
 422         gpio_request(GPIO_FN_SERIRQ, NULL);
 423         gpio_request(GPIO_FN_LPCPD, NULL);
 424         gpio_request(GPIO_FN_LDRQ, NULL);
 425         gpio_request(GPIO_FN_WP, NULL);
 426         gpio_request(GPIO_FN_FMS0, NULL);
 427         gpio_request(GPIO_FN_LAD3, NULL);
 428         gpio_request(GPIO_FN_LAD2, NULL);
 429         gpio_request(GPIO_FN_LAD1, NULL);
 430         gpio_request(GPIO_FN_LAD0, NULL);
 431         gpio_request(GPIO_FN_LFRAME, NULL);
 432         gpio_request(GPIO_FN_LRESET, NULL);
 433         gpio_request(GPIO_FN_LCLK, NULL);
 434         gpio_request(GPIO_FN_LGPIO7, NULL);
 435         gpio_request(GPIO_FN_LGPIO6, NULL);
 436         gpio_request(GPIO_FN_LGPIO5, NULL);
 437         gpio_request(GPIO_FN_LGPIO4, NULL);
 438
 439         /* SPI1 (PTH) */
 440         gpio_request(GPIO_FN_SP1_MOSI, NULL);
 441         gpio_request(GPIO_FN_SP1_MISO, NULL);
 442         gpio_request(GPIO_FN_SP1_SCK, NULL);
 443         gpio_request(GPIO_FN_SP1_SCK_FB, NULL);
 444         gpio_request(GPIO_FN_SP1_SS0, NULL);
 445         gpio_request(GPIO_FN_SP1_SS1, NULL);
 446
 447         /* SDHI (PTI) */
 448         gpio_request(GPIO_FN_SD_WP, NULL);
 449         gpio_request(GPIO_FN_SD_CD, NULL);
 450         gpio_request(GPIO_FN_SD_CLK, NULL);
 451         gpio_request(GPIO_FN_SD_CMD, NULL);
 452         gpio_request(GPIO_FN_SD_D3, NULL);
 453         gpio_request(GPIO_FN_SD_D2, NULL);
 454         gpio_request(GPIO_FN_SD_D1, NULL);
 455         gpio_request(GPIO_FN_SD_D0, NULL);
 456
 457         /* SCIF3/4 (PTJ, PTW) */
 458         gpio_request(GPIO_FN_RTS3, NULL);
 459         gpio_request(GPIO_FN_CTS3, NULL);
 460         gpio_request(GPIO_FN_TXD3, NULL);
 461         gpio_request(GPIO_FN_RXD3, NULL);
 462         gpio_request(GPIO_FN_RTS4, NULL);
 463         gpio_request(GPIO_FN_RXD4, NULL);
 464         gpio_request(GPIO_FN_TXD4, NULL);
 465         gpio_request(GPIO_FN_CTS4, NULL);
 466
 467         /* SERMUX (PTK, PTL, PTO, PTV) */
 468         gpio_request(GPIO_FN_COM2_TXD, NULL);
 469         gpio_request(GPIO_FN_COM2_RXD, NULL);
 470         gpio_request(GPIO_FN_COM2_RTS, NULL);
 471         gpio_request(GPIO_FN_COM2_CTS, NULL);
 472         gpio_request(GPIO_FN_COM2_DTR, NULL);
 473         gpio_request(GPIO_FN_COM2_DSR, NULL);
 474         gpio_request(GPIO_FN_COM2_DCD, NULL);
 475         gpio_request(GPIO_FN_COM2_RI, NULL);
 476         gpio_request(GPIO_FN_RAC_RXD, NULL);
 477         gpio_request(GPIO_FN_RAC_RTS, NULL);
 478         gpio_request(GPIO_FN_RAC_CTS, NULL);
 479         gpio_request(GPIO_FN_RAC_DTR, NULL);
 480         gpio_request(GPIO_FN_RAC_DSR, NULL);
 481         gpio_request(GPIO_FN_RAC_DCD, NULL);
 482         gpio_request(GPIO_FN_RAC_TXD, NULL);
 483         gpio_request(GPIO_FN_COM1_TXD, NULL);
 484         gpio_request(GPIO_FN_COM1_RXD, NULL);
 485         gpio_request(GPIO_FN_COM1_RTS, NULL);
 486         gpio_request(GPIO_FN_COM1_CTS, NULL);
 487
 488         writeb(0x10, 0xfe470000);       /* SMR0: SerMux mode 0 */
 489
 490         /* IIC (PTM, PTR, PTS) */
 491         gpio_request(GPIO_FN_SDA7, NULL);
 492         gpio_request(GPIO_FN_SCL7, NULL);
 493         gpio_request(GPIO_FN_SDA6, NULL);
 494         gpio_request(GPIO_FN_SCL6, NULL);
 495         gpio_request(GPIO_FN_SDA5, NULL);
 496         gpio_request(GPIO_FN_SCL5, NULL);
 497         gpio_request(GPIO_FN_SDA4, NULL);
 498         gpio_request(GPIO_FN_SCL4, NULL);
 499         gpio_request(GPIO_FN_SDA3, NULL);
 500         gpio_request(GPIO_FN_SCL3, NULL);
 501         gpio_request(GPIO_FN_SDA2, NULL);
 502         gpio_request(GPIO_FN_SCL2, NULL);
 503         gpio_request(GPIO_FN_SDA1, NULL);
 504         gpio_request(GPIO_FN_SCL1, NULL);
 505         gpio_request(GPIO_FN_SDA0, NULL);
 506         gpio_request(GPIO_FN_SCL0, NULL);
 507
 508         /* USB (PTN) */
 509         gpio_request(GPIO_FN_VBUS_EN, NULL);
 510         gpio_request(GPIO_FN_VBUS_OC, NULL);
 511
 512         /* SGPIO1/0 (PTN, PTO) */
 513         gpio_request(GPIO_FN_SGPIO1_CLK, NULL);
 514         gpio_request(GPIO_FN_SGPIO1_LOAD, NULL);
 515         gpio_request(GPIO_FN_SGPIO1_DI, NULL);
 516         gpio_request(GPIO_FN_SGPIO1_DO, NULL);
 517         gpio_request(GPIO_FN_SGPIO0_CLK, NULL);
 518         gpio_request(GPIO_FN_SGPIO0_LOAD, NULL);
 519         gpio_request(GPIO_FN_SGPIO0_DI, NULL);
 520         gpio_request(GPIO_FN_SGPIO0_DO, NULL);
 521
 522         /* WDT (PTN) */
 523         gpio_request(GPIO_FN_SUB_CLKIN, NULL);
 524
 525         /* System (PTT) */
 526         gpio_request(GPIO_FN_STATUS1, NULL);
 527         gpio_request(GPIO_FN_STATUS0, NULL);
 528
 529         /* PWMX (PTT) */
 530         gpio_request(GPIO_FN_PWMX1, NULL);
 531         gpio_request(GPIO_FN_PWMX0, NULL);
 532
 533         /* R-SPI (PTV) */
 534         gpio_request(GPIO_FN_R_SPI_MOSI, NULL);
 535         gpio_request(GPIO_FN_R_SPI_MISO, NULL);
 536         gpio_request(GPIO_FN_R_SPI_RSPCK, NULL);
 537         gpio_request(GPIO_FN_R_SPI_SSL0, NULL);
 538         gpio_request(GPIO_FN_R_SPI_SSL1, NULL);
 539
 540         /* EVC (PTV, PTW) */
 541         gpio_request(GPIO_FN_EVENT7, NULL);
 542         gpio_request(GPIO_FN_EVENT6, NULL);
 543         gpio_request(GPIO_FN_EVENT5, NULL);
 544         gpio_request(GPIO_FN_EVENT4, NULL);
 545         gpio_request(GPIO_FN_EVENT3, NULL);
 546         gpio_request(GPIO_FN_EVENT2, NULL);
 547         gpio_request(GPIO_FN_EVENT1, NULL);
 548         gpio_request(GPIO_FN_EVENT0, NULL);
 549
 550         /* LED for heartbeat */
 551         gpio_request(GPIO_PTU3, NULL);
 552         gpio_direction_output(GPIO_PTU3, 1);
 553         gpio_request(GPIO_PTU2, NULL);
 554         gpio_direction_output(GPIO_PTU2, 1);
 555         gpio_request(GPIO_PTU1, NULL);
 556         gpio_direction_output(GPIO_PTU1, 1);
 557         gpio_request(GPIO_PTU0, NULL);
 558         gpio_direction_output(GPIO_PTU0, 1);
 559
 560         /* control for MDIO of Gigabit Ethernet */
 561         gpio_request(GPIO_PTT4, NULL);
 562         gpio_direction_output(GPIO_PTT4, 1);
 563
 564         /* control for eMMC */
 565         gpio_request(GPIO_PTT7, NULL);          /* eMMC_RST# */
 566         gpio_direction_output(GPIO_PTT7, 0);
 567         gpio_request(GPIO_PTT6, NULL);          /* eMMC_INDEX# */
 568         gpio_direction_output(GPIO_PTT6, 0);
 569         gpio_request(GPIO_PTT5, NULL);          /* eMMC_PRST# */
 570         gpio_direction_output(GPIO_PTT5, 1);
 571
 572         /* register SPI device information */
 573         spi_register_board_info(spi_board_info,
 574                                 ARRAY_SIZE(spi_board_info));
 575
 576         /* General platform */
 577         return platform_add_devices(sh7757lcr_devices,
 578                                     ARRAY_SIZE(sh7757lcr_devices));
 579 }
 580 arch_initcall(sh7757lcr_devices_setup);
 581
 582 /* Initialize IRQ setting */
 583 void __init init_sh7757lcr_IRQ(void)
 584 {
 585         plat_irq_setup_pins(IRQ_MODE_IRQ7654);
 586         plat_irq_setup_pins(IRQ_MODE_IRQ3210);
 587 }
 588
 589 /* Initialize the board */
 590 static void __init sh7757lcr_setup(char **cmdline_p)
 591 {
 592         printk(KERN_INFO "Renesas R0P7757LC0012RL support.\n");
 593 }
 594
 595 static int sh7757lcr_mode_pins(void)
 596 {
 597         int value = 0;
 598
 599         /* These are the factory default settings of S3 (Low active).
 600          * If you change these dip switches then you will need to
 601          * adjust the values below as well.
 602          */
 603         value |= MODE_PIN0;     /* Clock Mode: 1 */
 604
 605         return value;
 606 }
 607
 608 /* The Machine Vector */
 609 static struct sh_machine_vector mv_sh7757lcr __initmv = {
 610         .mv_name                = "SH7757LCR",
 611         .mv_setup               = sh7757lcr_setup,
 612         .mv_init_irq            = init_sh7757lcr_IRQ,
 613         .mv_mode_pins           = sh7757lcr_mode_pins,
 614 };
 615