arch/sh/boards/mach-se/7722/irq.c

   1 /*
   2  * Hitachi UL SolutionEngine 7722 FPGA IRQ Support.
   3  *
   4  * Copyright (C) 2007  Nobuhiro Iwamatsu
   5  * Copyright (C) 2012  Paul Mundt
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  */
  11 #define DRV_NAME "SE7722-FPGA"
  12 #define pr_fmt(fmt) DRV_NAME ": " fmt
  13
  14 #define irq_reg_readl   ioread16
  15 #define irq_reg_writel  iowrite16
  16
  17 #include <linux/init.h>
  18 #include <linux/irq.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/irqdomain.h>
  21 #include <linux/io.h>
  22 #include <linux/err.h>
  23 #include <asm/sizes.h>
  24 #include <mach-se/mach/se7722.h>
  25
  26 #define IRQ01_BASE_ADDR 0x11800000
  27 #define IRQ01_MODE_REG  0
  28 #define IRQ01_STS_REG   4
  29 #define IRQ01_MASK_REG  8
  30
  31 static void __iomem *se7722_irq_regs;
  32 struct irq_domain *se7722_irq_domain;
  33
  34 static void se7722_irq_demux(unsigned int irq, struct irq_desc *desc)
  35 {
  36         struct irq_data *data = irq_get_irq_data(irq);
  37         struct irq_chip *chip = irq_data_get_irq_chip(data);
  38         unsigned long mask;
  39         int bit;
  40
  41         chip->irq_mask_ack(data);
  42
  43         mask = ioread16(se7722_irq_regs + IRQ01_STS_REG);
  44
  45         for_each_set_bit(bit, &mask, SE7722_FPGA_IRQ_NR)
  46                 generic_handle_irq(irq_linear_revmap(se7722_irq_domain, bit));
  47
  48         chip->irq_unmask(data);
  49 }
  50
  51 static void __init se7722_domain_init(void)
  52 {
  53         int i;
  54
  55         se7722_irq_domain = irq_domain_add_linear(NULL, SE7722_FPGA_IRQ_NR,
  56                                                   &irq_domain_simple_ops, NULL);
  57         if (unlikely(!se7722_irq_domain)) {
  58                 printk("Failed to get IRQ domain\n");
  59                 return;
  60         }
  61
  62         for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) {
  63                 int irq = irq_create_mapping(se7722_irq_domain, i);
  64
  65                 if (unlikely(irq == 0)) {
  66                         printk("Failed to allocate IRQ %d\n", i);
  67                         return;
  68                 }
  69         }
  70 }
  71
  72 static void __init se7722_gc_init(void)
  73 {
  74         struct irq_chip_generic *gc;
  75         struct irq_chip_type *ct;
  76         unsigned int irq_base;
  77
  78         irq_base = irq_linear_revmap(se7722_irq_domain, 0);
  79
  80         gc = irq_alloc_generic_chip(DRV_NAME, 1, irq_base, se7722_irq_regs,
  81                                     handle_level_irq);
  82         if (unlikely(!gc))
  83                 return;
  84
  85         ct = gc->chip_types;
  86         ct->chip.irq_mask = irq_gc_mask_set_bit;
  87         ct->chip.irq_unmask = irq_gc_mask_clr_bit;
  88
  89         ct->regs.mask = IRQ01_MASK_REG;
  90
  91         irq_setup_generic_chip(gc, IRQ_MSK(SE7722_FPGA_IRQ_NR),
  92                                IRQ_GC_INIT_MASK_CACHE,
  93                                IRQ_NOREQUEST | IRQ_NOPROBE, 0);
  94
  95         irq_set_chained_handler(IRQ0_IRQ, se7722_irq_demux);
  96         irq_set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW);
  97
  98         irq_set_chained_handler(IRQ1_IRQ, se7722_irq_demux);
  99         irq_set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW);
 100 }
 101
 102 /*
 103  * Initialize FPGA IRQs
 104  */
 105 void __init init_se7722_IRQ(void)
 106 {
 107         se7722_irq_regs = ioremap(IRQ01_BASE_ADDR, SZ_16);
 108         if (unlikely(!se7722_irq_regs)) {
 109                 printk("Failed to remap IRQ01 regs\n");
 110                 return;
 111         }
 112
 113         /*
 114          * All FPGA IRQs disabled by default
 115          */
 116         iowrite16(0, se7722_irq_regs + IRQ01_MASK_REG);
 117
 118         __raw_writew(0x2000, 0xb03fffec);  /* mrshpc irq enable */
 119
 120         se7722_domain_init();
 121         se7722_gc_init();
 122 }