2 * arch/sh/boards/se/7343/irq.c
5 #include <linux/init.h>
6 #include <linux/interrupt.h>
10 #include <asm/mach/se7343.h>
13 disable_intreq_irq(unsigned int irq
)
15 int bit
= irq
- OFFCHIP_IRQ_BASE
;
18 val
= ctrl_inw(PA_CPLD_IMSK
);
20 ctrl_outw(val
, PA_CPLD_IMSK
);
24 enable_intreq_irq(unsigned int irq
)
26 int bit
= irq
- OFFCHIP_IRQ_BASE
;
29 val
= ctrl_inw(PA_CPLD_IMSK
);
31 ctrl_outw(val
, PA_CPLD_IMSK
);
35 mask_and_ack_intreq_irq(unsigned int irq
)
37 disable_intreq_irq(irq
);
41 startup_intreq_irq(unsigned int irq
)
43 enable_intreq_irq(irq
);
48 shutdown_intreq_irq(unsigned int irq
)
50 disable_intreq_irq(irq
);
54 end_intreq_irq(unsigned int irq
)
56 if (!(irq_desc
[irq
].status
& (IRQ_DISABLED
| IRQ_INPROGRESS
)))
57 enable_intreq_irq(irq
);
60 static struct hw_interrupt_type intreq_irq_type
= {
61 .typename
= "FPGA-IRQ",
62 .startup
= startup_intreq_irq
,
63 .shutdown
= shutdown_intreq_irq
,
64 .enable
= enable_intreq_irq
,
65 .disable
= disable_intreq_irq
,
66 .ack
= mask_and_ack_intreq_irq
,
71 make_intreq_irq(unsigned int irq
)
73 disable_irq_nosync(irq
);
74 irq_desc
[irq
].chip
= &intreq_irq_type
;
75 disable_intreq_irq(irq
);
79 shmse_irq_demux(int irq
)
84 if (irq
== IRQ5_IRQ
) {
85 /* Read status Register */
86 val
= ctrl_inw(PA_CPLD_ST
);
89 return OFFCHIP_IRQ_BASE
+ bit
- 1;
94 /* IRQ5 is multiplexed between the following sources:
98 * 4. Serial Controller
100 * We configure IRQ5 as a cascade IRQ.
102 static struct irqaction irq5
= { no_action
, 0, CPU_MASK_NONE
, "IRQ5-cascade",
106 * Initialize IRQ setting
109 init_7343se_IRQ(void)
111 /* Setup Multiplexed interrupts */
112 ctrl_outw(8, PA_CPLD_MODESET
); /* Set all CPLD interrupts to active
115 /* Mask all CPLD controller interrupts */
116 ctrl_outw(0x0fff, PA_CPLD_IMSK
);
118 /* PC Card interrupts */
119 make_intreq_irq(PC_IRQ0
);
120 make_intreq_irq(PC_IRQ1
);
121 make_intreq_irq(PC_IRQ2
);
122 make_intreq_irq(PC_IRQ3
);
124 /* Extension Slot Interrupts */
125 make_intreq_irq(EXT_IRQ0
);
126 make_intreq_irq(EXT_IRQ1
);
127 make_intreq_irq(EXT_IRQ2
);
128 make_intreq_irq(EXT_IRQ3
);
130 /* USB Controller interrupts */
131 make_intreq_irq(USB_IRQ0
);
132 make_intreq_irq(USB_IRQ1
);
134 /* Serial Controller interrupts */
135 make_intreq_irq(UART_IRQ0
);
136 make_intreq_irq(UART_IRQ1
);
138 /* Setup all external interrupts to be active low */
139 ctrl_outw(0xaaaa, INTC_ICR1
);
141 make_ipr_irq(IRQ5_IRQ
, IRQ5_IPR_ADDR
+2, IRQ5_IPR_POS
, IRQ5_PRIORITY
);
142 setup_irq(IRQ5_IRQ
, &irq5
);
143 /* Set port control to use IRQ5 */
144 *(u16
*)0xA4050108 &= ~0xc;
146 make_ipr_irq(SIOF0_IRQ
, SIOF0_IPR_ADDR
, SIOF0_IPR_POS
, SIOF0_PRIORITY
);
147 make_ipr_irq(VPU_IRQ
, VPU_IPR_ADDR
, VPU_IPR_POS
, 8);
149 ctrl_outb(0x0f, INTC_IMCR5
); /* enable SCIF IRQ */
151 make_ipr_irq(DMTE0_IRQ
, DMA1_IPR_ADDR
, DMA1_IPR_POS
, DMA1_PRIORITY
);
152 make_ipr_irq(DMTE1_IRQ
, DMA1_IPR_ADDR
, DMA1_IPR_POS
, DMA1_PRIORITY
);
153 make_ipr_irq(DMTE2_IRQ
, DMA1_IPR_ADDR
, DMA1_IPR_POS
, DMA1_PRIORITY
);
154 make_ipr_irq(DMTE3_IRQ
, DMA1_IPR_ADDR
, DMA1_IPR_POS
, DMA1_PRIORITY
);
155 make_ipr_irq(DMTE4_IRQ
, DMA2_IPR_ADDR
, DMA2_IPR_POS
, DMA2_PRIORITY
);
156 make_ipr_irq(DMTE5_IRQ
, DMA2_IPR_ADDR
, DMA2_IPR_POS
, DMA2_PRIORITY
);
159 make_ipr_irq(IIC0_ALI_IRQ
, IIC0_IPR_ADDR
, IIC0_IPR_POS
, IIC0_PRIORITY
);
160 make_ipr_irq(IIC0_TACKI_IRQ
, IIC0_IPR_ADDR
, IIC0_IPR_POS
,
162 make_ipr_irq(IIC0_WAITI_IRQ
, IIC0_IPR_ADDR
, IIC0_IPR_POS
,
164 make_ipr_irq(IIC0_DTEI_IRQ
, IIC0_IPR_ADDR
, IIC0_IPR_POS
, IIC0_PRIORITY
);
166 make_ipr_irq(IIC1_ALI_IRQ
, IIC1_IPR_ADDR
, IIC1_IPR_POS
, IIC1_PRIORITY
);
167 make_ipr_irq(IIC1_TACKI_IRQ
, IIC1_IPR_ADDR
, IIC1_IPR_POS
,
169 make_ipr_irq(IIC1_WAITI_IRQ
, IIC1_IPR_ADDR
, IIC1_IPR_POS
,
171 make_ipr_irq(IIC1_DTEI_IRQ
, IIC1_IPR_ADDR
, IIC1_IPR_POS
, IIC1_PRIORITY
);
174 make_ipr_irq(SIOF0_IRQ
, SIOF0_IPR_ADDR
, SIOF0_IPR_POS
, SIOF0_PRIORITY
);
177 make_ipr_irq(SIU_IRQ
, SIU_IPR_ADDR
, SIU_IPR_POS
, SIU_PRIORITY
);
180 make_ipr_irq(CEU_IRQ
, VIO_IPR_ADDR
, VIO_IPR_POS
, VIO_PRIORITY
);
181 make_ipr_irq(BEU_IRQ
, VIO_IPR_ADDR
, VIO_IPR_POS
, VIO_PRIORITY
);
182 make_ipr_irq(VEU_IRQ
, VIO_IPR_ADDR
, VIO_IPR_POS
, VIO_PRIORITY
);
186 make_ipr_irq(MFI_IRQ
, MFI_IPR_ADDR
, MFI_IPR_POS
, MFI_PRIORITY
);
189 make_ipr_irq(LCDC_IRQ
, LCDC_IPR_ADDR
, LCDC_IPR_POS
, LCDC_PRIORITY
);
190 ctrl_outw(0x2000, PA_MRSHPC
+ 0x0c); /* mrshpc irq enable */