arch/sh/drivers/dma/dma-sh.c

   1 /*
   2  * arch/sh/drivers/dma/dma-sh.c
   3  *
   4  * SuperH On-chip DMAC Support
   5  *
   6  * Copyright (C) 2000 Takashi YOSHII
   7  * Copyright (C) 2003, 2004 Paul Mundt
   8  * Copyright (C) 2005 Andriy Skulysh
   9  *
  10  * This file is subject to the terms and conditions of the GNU General Public
  11  * License.  See the file "COPYING" in the main directory of this archive
  12  * for more details.
  13  */
  14 #include <linux/init.h>
  15 #include <linux/interrupt.h>
  16 #include <linux/module.h>
  17 #include <asm/dreamcast/dma.h>
  18 #include <asm/dma.h>
  19 #include <asm/io.h>
  20 #include "dma-sh.h"
  21
  22 static int dmte_irq_map[] = {
  23         DMTE0_IRQ,
  24         DMTE1_IRQ,
  25         DMTE2_IRQ,
  26         DMTE3_IRQ,
  27 #if defined(CONFIG_CPU_SUBTYPE_SH7720)  ||      \
  28     defined(CONFIG_CPU_SUBTYPE_SH7721)  ||      \
  29     defined(CONFIG_CPU_SUBTYPE_SH7751R) ||      \
  30     defined(CONFIG_CPU_SUBTYPE_SH7760)  ||      \
  31     defined(CONFIG_CPU_SUBTYPE_SH7709)  ||      \
  32     defined(CONFIG_CPU_SUBTYPE_SH7780)
  33         DMTE4_IRQ,
  34         DMTE5_IRQ,
  35 #endif
  36 #if defined(CONFIG_CPU_SUBTYPE_SH7751R) ||      \
  37     defined(CONFIG_CPU_SUBTYPE_SH7760)  ||      \
  38     defined(CONFIG_CPU_SUBTYPE_SH7780)
  39         DMTE6_IRQ,
  40         DMTE7_IRQ,
  41 #endif
  42 };
  43
  44 static inline unsigned int get_dmte_irq(unsigned int chan)
  45 {
  46         unsigned int irq = 0;
  47         if (chan < ARRAY_SIZE(dmte_irq_map))
  48                 irq = dmte_irq_map[chan];
  49         return irq;
  50 }
  51
  52 /*
  53  * We determine the correct shift size based off of the CHCR transmit size
  54  * for the given channel. Since we know that it will take:
  55  *
  56  *      info->count >> ts_shift[transmit_size]
  57  *
  58  * iterations to complete the transfer.
  59  */
  60 static inline unsigned int calc_xmit_shift(struct dma_channel *chan)
  61 {
  62         u32 chcr = ctrl_inl(CHCR[chan->chan]);
  63
  64         return ts_shift[(chcr & CHCR_TS_MASK)>>CHCR_TS_SHIFT];
  65 }
  66
  67 /*
  68  * The transfer end interrupt must read the chcr register to end the
  69  * hardware interrupt active condition.
  70  * Besides that it needs to waken any waiting process, which should handle
  71  * setting up the next transfer.
  72  */
  73 static irqreturn_t dma_tei(int irq, void *dev_id)
  74 {
  75         struct dma_channel *chan = dev_id;
  76         u32 chcr;
  77
  78         chcr = ctrl_inl(CHCR[chan->chan]);
  79
  80         if (!(chcr & CHCR_TE))
  81                 return IRQ_NONE;
  82
  83         chcr &= ~(CHCR_IE | CHCR_DE);
  84         ctrl_outl(chcr, CHCR[chan->chan]);
  85
  86         wake_up(&chan->wait_queue);
  87
  88         return IRQ_HANDLED;
  89 }
  90
  91 static int sh_dmac_request_dma(struct dma_channel *chan)
  92 {
  93         if (unlikely(!(chan->flags & DMA_TEI_CAPABLE)))
  94                 return 0;
  95
  96         return request_irq(get_dmte_irq(chan->chan), dma_tei,
  97                            IRQF_DISABLED, chan->dev_id, chan);
  98 }
  99
 100 static void sh_dmac_free_dma(struct dma_channel *chan)
 101 {
 102         free_irq(get_dmte_irq(chan->chan), chan);
 103 }
 104
 105 static int
 106 sh_dmac_configure_channel(struct dma_channel *chan, unsigned long chcr)
 107 {
 108         if (!chcr)
 109                 chcr = RS_DUAL | CHCR_IE;
 110
 111         if (chcr & CHCR_IE) {
 112                 chcr &= ~CHCR_IE;
 113                 chan->flags |= DMA_TEI_CAPABLE;
 114         } else {
 115                 chan->flags &= ~DMA_TEI_CAPABLE;
 116         }
 117
 118         ctrl_outl(chcr, CHCR[chan->chan]);
 119
 120         chan->flags |= DMA_CONFIGURED;
 121         return 0;
 122 }
 123
 124 static void sh_dmac_enable_dma(struct dma_channel *chan)
 125 {
 126         int irq;
 127         u32 chcr;
 128
 129         chcr = ctrl_inl(CHCR[chan->chan]);
 130         chcr |= CHCR_DE;
 131
 132         if (chan->flags & DMA_TEI_CAPABLE)
 133                 chcr |= CHCR_IE;
 134
 135         ctrl_outl(chcr, CHCR[chan->chan]);
 136
 137         if (chan->flags & DMA_TEI_CAPABLE) {
 138                 irq = get_dmte_irq(chan->chan);
 139                 enable_irq(irq);
 140         }
 141 }
 142
 143 static void sh_dmac_disable_dma(struct dma_channel *chan)
 144 {
 145         int irq;
 146         u32 chcr;
 147
 148         if (chan->flags & DMA_TEI_CAPABLE) {
 149                 irq = get_dmte_irq(chan->chan);
 150                 disable_irq(irq);
 151         }
 152
 153         chcr = ctrl_inl(CHCR[chan->chan]);
 154         chcr &= ~(CHCR_DE | CHCR_TE | CHCR_IE);
 155         ctrl_outl(chcr, CHCR[chan->chan]);
 156 }
 157
 158 static int sh_dmac_xfer_dma(struct dma_channel *chan)
 159 {
 160         /*
 161          * If we haven't pre-configured the channel with special flags, use
 162          * the defaults.
 163          */
 164         if (unlikely(!(chan->flags & DMA_CONFIGURED)))
 165                 sh_dmac_configure_channel(chan, 0);
 166
 167         sh_dmac_disable_dma(chan);
 168
 169         /*
 170          * Single-address mode usage note!
 171          *
 172          * It's important that we don't accidentally write any value to SAR/DAR
 173          * (this includes 0) that hasn't been directly specified by the user if
 174          * we're in single-address mode.
 175          *
 176          * In this case, only one address can be defined, anything else will
 177          * result in a DMA address error interrupt (at least on the SH-4),
 178          * which will subsequently halt the transfer.
 179          *
 180          * Channel 2 on the Dreamcast is a special case, as this is used for
 181          * cascading to the PVR2 DMAC. In this case, we still need to write
 182          * SAR and DAR, regardless of value, in order for cascading to work.
 183          */
 184         if (chan->sar || (mach_is_dreamcast() &&
 185                           chan->chan == PVR2_CASCADE_CHAN))
 186                 ctrl_outl(chan->sar, SAR[chan->chan]);
 187         if (chan->dar || (mach_is_dreamcast() &&
 188                           chan->chan == PVR2_CASCADE_CHAN))
 189                 ctrl_outl(chan->dar, DAR[chan->chan]);
 190
 191         ctrl_outl(chan->count >> calc_xmit_shift(chan), DMATCR[chan->chan]);
 192
 193         sh_dmac_enable_dma(chan);
 194
 195         return 0;
 196 }
 197
 198 static int sh_dmac_get_dma_residue(struct dma_channel *chan)
 199 {
 200         if (!(ctrl_inl(CHCR[chan->chan]) & CHCR_DE))
 201                 return 0;
 202
 203         return ctrl_inl(DMATCR[chan->chan]) << calc_xmit_shift(chan);
 204 }
 205
 206 #if defined(CONFIG_CPU_SUBTYPE_SH7720) || \
 207     defined(CONFIG_CPU_SUBTYPE_SH7721) || \
 208     defined(CONFIG_CPU_SUBTYPE_SH7780)
 209 #define dmaor_read_reg()        ctrl_inw(DMAOR)
 210 #define dmaor_write_reg(data)   ctrl_outw(data, DMAOR)
 211 #else
 212 #define dmaor_read_reg()        ctrl_inl(DMAOR)
 213 #define dmaor_write_reg(data)   ctrl_outl(data, DMAOR)
 214 #endif
 215
 216 static inline int dmaor_reset(void)
 217 {
 218         unsigned long dmaor = dmaor_read_reg();
 219
 220         /* Try to clear the error flags first, incase they are set */
 221         dmaor &= ~(DMAOR_NMIF | DMAOR_AE);
 222         dmaor_write_reg(dmaor);
 223
 224         dmaor |= DMAOR_INIT;
 225         dmaor_write_reg(dmaor);
 226
 227         /* See if we got an error again */
 228         if ((dmaor_read_reg() & (DMAOR_AE | DMAOR_NMIF))) {
 229                 printk(KERN_ERR "dma-sh: Can't initialize DMAOR.\n");
 230                 return -EINVAL;
 231         }
 232
 233         return 0;
 234 }
 235
 236 #if defined(CONFIG_CPU_SH4)
 237 static irqreturn_t dma_err(int irq, void *dummy)
 238 {
 239         dmaor_reset();
 240         disable_irq(irq);
 241
 242         return IRQ_HANDLED;
 243 }
 244 #endif
 245
 246 static struct dma_ops sh_dmac_ops = {
 247         .request        = sh_dmac_request_dma,
 248         .free           = sh_dmac_free_dma,
 249         .get_residue    = sh_dmac_get_dma_residue,
 250         .xfer           = sh_dmac_xfer_dma,
 251         .configure      = sh_dmac_configure_channel,
 252 };
 253
 254 static struct dma_info sh_dmac_info = {
 255         .name           = "sh_dmac",
 256         .nr_channels    = CONFIG_NR_ONCHIP_DMA_CHANNELS,
 257         .ops            = &sh_dmac_ops,
 258         .flags          = DMAC_CHANNELS_TEI_CAPABLE,
 259 };
 260
 261 static int __init sh_dmac_init(void)
 262 {
 263         struct dma_info *info = &sh_dmac_info;
 264         int i;
 265
 266 #ifdef CONFIG_CPU_SH4
 267         i = request_irq(DMAE_IRQ, dma_err, IRQF_DISABLED, "DMAC Address Error", 0);
 268         if (unlikely(i < 0))
 269                 return i;
 270 #endif
 271
 272         /*
 273          * Initialize DMAOR, and clean up any error flags that may have
 274          * been set.
 275          */
 276         i = dmaor_reset();
 277         if (unlikely(i != 0))
 278                 return i;
 279
 280         return register_dmac(info);
 281 }
 282
 283 static void __exit sh_dmac_exit(void)
 284 {
 285 #ifdef CONFIG_CPU_SH4
 286         free_irq(DMAE_IRQ, 0);
 287 #endif
 288         unregister_dmac(&sh_dmac_info);
 289 }
 290
 291 subsys_initcall(sh_dmac_init);
 292 module_exit(sh_dmac_exit);
 293
 294 MODULE_AUTHOR("Takashi YOSHII, Paul Mundt, Andriy Skulysh");
 295 MODULE_DESCRIPTION("SuperH On-Chip DMAC Support");
 296 MODULE_LICENSE("GPL");