arch/sh/drivers/pci/pci-st40.c

   1 /*
   2  * Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
   3  *
   4  * May be copied or modified under the terms of the GNU General Public
   5  * License.  See linux/COPYING for more information.
   6  *
   7  * Support functions for the ST40 PCI hardware.
   8  */
   9
  10 #include <linux/kernel.h>
  11 #include <linux/smp.h>
  12 #include <linux/smp_lock.h>
  13 #include <linux/init.h>
  14 #include <linux/errno.h>
  15 #include <linux/pci.h>
  16 #include <linux/delay.h>
  17 #include <linux/types.h>
  18 #include <asm/pci.h>
  19 #include <linux/irq.h>
  20 #include <linux/interrupt.h>    /* irqreturn_t */
  21
  22 #include "pci-st40.h"
  23
  24 /* This is in P2 of course */
  25 #define ST40PCI_BASE_ADDRESS     (0xb0000000)
  26 #define ST40PCI_MEM_ADDRESS      (ST40PCI_BASE_ADDRESS+0x0)
  27 #define ST40PCI_IO_ADDRESS       (ST40PCI_BASE_ADDRESS+0x06000000)
  28 #define ST40PCI_REG_ADDRESS      (ST40PCI_BASE_ADDRESS+0x07000000)
  29
  30 #define ST40PCI_REG(x) (ST40PCI_REG_ADDRESS+(ST40PCI_##x))
  31 #define ST40PCI_REG_INDEXED(reg, index)                                 \
  32         (ST40PCI_REG(reg##0) +                                  \
  33           ((ST40PCI_REG(reg##1) - ST40PCI_REG(reg##0))*index))
  34
  35 #define ST40PCI_WRITE(reg,val) writel((val),ST40PCI_REG(reg))
  36 #define ST40PCI_WRITE_SHORT(reg,val) writew((val),ST40PCI_REG(reg))
  37 #define ST40PCI_WRITE_BYTE(reg,val) writeb((val),ST40PCI_REG(reg))
  38 #define ST40PCI_WRITE_INDEXED(reg, index, val)                          \
  39          writel((val), ST40PCI_REG_INDEXED(reg, index));
  40
  41 #define ST40PCI_READ(reg) readl(ST40PCI_REG(reg))
  42 #define ST40PCI_READ_SHORT(reg) readw(ST40PCI_REG(reg))
  43 #define ST40PCI_READ_BYTE(reg) readb(ST40PCI_REG(reg))
  44
  45 #define ST40PCI_SERR_IRQ        64
  46 #define ST40PCI_ERR_IRQ         65
  47
  48
  49 /* Macros to extract PLL params */
  50 #define PLL_MDIV(reg)  ( ((unsigned)reg) & 0xff )
  51 #define PLL_NDIV(reg) ( (((unsigned)reg)>>8) & 0xff )
  52 #define PLL_PDIV(reg) ( (((unsigned)reg)>>16) & 0x3 )
  53 #define PLL_SETUP(reg) ( (((unsigned)reg)>>19) & 0x1ff )
  54
  55 /* Build up the appropriate settings */
  56 #define PLL_SET(mdiv,ndiv,pdiv,setup) \
  57 ( ((mdiv)&0xff) | (((ndiv)&0xff)<<8) | (((pdiv)&3)<<16)| (((setup)&0x1ff)<<19))
  58
  59 #define PLLPCICR (0xbb040000+0x10)
  60
  61 #define PLLPCICR_POWERON (1<<28)
  62 #define PLLPCICR_OUT_EN (1<<29)
  63 #define PLLPCICR_LOCKSELECT (1<<30)
  64 #define PLLPCICR_LOCK (1<<31)
  65
  66
  67 #define PLL_25MHZ 0x793c8512
  68 #define PLL_33MHZ PLL_SET(18,88,3,295)
  69
  70 static void pci_set_rbar_region(unsigned int region,     unsigned long localAddr,
  71                          unsigned long pciOffset, unsigned long regionSize);
  72
  73 static __init void SetPCIPLL(void)
  74 {
  75         {
  76                 /* Lets play with the PLL values */
  77                 unsigned long pll1cr1;
  78                 unsigned long mdiv, ndiv, pdiv;
  79                 unsigned long muxcr;
  80                 unsigned int muxcr_ratios[4] = { 8, 16, 21, 1 };
  81                 unsigned int freq;
  82
  83 #define CLKGENA            0xbb040000
  84 #define CLKGENA_PLL2_MUXCR CLKGENA + 0x48
  85                 pll1cr1 = ctrl_inl(PLLPCICR);
  86                 printk("PLL1CR1 %08lx\n", pll1cr1);
  87                 mdiv = PLL_MDIV(pll1cr1);
  88                 ndiv = PLL_NDIV(pll1cr1);
  89                 pdiv = PLL_PDIV(pll1cr1);
  90                 printk("mdiv %02lx ndiv %02lx pdiv %02lx\n", mdiv, ndiv, pdiv);
  91                 freq = ((2*27*ndiv)/mdiv) / (1 << pdiv);
  92                 printk("PLL freq %dMHz\n", freq);
  93                 muxcr = ctrl_inl(CLKGENA_PLL2_MUXCR);
  94                 printk("PCI freq %dMhz\n", freq / muxcr_ratios[muxcr & 3]);
  95         }
  96 }
  97
  98
  99 struct pci_err {
 100   unsigned mask;
 101   const char *error_string;
 102 };
 103
 104 static struct pci_err int_error[]={
 105   { INT_MNLTDIM,"MNLTDIM: Master non-lock transfer"},
 106   { INT_TTADI,  "TTADI: Illegal byte enable in I/O transfer"},
 107   { INT_TMTO,   "TMTO: Target memory read/write timeout"},
 108   { INT_MDEI,   "MDEI: Master function disable error"},
 109   { INT_APEDI,  "APEDI: Address parity error"},
 110   { INT_SDI,    "SDI: SERR detected"},
 111   { INT_DPEITW, "DPEITW: Data parity error target write"},
 112   { INT_PEDITR, "PEDITR: PERR detected"},
 113   { INT_TADIM,  "TADIM: Target abort detected"},
 114   { INT_MADIM,  "MADIM: Master abort detected"},
 115   { INT_MWPDI,  "MWPDI: PERR from target at data write"},
 116   { INT_MRDPEI, "MRDPEI: Master read data parity error"}
 117 };
 118 #define NUM_PCI_INT_ERRS (sizeof(int_error)/sizeof(struct pci_err))
 119
 120 static struct pci_err aint_error[]={
 121   { AINT_MBI,   "MBI: Master broken"},
 122   { AINT_TBTOI, "TBTOI: Target bus timeout"},
 123   { AINT_MBTOI, "MBTOI: Master bus timeout"},
 124   { AINT_TAI,   "TAI: Target abort"},
 125   { AINT_MAI,   "MAI: Master abort"},
 126   { AINT_RDPEI, "RDPEI: Read data parity"},
 127   { AINT_WDPE,  "WDPE: Write data parity"}
 128 };
 129
 130 #define NUM_PCI_AINT_ERRS (sizeof(aint_error)/sizeof(struct pci_err))
 131
 132 static void print_pci_errors(unsigned reg,struct pci_err *error,int num_errors)
 133 {
 134   int i;
 135
 136   for(i=0;i<num_errors;i++) {
 137     if(reg & error[i].mask) {
 138       printk("%s\n",error[i].error_string);
 139     }
 140   }
 141
 142 }
 143
 144
 145 static char * pci_commands[16]={
 146         "Int Ack",
 147         "Special Cycle",
 148         "I/O Read",
 149         "I/O Write",
 150         "Reserved",
 151         "Reserved",
 152         "Memory Read",
 153         "Memory Write",
 154         "Reserved",
 155         "Reserved",
 156         "Configuration Read",
 157         "Configuration Write",
 158         "Memory Read Multiple",
 159         "Dual Address Cycle",
 160         "Memory Read Line",
 161         "Memory Write-and-Invalidate"
 162 };
 163
 164 static irqreturn_t st40_pci_irq(int irq, void *dev_instance)
 165 {
 166         unsigned pci_int, pci_air, pci_cir, pci_aint;
 167         static int count=0;
 168
 169
 170         pci_int = ST40PCI_READ(INT);pci_aint = ST40PCI_READ(AINT);
 171         pci_cir = ST40PCI_READ(CIR);pci_air = ST40PCI_READ(AIR);
 172
 173         /* Reset state to stop multiple interrupts */
 174         ST40PCI_WRITE(INT, ~0); ST40PCI_WRITE(AINT, ~0);
 175
 176
 177         if(++count>1) return IRQ_HANDLED;
 178
 179         printk("** PCI ERROR **\n");
 180
 181         if(pci_int) {
 182                 printk("** INT register status\n");
 183                 print_pci_errors(pci_int,int_error,NUM_PCI_INT_ERRS);
 184         }
 185
 186         if(pci_aint) {
 187                 printk("** AINT register status\n");
 188                 print_pci_errors(pci_aint,aint_error,NUM_PCI_AINT_ERRS);
 189         }
 190
 191         printk("** Address and command info\n");
 192
 193         printk("** Command  %s : Address 0x%x\n",
 194                pci_commands[pci_cir&0xf],pci_air);
 195
 196         if(pci_cir&CIR_PIOTEM) {
 197                 printk("CIR_PIOTEM:PIO transfer error for master\n");
 198         }
 199         if(pci_cir&CIR_RWTET) {
 200                 printk("CIR_RWTET:Read/Write transfer error for target\n");
 201         }
 202
 203         return IRQ_HANDLED;
 204 }
 205
 206
 207 /* Rounds a number UP to the nearest power of two. Used for
 208  * sizing the PCI window.
 209  */
 210 static u32 r2p2(u32 num)
 211 {
 212         int i = 31;
 213         u32 tmp = num;
 214
 215         if (num == 0)
 216                 return 0;
 217
 218         do {
 219                 if (tmp & (1 << 31))
 220                         break;
 221                 i--;
 222                 tmp <<= 1;
 223         } while (i >= 0);
 224
 225         tmp = 1 << i;
 226         /* If the original number isn't a power of 2, round it up */
 227         if (tmp != num)
 228                 tmp <<= 1;
 229
 230         return tmp;
 231 }
 232
 233 static void __init pci_fixup_ide_bases(struct pci_dev *d)
 234 {
 235         int i;
 236
 237         /*
 238          * PCI IDE controllers use non-standard I/O port decoding, respect it.
 239          */
 240         if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
 241                 return;
 242         printk("PCI: IDE base address fixup for %s\n", pci_name(d));
 243         for(i=0; i<4; i++) {
 244                 struct resource *r = &d->resource[i];
 245                 if ((r->start & ~0x80) == 0x374) {
 246                         r->start |= 2;
 247                         r->end = r->start;
 248                 }
 249         }
 250 }
 251 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
 252
 253 int __init st40pci_init(unsigned memStart, unsigned memSize)
 254 {
 255         u32 lsr0;
 256
 257         SetPCIPLL();
 258
 259         /* Initialises the ST40 pci subsystem, performing a reset, then programming
 260          * up the address space decoders appropriately
 261          */
 262
 263         /* Should reset core here as well methink */
 264
 265         ST40PCI_WRITE(CR, CR_LOCK_MASK | CR_SOFT_RESET);
 266
 267         /* Loop while core resets */
 268         while (ST40PCI_READ(CR) & CR_SOFT_RESET);
 269
 270         /* Switch off interrupts */
 271         ST40PCI_WRITE(INTM, 0);
 272         ST40PCI_WRITE(AINT, 0);
 273
 274         /* Now, lets reset all the cards on the bus with extreme prejudice */
 275         ST40PCI_WRITE(CR, CR_LOCK_MASK | CR_RSTCTL);
 276         udelay(250);
 277
 278         /* Set bus active, take it out of reset */
 279         ST40PCI_WRITE(CR, CR_LOCK_MASK | CR_BMAM | CR_CFINT | CR_PFCS | CR_PFE);
 280
 281         /* The PCI spec says that no access must be made to the bus until 1 second
 282          * after reset. This seem ludicrously long, but some delay is needed here
 283          */
 284         mdelay(1000);
 285
 286         /* Switch off interrupts */
 287         ST40PCI_WRITE(INTM, 0);
 288         ST40PCI_WRITE(AINT, 0);
 289
 290         /* Allow it to be a master */
 291
 292         ST40PCI_WRITE_SHORT(CSR_CMD,
 293                             PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
 294                             PCI_COMMAND_IO);
 295
 296         /* Accesse to the 0xb0000000 -> 0xb6000000 area will go through to 0x10000000 -> 0x16000000
 297          * on the PCI bus. This allows a nice 1-1 bus to phys mapping.
 298          */
 299
 300
 301         ST40PCI_WRITE(MBR, 0x10000000);
 302         /* Always set the max size 128M (actually, it is only 96MB wide) */
 303         ST40PCI_WRITE(MBMR, 0x07ff0000);
 304
 305         /* I/O addresses are mapped at 0xb6000000 -> 0xb7000000. These are changed to 0, to
 306          * allow cards that have legacy io such as vga to function correctly. This gives a
 307          * maximum of 64K of io/space as only the bottom 16 bits of the address are copied
 308          * over to the bus  when the transaction is made. 64K of io space is more than enough
 309          */
 310         ST40PCI_WRITE(IOBR, 0x0);
 311         /* Set up the 64K window */
 312         ST40PCI_WRITE(IOBMR, 0x0);
 313
 314         /* Now we set up the mbars so the PCI bus can see the local memory */
 315         /* Expose a 256M window starting at PCI address 0... */
 316         ST40PCI_WRITE(CSR_MBAR0, 0);
 317         ST40PCI_WRITE(LSR0, 0x0fff0001);
 318
 319         /* ... and set up the initial incomming window to expose all of RAM */
 320         pci_set_rbar_region(7, memStart, memStart, memSize);
 321
 322         /* Maximise timeout values */
 323         ST40PCI_WRITE_BYTE(CSR_TRDY, 0xff);
 324         ST40PCI_WRITE_BYTE(CSR_RETRY, 0xff);
 325         ST40PCI_WRITE_BYTE(CSR_MIT, 0xff);
 326
 327         ST40PCI_WRITE_BYTE(PERF,PERF_MASTER_WRITE_POSTING);
 328
 329         return 1;
 330 }
 331
 332 char * __init pcibios_setup(char *str)
 333 {
 334         return str;
 335 }
 336
 337
 338 #define SET_CONFIG_BITS(bus,devfn,where)\
 339   (((bus) << 16) | ((devfn) << 8) | ((where) & ~3) | (bus!=0))
 340
 341 #define CONFIG_CMD(bus, devfn, where) SET_CONFIG_BITS(bus->number,devfn,where)
 342
 343
 344 static int CheckForMasterAbort(void)
 345 {
 346         if (ST40PCI_READ(INT) & INT_MADIM) {
 347                 /* Should we clear config space version as well ??? */
 348                 ST40PCI_WRITE(INT, INT_MADIM);
 349                 ST40PCI_WRITE_SHORT(CSR_STATUS, 0);
 350                 return 1;
 351         }
 352
 353         return 0;
 354 }
 355
 356 /* Write to config register */
 357 static int st40pci_read(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 * val)
 358 {
 359         ST40PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
 360         switch (size) {
 361                 case 1:
 362                         *val = (u8)ST40PCI_READ_BYTE(PDR + (where & 3));
 363                         break;
 364                 case 2:
 365                         *val = (u16)ST40PCI_READ_SHORT(PDR + (where & 2));
 366                         break;
 367                 case 4:
 368                         *val = ST40PCI_READ(PDR);
 369                         break;
 370         }
 371
 372         if (CheckForMasterAbort()){
 373                 switch (size) {
 374                         case 1:
 375                                 *val = (u8)0xff;
 376                                 break;
 377                         case 2:
 378                                 *val = (u16)0xffff;
 379                                 break;
 380                         case 4:
 381                                 *val = 0xffffffff;
 382                                 break;
 383                 }
 384         }
 385
 386         return PCIBIOS_SUCCESSFUL;
 387 }
 388
 389 static int st40pci_write(struct pci_bus *bus, unsigned int devfn, int where, int size, u32 val)
 390 {
 391         ST40PCI_WRITE(PAR, CONFIG_CMD(bus, devfn, where));
 392
 393         switch (size) {
 394                 case 1:
 395                         ST40PCI_WRITE_BYTE(PDR + (where & 3), (u8)val);
 396                         break;
 397                 case 2:
 398                         ST40PCI_WRITE_SHORT(PDR + (where & 2), (u16)val);
 399                         break;
 400                 case 4:
 401                         ST40PCI_WRITE(PDR, val);
 402                         break;
 403         }
 404
 405         CheckForMasterAbort();
 406
 407         return PCIBIOS_SUCCESSFUL;
 408 }
 409
 410 struct pci_ops st40pci_config_ops = {
 411         .read =         st40pci_read,
 412         .write =        st40pci_write,
 413 };
 414
 415
 416 /* Everything hangs off this */
 417 static struct pci_bus *pci_root_bus;
 418
 419 static int __init pcibios_init(void)
 420 {
 421         extern unsigned long memory_start, memory_end;
 422
 423         printk(KERN_ALERT "pci-st40.c: pcibios_init\n");
 424
 425         if (sh_mv.mv_init_pci != NULL) {
 426                 sh_mv.mv_init_pci();
 427         }
 428
 429         /* The pci subsytem needs to know where memory is and how much
 430          * of it there is. I've simply made these globals. A better mechanism
 431          * is probably needed.
 432          */
 433         st40pci_init(PHYSADDR(memory_start),
 434                      PHYSADDR(memory_end) - PHYSADDR(memory_start));
 435
 436         if (request_irq(ST40PCI_ERR_IRQ, st40_pci_irq,
 437                         IRQF_DISABLED, "st40pci", NULL)) {
 438                 printk(KERN_ERR "st40pci: Cannot hook interrupt\n");
 439                 return -EIO;
 440         }
 441
 442         /* Enable the PCI interrupts on the device */
 443         ST40PCI_WRITE(INTM, ~0);
 444         ST40PCI_WRITE(AINT, ~0);
 445
 446         /* Map the io address apprioately */
 447 #ifdef CONFIG_HD64465
 448         hd64465_port_map(PCIBIOS_MIN_IO, (64 * 1024) - PCIBIOS_MIN_IO + 1,
 449                          ST40_IO_ADDR + PCIBIOS_MIN_IO, 0);
 450 #endif
 451
 452         /* ok, do the scan man */
 453         pci_root_bus = pci_scan_bus(0, &st40pci_config_ops, NULL);
 454         pci_assign_unassigned_resources();
 455
 456         return 0;
 457 }
 458 subsys_initcall(pcibios_init);
 459
 460 /*
 461  * Publish a region of local address space over the PCI bus
 462  * to other devices.
 463  */
 464 static void pci_set_rbar_region(unsigned int region,     unsigned long localAddr,
 465                          unsigned long pciOffset, unsigned long regionSize)
 466 {
 467         unsigned long mask;
 468
 469         if (region > 7)
 470                 return;
 471
 472         if (regionSize > (512 * 1024 * 1024))
 473                 return;
 474
 475         mask = r2p2(regionSize) - 0x10000;
 476
 477         /* Diable the region (in case currently in use, should never happen) */
 478         ST40PCI_WRITE_INDEXED(RSR, region, 0);
 479
 480         /* Start of local address space to publish */
 481         ST40PCI_WRITE_INDEXED(RLAR, region, PHYSADDR(localAddr) );
 482
 483         /* Start of region in PCI address space as an offset from MBAR0 */
 484         ST40PCI_WRITE_INDEXED(RBAR, region, pciOffset);
 485
 486         /* Size of region */
 487         ST40PCI_WRITE_INDEXED(RSR, region, mask | 1);
 488 }
 489