arch/sh/include/cpu-sh4/cpu/dma-register.h

   1 /*
   2  * SH4 CPU-specific DMA definitions, used by both DMA drivers
   3  *
   4  * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #ifndef CPU_DMA_REGISTER_H
  11 #define CPU_DMA_REGISTER_H
  12
  13 /* SH7751/7760/7780 DMA IRQ sources */
  14
  15 #ifdef CONFIG_CPU_SH4A
  16
  17 #define DMAOR_INIT      DMAOR_DME
  18
  19 #if defined(CONFIG_CPU_SUBTYPE_SH7343) || \
  20         defined(CONFIG_CPU_SUBTYPE_SH7730)
  21 #define CHCR_TS_LOW_MASK        0x00000018
  22 #define CHCR_TS_LOW_SHIFT       3
  23 #define CHCR_TS_HIGH_MASK       0
  24 #define CHCR_TS_HIGH_SHIFT      0
  25 #elif defined(CONFIG_CPU_SUBTYPE_SH7722) || \
  26         defined(CONFIG_CPU_SUBTYPE_SH7724) || \
  27         defined(CONFIG_CPU_SUBTYPE_SH7786)
  28 #define CHCR_TS_LOW_MASK        0x00000018
  29 #define CHCR_TS_LOW_SHIFT       3
  30 #define CHCR_TS_HIGH_MASK       0x00300000
  31 #define CHCR_TS_HIGH_SHIFT      (20 - 2)        /* 2 bits for shifted low TS */
  32 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
  33         defined(CONFIG_CPU_SUBTYPE_SH7764)
  34 #define CHCR_TS_LOW_MASK        0x00000018
  35 #define CHCR_TS_LOW_SHIFT       3
  36 #define CHCR_TS_HIGH_MASK       0
  37 #define CHCR_TS_HIGH_SHIFT      0
  38 #elif defined(CONFIG_CPU_SUBTYPE_SH7723)
  39 #define CHCR_TS_LOW_MASK        0x00000018
  40 #define CHCR_TS_LOW_SHIFT       3
  41 #define CHCR_TS_HIGH_MASK       0
  42 #define CHCR_TS_HIGH_SHIFT      0
  43 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
  44 #define CHCR_TS_LOW_MASK        0x00000018
  45 #define CHCR_TS_LOW_SHIFT       3
  46 #define CHCR_TS_HIGH_MASK       0
  47 #define CHCR_TS_HIGH_SHIFT      0
  48 #else /* SH7785 */
  49 #define CHCR_TS_LOW_MASK        0x00000018
  50 #define CHCR_TS_LOW_SHIFT       3
  51 #define CHCR_TS_HIGH_MASK       0
  52 #define CHCR_TS_HIGH_SHIFT      0
  53 #endif
  54
  55 /* Transmit sizes and respective CHCR register values */
  56 enum {
  57         XMIT_SZ_8BIT            = 0,
  58         XMIT_SZ_16BIT           = 1,
  59         XMIT_SZ_32BIT           = 2,
  60         XMIT_SZ_64BIT           = 7,
  61         XMIT_SZ_128BIT          = 3,
  62         XMIT_SZ_256BIT          = 4,
  63         XMIT_SZ_128BIT_BLK      = 0xb,
  64         XMIT_SZ_256BIT_BLK      = 0xc,
  65 };
  66
  67 /* log2(size / 8) - used to calculate number of transfers */
  68 #define TS_SHIFT {                      \
  69         [XMIT_SZ_8BIT]          = 0,    \
  70         [XMIT_SZ_16BIT]         = 1,    \
  71         [XMIT_SZ_32BIT]         = 2,    \
  72         [XMIT_SZ_64BIT]         = 3,    \
  73         [XMIT_SZ_128BIT]        = 4,    \
  74         [XMIT_SZ_256BIT]        = 5,    \
  75         [XMIT_SZ_128BIT_BLK]    = 4,    \
  76         [XMIT_SZ_256BIT_BLK]    = 5,    \
  77 }
  78
  79 #define TS_INDEX2VAL(i) ((((i) & 3) << CHCR_TS_LOW_SHIFT) | \
  80                          (((i) & 0xc) << CHCR_TS_HIGH_SHIFT))
  81
  82 #else /* CONFIG_CPU_SH4A */
  83
  84 #define DMAOR_INIT      (0x8000 | DMAOR_DME)
  85
  86 #define CHCR_TS_LOW_MASK        0x70
  87 #define CHCR_TS_LOW_SHIFT       4
  88 #define CHCR_TS_HIGH_MASK       0
  89 #define CHCR_TS_HIGH_SHIFT      0
  90
  91 /* Transmit sizes and respective CHCR register values */
  92 enum {
  93         XMIT_SZ_8BIT    = 1,
  94         XMIT_SZ_16BIT   = 2,
  95         XMIT_SZ_32BIT   = 3,
  96         XMIT_SZ_64BIT   = 0,
  97         XMIT_SZ_256BIT  = 4,
  98 };
  99
 100 /* log2(size / 8) - used to calculate number of transfers */
 101 #define TS_SHIFT {                      \
 102         [XMIT_SZ_8BIT]          = 0,    \
 103         [XMIT_SZ_16BIT]         = 1,    \
 104         [XMIT_SZ_32BIT]         = 2,    \
 105         [XMIT_SZ_64BIT]         = 3,    \
 106         [XMIT_SZ_256BIT]        = 5,    \
 107 }
 108
 109 #define TS_INDEX2VAL(i) (((i) & 7) << CHCR_TS_LOW_SHIFT)
 110
 111 #endif /* CONFIG_CPU_SH4A */
 112
 113 #endif