arch/sh/kernel/cpu/init.c

   1 /*
   2  * arch/sh/kernel/cpu/init.c
   3  *
   4  * CPU init code
   5  *
   6  * Copyright (C) 2002 - 2009  Paul Mundt
   7  * Copyright (C) 2003  Richard Curnow
   8  *
   9  * This file is subject to the terms and conditions of the GNU General Public
  10  * License.  See the file "COPYING" in the main directory of this archive
  11  * for more details.
  12  */
  13 #include <linux/init.h>
  14 #include <linux/kernel.h>
  15 #include <linux/mm.h>
  16 #include <linux/log2.h>
  17 #include <asm/mmu_context.h>
  18 #include <asm/processor.h>
  19 #include <asm/uaccess.h>
  20 #include <asm/page.h>
  21 #include <asm/system.h>
  22 #include <asm/cacheflush.h>
  23 #include <asm/cache.h>
  24 #include <asm/elf.h>
  25 #include <asm/io.h>
  26 #include <asm/smp.h>
  27 #ifdef CONFIG_SUPERH32
  28 #include <asm/ubc.h>
  29 #endif
  30
  31 /*
  32  * Generic wrapper for command line arguments to disable on-chip
  33  * peripherals (nofpu, nodsp, and so forth).
  34  */
  35 #define onchip_setup(x)                         \
  36 static int x##_disabled __initdata = 0;         \
  37                                                 \
  38 static int __init x##_setup(char *opts)         \
  39 {                                               \
  40         x##_disabled = 1;                       \
  41         return 1;                               \
  42 }                                               \
  43 __setup("no" __stringify(x), x##_setup);
  44
  45 onchip_setup(fpu);
  46 onchip_setup(dsp);
  47
  48 #ifdef CONFIG_SPECULATIVE_EXECUTION
  49 #define CPUOPM          0xff2f0000
  50 #define CPUOPM_RABD     (1 << 5)
  51
  52 static void __init speculative_execution_init(void)
  53 {
  54         /* Clear RABD */
  55         ctrl_outl(ctrl_inl(CPUOPM) & ~CPUOPM_RABD, CPUOPM);
  56
  57         /* Flush the update */
  58         (void)ctrl_inl(CPUOPM);
  59         ctrl_barrier();
  60 }
  61 #else
  62 #define speculative_execution_init()    do { } while (0)
  63 #endif
  64
  65 #ifdef CONFIG_CPU_SH4A
  66 #define EXPMASK                 0xff2f0004
  67 #define EXPMASK_RTEDS           (1 << 0)
  68 #define EXPMASK_BRDSSLP         (1 << 1)
  69 #define EXPMASK_MMCAW           (1 << 4)
  70
  71 static void __init expmask_init(void)
  72 {
  73         unsigned long expmask = __raw_readl(EXPMASK);
  74
  75         /*
  76          * Future proofing.
  77          *
  78          * Disable support for slottable sleep instruction
  79          * and non-nop instructions in the rte delay slot.
  80          */
  81         expmask &= ~(EXPMASK_RTEDS | EXPMASK_BRDSSLP);
  82
  83         /*
  84          * Enable associative writes to the memory-mapped cache array
  85          * until the cache flush ops have been rewritten.
  86          */
  87         expmask |= EXPMASK_MMCAW;
  88
  89         __raw_writel(expmask, EXPMASK);
  90         ctrl_barrier();
  91 }
  92 #else
  93 #define expmask_init()  do { } while (0)
  94 #endif
  95
  96 /* 2nd-level cache init */
  97 void __uses_jump_to_uncached __attribute__ ((weak)) l2_cache_init(void)
  98 {
  99 }
 100
 101 /*
 102  * Generic first-level cache init
 103  */
 104 #ifdef CONFIG_SUPERH32
 105 static void __uses_jump_to_uncached cache_init(void)
 106 {
 107         unsigned long ccr, flags;
 108
 109         jump_to_uncached();
 110         ccr = ctrl_inl(CCR);
 111
 112         /*
 113          * At this point we don't know whether the cache is enabled or not - a
 114          * bootloader may have enabled it.  There are at least 2 things that
 115          * could be dirty in the cache at this point:
 116          * 1. kernel command line set up by boot loader
 117          * 2. spilled registers from the prolog of this function
 118          * => before re-initialising the cache, we must do a purge of the whole
 119          * cache out to memory for safety.  As long as nothing is spilled
 120          * during the loop to lines that have already been done, this is safe.
 121          * - RPC
 122          */
 123         if (ccr & CCR_CACHE_ENABLE) {
 124                 unsigned long ways, waysize, addrstart;
 125
 126                 waysize = current_cpu_data.dcache.sets;
 127
 128 #ifdef CCR_CACHE_ORA
 129                 /*
 130                  * If the OC is already in RAM mode, we only have
 131                  * half of the entries to flush..
 132                  */
 133                 if (ccr & CCR_CACHE_ORA)
 134                         waysize >>= 1;
 135 #endif
 136
 137                 waysize <<= current_cpu_data.dcache.entry_shift;
 138
 139 #ifdef CCR_CACHE_EMODE
 140                 /* If EMODE is not set, we only have 1 way to flush. */
 141                 if (!(ccr & CCR_CACHE_EMODE))
 142                         ways = 1;
 143                 else
 144 #endif
 145                         ways = current_cpu_data.dcache.ways;
 146
 147                 addrstart = CACHE_OC_ADDRESS_ARRAY;
 148                 do {
 149                         unsigned long addr;
 150
 151                         for (addr = addrstart;
 152                              addr < addrstart + waysize;
 153                              addr += current_cpu_data.dcache.linesz)
 154                                 ctrl_outl(0, addr);
 155
 156                         addrstart += current_cpu_data.dcache.way_incr;
 157                 } while (--ways);
 158         }
 159
 160         /*
 161          * Default CCR values .. enable the caches
 162          * and invalidate them immediately..
 163          */
 164         flags = CCR_CACHE_ENABLE | CCR_CACHE_INVALIDATE;
 165
 166 #ifdef CCR_CACHE_EMODE
 167         /* Force EMODE if possible */
 168         if (current_cpu_data.dcache.ways > 1)
 169                 flags |= CCR_CACHE_EMODE;
 170         else
 171                 flags &= ~CCR_CACHE_EMODE;
 172 #endif
 173
 174 #if defined(CONFIG_CACHE_WRITETHROUGH)
 175         /* Write-through */
 176         flags |= CCR_CACHE_WT;
 177 #elif defined(CONFIG_CACHE_WRITEBACK)
 178         /* Write-back */
 179         flags |= CCR_CACHE_CB;
 180 #else
 181         /* Off */
 182         flags &= ~CCR_CACHE_ENABLE;
 183 #endif
 184
 185         l2_cache_init();
 186
 187         ctrl_outl(flags, CCR);
 188         back_to_cached();
 189 }
 190 #else
 191 #define cache_init()    do { } while (0)
 192 #endif
 193
 194 #define CSHAPE(totalsize, linesize, assoc) \
 195         ((totalsize & ~0xff) | (linesize << 4) | assoc)
 196
 197 #define CACHE_DESC_SHAPE(desc)  \
 198         CSHAPE((desc).way_size * (desc).ways, ilog2((desc).linesz), (desc).ways)
 199
 200 static void detect_cache_shape(void)
 201 {
 202         l1d_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.dcache);
 203
 204         if (current_cpu_data.dcache.flags & SH_CACHE_COMBINED)
 205                 l1i_cache_shape = l1d_cache_shape;
 206         else
 207                 l1i_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.icache);
 208
 209         if (current_cpu_data.flags & CPU_HAS_L2_CACHE)
 210                 l2_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.scache);
 211         else
 212                 l2_cache_shape = -1; /* No S-cache */
 213 }
 214
 215 #ifdef CONFIG_SH_DSP
 216 static void __init release_dsp(void)
 217 {
 218         unsigned long sr;
 219
 220         /* Clear SR.DSP bit */
 221         __asm__ __volatile__ (
 222                 "stc\tsr, %0\n\t"
 223                 "and\t%1, %0\n\t"
 224                 "ldc\t%0, sr\n\t"
 225                 : "=&r" (sr)
 226                 : "r" (~SR_DSP)
 227         );
 228 }
 229
 230 static void __init dsp_init(void)
 231 {
 232         unsigned long sr;
 233
 234         /*
 235          * Set the SR.DSP bit, wait for one instruction, and then read
 236          * back the SR value.
 237          */
 238         __asm__ __volatile__ (
 239                 "stc\tsr, %0\n\t"
 240                 "or\t%1, %0\n\t"
 241                 "ldc\t%0, sr\n\t"
 242                 "nop\n\t"
 243                 "stc\tsr, %0\n\t"
 244                 : "=&r" (sr)
 245                 : "r" (SR_DSP)
 246         );
 247
 248         /* If the DSP bit is still set, this CPU has a DSP */
 249         if (sr & SR_DSP)
 250                 current_cpu_data.flags |= CPU_HAS_DSP;
 251
 252         /* Now that we've determined the DSP status, clear the DSP bit. */
 253         release_dsp();
 254 }
 255 #endif /* CONFIG_SH_DSP */
 256
 257 /**
 258  * sh_cpu_init
 259  *
 260  * This is our initial entry point for each CPU, and is invoked on the boot
 261  * CPU prior to calling start_kernel(). For SMP, a combination of this and
 262  * start_secondary() will bring up each processor to a ready state prior
 263  * to hand forking the idle loop.
 264  *
 265  * We do all of the basic processor init here, including setting up the
 266  * caches, FPU, DSP, kicking the UBC, etc. By the time start_kernel() is
 267  * hit (and subsequently platform_setup()) things like determining the
 268  * CPU subtype and initial configuration will all be done.
 269  *
 270  * Each processor family is still responsible for doing its own probing
 271  * and cache configuration in detect_cpu_and_cache_system().
 272  */
 273
 274 asmlinkage void __init sh_cpu_init(void)
 275 {
 276         current_thread_info()->cpu = hard_smp_processor_id();
 277
 278         /* First, probe the CPU */
 279         detect_cpu_and_cache_system();
 280
 281         if (current_cpu_data.type == CPU_SH_NONE)
 282                 panic("Unknown CPU");
 283
 284         /* First setup the rest of the I-cache info */
 285         current_cpu_data.icache.entry_mask = current_cpu_data.icache.way_incr -
 286                                       current_cpu_data.icache.linesz;
 287
 288         current_cpu_data.icache.way_size = current_cpu_data.icache.sets *
 289                                     current_cpu_data.icache.linesz;
 290
 291         /* And the D-cache too */
 292         current_cpu_data.dcache.entry_mask = current_cpu_data.dcache.way_incr -
 293                                       current_cpu_data.dcache.linesz;
 294
 295         current_cpu_data.dcache.way_size = current_cpu_data.dcache.sets *
 296                                     current_cpu_data.dcache.linesz;
 297
 298         /* Init the cache */
 299         cache_init();
 300
 301         if (raw_smp_processor_id() == 0) {
 302                 shm_align_mask = max_t(unsigned long,
 303                                        current_cpu_data.dcache.way_size - 1,
 304                                        PAGE_SIZE - 1);
 305
 306                 /* Boot CPU sets the cache shape */
 307                 detect_cache_shape();
 308         }
 309
 310         /* Disable the FPU */
 311         if (fpu_disabled) {
 312                 printk("FPU Disabled\n");
 313                 current_cpu_data.flags &= ~CPU_HAS_FPU;
 314                 disable_fpu();
 315         }
 316
 317         /* FPU initialization */
 318         if ((current_cpu_data.flags & CPU_HAS_FPU)) {
 319                 clear_thread_flag(TIF_USEDFPU);
 320                 clear_used_math();
 321         }
 322
 323         /*
 324          * Initialize the per-CPU ASID cache very early, since the
 325          * TLB flushing routines depend on this being setup.
 326          */
 327         current_cpu_data.asid_cache = NO_CONTEXT;
 328
 329 #ifdef CONFIG_SH_DSP
 330         /* Probe for DSP */
 331         dsp_init();
 332
 333         /* Disable the DSP */
 334         if (dsp_disabled) {
 335                 printk("DSP Disabled\n");
 336                 current_cpu_data.flags &= ~CPU_HAS_DSP;
 337                 release_dsp();
 338         }
 339 #endif
 340
 341         /*
 342          * Some brain-damaged loaders decided it would be a good idea to put
 343          * the UBC to sleep. This causes some issues when it comes to things
 344          * like PTRACE_SINGLESTEP or doing hardware watchpoints in GDB.  So ..
 345          * we wake it up and hope that all is well.
 346          */
 347 #ifdef CONFIG_SUPERH32
 348         if (raw_smp_processor_id() == 0)
 349                 ubc_wakeup();
 350 #endif
 351
 352         speculative_execution_init();
 353         expmask_init();
 354 }