arch/sh/kernel/cpu/sh4a/clock-sh7757.c

   1 /*
   2  * arch/sh/kernel/cpu/sh4/clock-sh7757.c
   3  *
   4  * SH7757 support for the clock framework
   5  *
   6  *  Copyright (C) 2009-2010  Renesas Solutions Corp.
   7  *
   8  * This file is subject to the terms and conditions of the GNU General Public
   9  * License.  See the file "COPYING" in the main directory of this archive
  10  * for more details.
  11  */
  12 #include <linux/init.h>
  13 #include <linux/kernel.h>
  14 #include <linux/io.h>
  15 #include <linux/clkdev.h>
  16 #include <asm/clock.h>
  17 #include <asm/freq.h>
  18
  19 /*
  20  * Default rate for the root input clock, reset this with clk_set_rate()
  21  * from the platform code.
  22  */
  23 static struct clk extal_clk = {
  24         .rate           = 48000000,
  25 };
  26
  27 static unsigned long pll_recalc(struct clk *clk)
  28 {
  29         int multiplier;
  30
  31         multiplier = test_mode_pin(MODE_PIN0) ? 24 : 16;
  32
  33         return clk->parent->rate * multiplier;
  34 }
  35
  36 static struct clk_ops pll_clk_ops = {
  37         .recalc         = pll_recalc,
  38 };
  39
  40 static struct clk pll_clk = {
  41         .ops            = &pll_clk_ops,
  42         .parent         = &extal_clk,
  43         .flags          = CLK_ENABLE_ON_INIT,
  44 };
  45
  46 static struct clk *clks[] = {
  47         &extal_clk,
  48         &pll_clk,
  49 };
  50
  51 static unsigned int div2[] = { 1, 1, 2, 1, 1, 4, 1, 6,
  52                                1, 1, 1, 16, 1, 24, 1, 1 };
  53
  54 static struct clk_div_mult_table div4_div_mult_table = {
  55         .divisors = div2,
  56         .nr_divisors = ARRAY_SIZE(div2),
  57 };
  58
  59 static struct clk_div4_table div4_table = {
  60         .div_mult_table = &div4_div_mult_table,
  61 };
  62
  63 enum { DIV4_I, DIV4_SH, DIV4_P, DIV4_NR };
  64
  65 #define DIV4(_bit, _mask, _flags) \
  66   SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags)
  67
  68 struct clk div4_clks[DIV4_NR] = {
  69         /*
  70          * P clock is always enable, because some P clock modules is used
  71          * by Host PC.
  72          */
  73         [DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT),
  74         [DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT),
  75         [DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT),
  76 };
  77
  78 #define MSTPCR0         0xffc80030
  79 #define MSTPCR1         0xffc80034
  80
  81 enum { MSTP004, MSTP000, MSTP114, MSTP113, MSTP112,
  82        MSTP111, MSTP110, MSTP103, MSTP102,
  83        MSTP_NR };
  84
  85 static struct clk mstp_clks[MSTP_NR] = {
  86         /* MSTPCR0 */
  87         [MSTP004] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 4, 0),
  88         [MSTP000] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 0, 0),
  89
  90         /* MSTPCR1 */
  91         [MSTP114] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 14, 0),
  92         [MSTP113] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 13, 0),
  93         [MSTP112] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 12, 0),
  94         [MSTP111] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 11, 0),
  95         [MSTP110] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 10, 0),
  96         [MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 3, 0),
  97         [MSTP102] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 2, 0),
  98 };
  99
 100 #define CLKDEV_CON_ID(_id, _clk) { .con_id = _id, .clk = _clk }
 101
 102 static struct clk_lookup lookups[] = {
 103         /* main clocks */
 104         CLKDEV_CON_ID("extal", &extal_clk),
 105         CLKDEV_CON_ID("pll_clk", &pll_clk),
 106
 107         /* DIV4 clocks */
 108         CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
 109         CLKDEV_CON_ID("shyway_clk", &div4_clks[DIV4_SH]),
 110         CLKDEV_CON_ID("cpu_clk", &div4_clks[DIV4_I]),
 111
 112         /* MSTP32 clocks */
 113         CLKDEV_CON_ID("sdhi0", &mstp_clks[MSTP004]),
 114         CLKDEV_CON_ID("riic", &mstp_clks[MSTP000]),
 115         {
 116                 /* TMU0 */
 117                 .dev_id         = "sh_tmu.0",
 118                 .con_id         = "tmu_fck",
 119                 .clk            = &mstp_clks[MSTP113],
 120         }, {
 121                 /* TMU1 */
 122                 .dev_id         = "sh_tmu.1",
 123                 .con_id         = "tmu_fck",
 124                 .clk            = &mstp_clks[MSTP114],
 125         },
 126         {
 127                 /* SCIF4 (But, ID is 2) */
 128                 .dev_id         = "sh-sci.2",
 129                 .con_id         = "sci_fck",
 130                 .clk            = &mstp_clks[MSTP112],
 131         }, {
 132                 /* SCIF3 */
 133                 .dev_id         = "sh-sci.1",
 134                 .con_id         = "sci_fck",
 135                 .clk            = &mstp_clks[MSTP111],
 136         }, {
 137                 /* SCIF2 */
 138                 .dev_id         = "sh-sci.0",
 139                 .con_id         = "sci_fck",
 140                 .clk            = &mstp_clks[MSTP110],
 141         },
 142         CLKDEV_CON_ID("usb0", &mstp_clks[MSTP102]),
 143 };
 144
 145 int __init arch_clk_init(void)
 146 {
 147         int i, ret = 0;
 148
 149         for (i = 0; i < ARRAY_SIZE(clks); i++)
 150                 ret |= clk_register(clks[i]);
 151         for (i = 0; i < ARRAY_SIZE(lookups); i++)
 152                 clkdev_add(&lookups[i]);
 153
 154         if (!ret)
 155                 ret = sh_clk_div4_register(div4_clks, ARRAY_SIZE(div4_clks),
 156                                            &div4_table);
 157         if (!ret)
 158                 ret = sh_clk_mstp32_register(mstp_clks, MSTP_NR);
 159
 160         return ret;
 161 }
 162