4 * Copyright (C) 2006 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/serial_sci.h>
14 #include <linux/uio_driver.h>
15 #include <linux/sh_timer.h>
16 #include <linux/sh_intc.h>
17 #include <asm/clock.h>
20 static struct plat_sci_port scif0_platform_data
= {
21 .flags
= UPF_BOOT_AUTOCONF
,
22 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_CKE1
,
26 static struct resource scif0_resources
[] = {
27 DEFINE_RES_MEM(0xffe00000, 0x100),
28 DEFINE_RES_IRQ(evt2irq(0xc00)),
31 static struct platform_device scif0_device
= {
34 .resource
= scif0_resources
,
35 .num_resources
= ARRAY_SIZE(scif0_resources
),
37 .platform_data
= &scif0_platform_data
,
41 static struct plat_sci_port scif1_platform_data
= {
42 .flags
= UPF_BOOT_AUTOCONF
,
43 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_CKE1
,
47 static struct resource scif1_resources
[] = {
48 DEFINE_RES_MEM(0xffe10000, 0x100),
49 DEFINE_RES_IRQ(evt2irq(0xc20)),
52 static struct platform_device scif1_device
= {
55 .resource
= scif1_resources
,
56 .num_resources
= ARRAY_SIZE(scif1_resources
),
58 .platform_data
= &scif1_platform_data
,
62 static struct plat_sci_port scif2_platform_data
= {
63 .flags
= UPF_BOOT_AUTOCONF
,
64 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_CKE1
,
68 static struct resource scif2_resources
[] = {
69 DEFINE_RES_MEM(0xffe20000, 0x100),
70 DEFINE_RES_IRQ(evt2irq(0xc40)),
73 static struct platform_device scif2_device
= {
76 .resource
= scif2_resources
,
77 .num_resources
= ARRAY_SIZE(scif2_resources
),
79 .platform_data
= &scif2_platform_data
,
83 static struct plat_sci_port scif3_platform_data
= {
84 .flags
= UPF_BOOT_AUTOCONF
,
85 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_CKE1
,
89 static struct resource scif3_resources
[] = {
90 DEFINE_RES_MEM(0xffe30000, 0x100),
91 DEFINE_RES_IRQ(evt2irq(0xc60)),
94 static struct platform_device scif3_device
= {
97 .resource
= scif3_resources
,
98 .num_resources
= ARRAY_SIZE(scif3_resources
),
100 .platform_data
= &scif3_platform_data
,
104 static struct resource iic0_resources
[] = {
109 .flags
= IORESOURCE_MEM
,
112 .start
= evt2irq(0xe00),
113 .end
= evt2irq(0xe60),
114 .flags
= IORESOURCE_IRQ
,
118 static struct platform_device iic0_device
= {
119 .name
= "i2c-sh_mobile",
120 .id
= 0, /* "i2c0" clock */
121 .num_resources
= ARRAY_SIZE(iic0_resources
),
122 .resource
= iic0_resources
,
125 static struct resource iic1_resources
[] = {
130 .flags
= IORESOURCE_MEM
,
133 .start
= evt2irq(0x780),
134 .end
= evt2irq(0x7e0),
135 .flags
= IORESOURCE_IRQ
,
139 static struct platform_device iic1_device
= {
140 .name
= "i2c-sh_mobile",
141 .id
= 1, /* "i2c1" clock */
142 .num_resources
= ARRAY_SIZE(iic1_resources
),
143 .resource
= iic1_resources
,
146 static struct uio_info vpu_platform_data
= {
149 .irq
= evt2irq(0x980),
152 static struct resource vpu_resources
[] = {
157 .flags
= IORESOURCE_MEM
,
160 /* place holder for contiguous memory */
164 static struct platform_device vpu_device
= {
165 .name
= "uio_pdrv_genirq",
168 .platform_data
= &vpu_platform_data
,
170 .resource
= vpu_resources
,
171 .num_resources
= ARRAY_SIZE(vpu_resources
),
174 static struct uio_info veu_platform_data
= {
177 .irq
= evt2irq(0x8c0),
180 static struct resource veu_resources
[] = {
185 .flags
= IORESOURCE_MEM
,
188 /* place holder for contiguous memory */
192 static struct platform_device veu_device
= {
193 .name
= "uio_pdrv_genirq",
196 .platform_data
= &veu_platform_data
,
198 .resource
= veu_resources
,
199 .num_resources
= ARRAY_SIZE(veu_resources
),
202 static struct uio_info jpu_platform_data
= {
205 .irq
= evt2irq(0x560),
208 static struct resource jpu_resources
[] = {
213 .flags
= IORESOURCE_MEM
,
216 /* place holder for contiguous memory */
220 static struct platform_device jpu_device
= {
221 .name
= "uio_pdrv_genirq",
224 .platform_data
= &jpu_platform_data
,
226 .resource
= jpu_resources
,
227 .num_resources
= ARRAY_SIZE(jpu_resources
),
230 static struct sh_timer_config cmt_platform_data
= {
231 .channel_offset
= 0x60,
233 .clockevent_rating
= 125,
234 .clocksource_rating
= 200,
237 static struct resource cmt_resources
[] = {
241 .flags
= IORESOURCE_MEM
,
244 .start
= evt2irq(0xf00),
245 .flags
= IORESOURCE_IRQ
,
249 static struct platform_device cmt_device
= {
253 .platform_data
= &cmt_platform_data
,
255 .resource
= cmt_resources
,
256 .num_resources
= ARRAY_SIZE(cmt_resources
),
259 static struct sh_timer_config tmu0_platform_data
= {
260 .channel_offset
= 0x04,
262 .clockevent_rating
= 200,
265 static struct resource tmu0_resources
[] = {
269 .flags
= IORESOURCE_MEM
,
272 .start
= evt2irq(0x400),
273 .flags
= IORESOURCE_IRQ
,
277 static struct platform_device tmu0_device
= {
281 .platform_data
= &tmu0_platform_data
,
283 .resource
= tmu0_resources
,
284 .num_resources
= ARRAY_SIZE(tmu0_resources
),
287 static struct sh_timer_config tmu1_platform_data
= {
288 .channel_offset
= 0x10,
290 .clocksource_rating
= 200,
293 static struct resource tmu1_resources
[] = {
297 .flags
= IORESOURCE_MEM
,
300 .start
= evt2irq(0x420),
301 .flags
= IORESOURCE_IRQ
,
305 static struct platform_device tmu1_device
= {
309 .platform_data
= &tmu1_platform_data
,
311 .resource
= tmu1_resources
,
312 .num_resources
= ARRAY_SIZE(tmu1_resources
),
315 static struct sh_timer_config tmu2_platform_data
= {
316 .channel_offset
= 0x1c,
320 static struct resource tmu2_resources
[] = {
324 .flags
= IORESOURCE_MEM
,
327 .start
= evt2irq(0x440),
328 .flags
= IORESOURCE_IRQ
,
332 static struct platform_device tmu2_device
= {
336 .platform_data
= &tmu2_platform_data
,
338 .resource
= tmu2_resources
,
339 .num_resources
= ARRAY_SIZE(tmu2_resources
),
342 static struct platform_device
*sh7343_devices
[] __initdata
= {
358 static int __init
sh7343_devices_setup(void)
360 platform_resource_setup_memory(&vpu_device
, "vpu", 1 << 20);
361 platform_resource_setup_memory(&veu_device
, "veu", 2 << 20);
362 platform_resource_setup_memory(&jpu_device
, "jpu", 2 << 20);
364 return platform_add_devices(sh7343_devices
,
365 ARRAY_SIZE(sh7343_devices
));
367 arch_initcall(sh7343_devices_setup
);
369 static struct platform_device
*sh7343_early_devices
[] __initdata
= {
380 void __init
plat_early_device_setup(void)
382 early_platform_add_devices(sh7343_early_devices
,
383 ARRAY_SIZE(sh7343_early_devices
));
391 /* interrupt sources */
392 IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
,
393 DMAC0
, DMAC1
, DMAC2
, DMAC3
,
394 VIO_CEUI
, VIO_BEUI
, VIO_VEUI
, VOU
,
395 MFI
, VPU
, TPU
, Z3D4
, USBI0
, USBI1
,
396 MMC_ERR
, MMC_TRAN
, MMC_FSTAT
, MMC_FRDY
,
397 DMAC4
, DMAC5
, DMAC_DADERR
,
399 SCIF
, SCIF1
, SCIF2
, SCIF3
,
401 FLCTL_FLSTEI
, FLCTL_FLENDI
, FLCTL_FLTREQ0I
, FLCTL_FLTREQ1I
,
402 I2C0_ALI
, I2C0_TACKI
, I2C0_WAITI
, I2C0_DTEI
,
403 I2C1_ALI
, I2C1_TACKI
, I2C1_WAITI
, I2C1_DTEI
,
404 SIM_TEI
, SIM_TXI
, SIM_RXI
, SIM_ERI
,
405 IRDA
, SDHI
, CMT
, TSIF
, SIU
,
409 /* interrupt groups */
411 DMAC0123
, VIOVOU
, MMC
, DMAC45
, FLCTL
, I2C0
, I2C1
, SIM
, USB
,
414 static struct intc_vect vectors
[] __initdata
= {
415 INTC_VECT(IRQ0
, 0x600), INTC_VECT(IRQ1
, 0x620),
416 INTC_VECT(IRQ2
, 0x640), INTC_VECT(IRQ3
, 0x660),
417 INTC_VECT(IRQ4
, 0x680), INTC_VECT(IRQ5
, 0x6a0),
418 INTC_VECT(IRQ6
, 0x6c0), INTC_VECT(IRQ7
, 0x6e0),
419 INTC_VECT(I2C1_ALI
, 0x780), INTC_VECT(I2C1_TACKI
, 0x7a0),
420 INTC_VECT(I2C1_WAITI
, 0x7c0), INTC_VECT(I2C1_DTEI
, 0x7e0),
421 INTC_VECT(DMAC0
, 0x800), INTC_VECT(DMAC1
, 0x820),
422 INTC_VECT(DMAC2
, 0x840), INTC_VECT(DMAC3
, 0x860),
423 INTC_VECT(VIO_CEUI
, 0x880), INTC_VECT(VIO_BEUI
, 0x8a0),
424 INTC_VECT(VIO_VEUI
, 0x8c0), INTC_VECT(VOU
, 0x8e0),
425 INTC_VECT(MFI
, 0x900), INTC_VECT(VPU
, 0x980),
426 INTC_VECT(TPU
, 0x9a0), INTC_VECT(Z3D4
, 0x9e0),
427 INTC_VECT(USBI0
, 0xa20), INTC_VECT(USBI1
, 0xa40),
428 INTC_VECT(MMC_ERR
, 0xb00), INTC_VECT(MMC_TRAN
, 0xb20),
429 INTC_VECT(MMC_FSTAT
, 0xb40), INTC_VECT(MMC_FRDY
, 0xb60),
430 INTC_VECT(DMAC4
, 0xb80), INTC_VECT(DMAC5
, 0xba0),
431 INTC_VECT(DMAC_DADERR
, 0xbc0), INTC_VECT(KEYSC
, 0xbe0),
432 INTC_VECT(SCIF
, 0xc00), INTC_VECT(SCIF1
, 0xc20),
433 INTC_VECT(SCIF2
, 0xc40), INTC_VECT(SCIF3
, 0xc60),
434 INTC_VECT(SIOF0
, 0xc80), INTC_VECT(SIOF1
, 0xca0),
435 INTC_VECT(SIO
, 0xd00),
436 INTC_VECT(FLCTL_FLSTEI
, 0xd80), INTC_VECT(FLCTL_FLENDI
, 0xda0),
437 INTC_VECT(FLCTL_FLTREQ0I
, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I
, 0xde0),
438 INTC_VECT(I2C0_ALI
, 0xe00), INTC_VECT(I2C0_TACKI
, 0xe20),
439 INTC_VECT(I2C0_WAITI
, 0xe40), INTC_VECT(I2C0_DTEI
, 0xe60),
440 INTC_VECT(SDHI
, 0xe80), INTC_VECT(SDHI
, 0xea0),
441 INTC_VECT(SDHI
, 0xec0), INTC_VECT(SDHI
, 0xee0),
442 INTC_VECT(CMT
, 0xf00), INTC_VECT(TSIF
, 0xf20),
443 INTC_VECT(SIU
, 0xf80),
444 INTC_VECT(TMU0
, 0x400), INTC_VECT(TMU1
, 0x420),
445 INTC_VECT(TMU2
, 0x440),
446 INTC_VECT(JPU
, 0x560), INTC_VECT(LCDC
, 0x580),
449 static struct intc_group groups
[] __initdata
= {
450 INTC_GROUP(DMAC0123
, DMAC0
, DMAC1
, DMAC2
, DMAC3
),
451 INTC_GROUP(VIOVOU
, VIO_CEUI
, VIO_BEUI
, VIO_VEUI
, VOU
),
452 INTC_GROUP(MMC
, MMC_FRDY
, MMC_FSTAT
, MMC_TRAN
, MMC_ERR
),
453 INTC_GROUP(DMAC45
, DMAC4
, DMAC5
, DMAC_DADERR
),
454 INTC_GROUP(FLCTL
, FLCTL_FLSTEI
, FLCTL_FLENDI
,
455 FLCTL_FLTREQ0I
, FLCTL_FLTREQ1I
),
456 INTC_GROUP(I2C0
, I2C0_ALI
, I2C0_TACKI
, I2C0_WAITI
, I2C0_DTEI
),
457 INTC_GROUP(I2C1
, I2C1_ALI
, I2C1_TACKI
, I2C1_WAITI
, I2C1_DTEI
),
458 INTC_GROUP(SIM
, SIM_TEI
, SIM_TXI
, SIM_RXI
, SIM_ERI
),
459 INTC_GROUP(USB
, USBI0
, USBI1
),
462 static struct intc_mask_reg mask_registers
[] __initdata
= {
463 { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
464 { VOU
, VIO_VEUI
, VIO_BEUI
, VIO_CEUI
, DMAC3
, DMAC2
, DMAC1
, DMAC0
} },
465 { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
466 { 0, 0, 0, VPU
, 0, 0, 0, MFI
} },
467 { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
468 { SIM_TEI
, SIM_TXI
, SIM_RXI
, SIM_ERI
, 0, 0, 0, IRDA
} },
469 { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
470 { 0, TMU2
, TMU1
, TMU0
, JPU
, 0, 0, LCDC
} },
471 { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
472 { KEYSC
, DMAC_DADERR
, DMAC5
, DMAC4
, SCIF3
, SCIF2
, SCIF1
, SCIF
} },
473 { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
474 { 0, 0, 0, SIO
, Z3D4
, 0, SIOF1
, SIOF0
} },
475 { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
476 { I2C0_DTEI
, I2C0_WAITI
, I2C0_TACKI
, I2C0_ALI
,
477 FLCTL_FLTREQ1I
, FLCTL_FLTREQ0I
, FLCTL_FLENDI
, FLCTL_FLSTEI
} },
478 { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
479 { DISABLED
, ENABLED
, ENABLED
, ENABLED
, 0, 0, 0, SIU
} },
480 { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
481 { 0, 0, 0, CMT
, 0, USBI1
, USBI0
} },
482 { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
483 { MMC_FRDY
, MMC_FSTAT
, MMC_TRAN
, MMC_ERR
} },
484 { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
485 { I2C1_DTEI
, I2C1_WAITI
, I2C1_TACKI
, I2C1_ALI
, TPU
, 0, 0, TSIF
} },
486 { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
487 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
490 static struct intc_prio_reg prio_registers
[] __initdata
= {
491 { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0
, TMU1
, TMU2
} },
492 { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU
, LCDC
, SIM
} },
493 { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123
, VIOVOU
, MFI
, VPU
} },
494 { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC
, DMAC45
, USB
, CMT
} },
495 { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF
, SCIF1
, SCIF2
, SCIF3
} },
496 { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0
, SIOF1
, FLCTL
, I2C0
} },
497 { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO
, 0, TSIF
, I2C1
} },
498 { 0xa4080024, 0, 16, 4, /* IPRJ */ { Z3D4
, 0, SIU
} },
499 { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC
, 0, SDHI
} },
500 { 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU
} },
501 { 0xa4140010, 0, 32, 4, /* INTPRI00 */
502 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
505 static struct intc_sense_reg sense_registers
[] __initdata
= {
506 { 0xa414001c, 16, 2, /* ICR1 */
507 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
510 static struct intc_mask_reg ack_registers
[] __initdata
= {
511 { 0xa4140024, 0, 8, /* INTREQ00 */
512 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
515 static struct intc_desc intc_desc __initdata
= {
517 .force_enable
= ENABLED
,
518 .force_disable
= DISABLED
,
519 .hw
= INTC_HW_DESC(vectors
, groups
, mask_registers
,
520 prio_registers
, sense_registers
, ack_registers
),
523 void __init
plat_irq_setup(void)
525 register_intc_controller(&intc_desc
);