arch/sh/kernel/cpu/sh4a/setup-sh7343.c

   1 /*
   2  * SH7343 Setup
   3  *
   4  *  Copyright (C) 2006  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/serial_sci.h>
  14 #include <linux/uio_driver.h>
  15 #include <linux/sh_timer.h>
  16 #include <linux/sh_intc.h>
  17 #include <asm/clock.h>
  18
  19 /* Serial */
  20 static struct plat_sci_port scif0_platform_data = {
  21         .mapbase        = 0xffe00000,
  22         .flags          = UPF_BOOT_AUTOCONF,
  23         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
  24         .scbrr_algo_id  = SCBRR_ALGO_2,
  25         .type           = PORT_SCIF,
  26         .irqs           = SCIx_IRQ_MUXED(evt2irq(0xc00)),
  27 };
  28
  29 static struct platform_device scif0_device = {
  30         .name           = "sh-sci",
  31         .id             = 0,
  32         .dev            = {
  33                 .platform_data  = &scif0_platform_data,
  34         },
  35 };
  36
  37 static struct plat_sci_port scif1_platform_data = {
  38         .mapbase        = 0xffe10000,
  39         .flags          = UPF_BOOT_AUTOCONF,
  40         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
  41         .scbrr_algo_id  = SCBRR_ALGO_2,
  42         .type           = PORT_SCIF,
  43         .irqs           = SCIx_IRQ_MUXED(evt2irq(0xc20)),
  44 };
  45
  46 static struct platform_device scif1_device = {
  47         .name           = "sh-sci",
  48         .id             = 1,
  49         .dev            = {
  50                 .platform_data  = &scif1_platform_data,
  51         },
  52 };
  53
  54 static struct plat_sci_port scif2_platform_data = {
  55         .mapbase        = 0xffe20000,
  56         .flags          = UPF_BOOT_AUTOCONF,
  57         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
  58         .scbrr_algo_id  = SCBRR_ALGO_2,
  59         .type           = PORT_SCIF,
  60         .irqs           = SCIx_IRQ_MUXED(evt2irq(0xc40)),
  61 };
  62
  63 static struct platform_device scif2_device = {
  64         .name           = "sh-sci",
  65         .id             = 2,
  66         .dev            = {
  67                 .platform_data  = &scif2_platform_data,
  68         },
  69 };
  70
  71 static struct plat_sci_port scif3_platform_data = {
  72         .mapbase        = 0xffe30000,
  73         .flags          = UPF_BOOT_AUTOCONF,
  74         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
  75         .scbrr_algo_id  = SCBRR_ALGO_2,
  76         .type           = PORT_SCIF,
  77         .irqs           = SCIx_IRQ_MUXED(evt2irq(0xc60)),
  78 };
  79
  80 static struct platform_device scif3_device = {
  81         .name           = "sh-sci",
  82         .id             = 3,
  83         .dev            = {
  84                 .platform_data  = &scif3_platform_data,
  85         },
  86 };
  87
  88 static struct resource iic0_resources[] = {
  89         [0] = {
  90                 .name   = "IIC0",
  91                 .start  = 0x04470000,
  92                 .end    = 0x04470017,
  93                 .flags  = IORESOURCE_MEM,
  94         },
  95         [1] = {
  96                 .start  = evt2irq(0xe00),
  97                 .end    = evt2irq(0xe60),
  98                 .flags  = IORESOURCE_IRQ,
  99        },
 100 };
 101
 102 static struct platform_device iic0_device = {
 103         .name           = "i2c-sh_mobile",
 104         .id             = 0, /* "i2c0" clock */
 105         .num_resources  = ARRAY_SIZE(iic0_resources),
 106         .resource       = iic0_resources,
 107 };
 108
 109 static struct resource iic1_resources[] = {
 110         [0] = {
 111                 .name   = "IIC1",
 112                 .start  = 0x04750000,
 113                 .end    = 0x04750017,
 114                 .flags  = IORESOURCE_MEM,
 115         },
 116         [1] = {
 117                 .start  = evt2irq(0x780),
 118                 .end    = evt2irq(0x7e0),
 119                 .flags  = IORESOURCE_IRQ,
 120        },
 121 };
 122
 123 static struct platform_device iic1_device = {
 124         .name           = "i2c-sh_mobile",
 125         .id             = 1, /* "i2c1" clock */
 126         .num_resources  = ARRAY_SIZE(iic1_resources),
 127         .resource       = iic1_resources,
 128 };
 129
 130 static struct uio_info vpu_platform_data = {
 131         .name = "VPU4",
 132         .version = "0",
 133         .irq = evt2irq(0x980),
 134 };
 135
 136 static struct resource vpu_resources[] = {
 137         [0] = {
 138                 .name   = "VPU",
 139                 .start  = 0xfe900000,
 140                 .end    = 0xfe9022eb,
 141                 .flags  = IORESOURCE_MEM,
 142         },
 143         [1] = {
 144                 /* place holder for contiguous memory */
 145         },
 146 };
 147
 148 static struct platform_device vpu_device = {
 149         .name           = "uio_pdrv_genirq",
 150         .id             = 0,
 151         .dev = {
 152                 .platform_data  = &vpu_platform_data,
 153         },
 154         .resource       = vpu_resources,
 155         .num_resources  = ARRAY_SIZE(vpu_resources),
 156 };
 157
 158 static struct uio_info veu_platform_data = {
 159         .name = "VEU",
 160         .version = "0",
 161         .irq = evt2irq(0x8c0),
 162 };
 163
 164 static struct resource veu_resources[] = {
 165         [0] = {
 166                 .name   = "VEU",
 167                 .start  = 0xfe920000,
 168                 .end    = 0xfe9200b7,
 169                 .flags  = IORESOURCE_MEM,
 170         },
 171         [1] = {
 172                 /* place holder for contiguous memory */
 173         },
 174 };
 175
 176 static struct platform_device veu_device = {
 177         .name           = "uio_pdrv_genirq",
 178         .id             = 1,
 179         .dev = {
 180                 .platform_data  = &veu_platform_data,
 181         },
 182         .resource       = veu_resources,
 183         .num_resources  = ARRAY_SIZE(veu_resources),
 184 };
 185
 186 static struct uio_info jpu_platform_data = {
 187         .name = "JPU",
 188         .version = "0",
 189         .irq = evt2irq(0x560),
 190 };
 191
 192 static struct resource jpu_resources[] = {
 193         [0] = {
 194                 .name   = "JPU",
 195                 .start  = 0xfea00000,
 196                 .end    = 0xfea102d3,
 197                 .flags  = IORESOURCE_MEM,
 198         },
 199         [1] = {
 200                 /* place holder for contiguous memory */
 201         },
 202 };
 203
 204 static struct platform_device jpu_device = {
 205         .name           = "uio_pdrv_genirq",
 206         .id             = 2,
 207         .dev = {
 208                 .platform_data  = &jpu_platform_data,
 209         },
 210         .resource       = jpu_resources,
 211         .num_resources  = ARRAY_SIZE(jpu_resources),
 212 };
 213
 214 static struct sh_timer_config cmt_platform_data = {
 215         .channel_offset = 0x60,
 216         .timer_bit = 5,
 217         .clockevent_rating = 125,
 218         .clocksource_rating = 200,
 219 };
 220
 221 static struct resource cmt_resources[] = {
 222         [0] = {
 223                 .start  = 0x044a0060,
 224                 .end    = 0x044a006b,
 225                 .flags  = IORESOURCE_MEM,
 226         },
 227         [1] = {
 228                 .start  = evt2irq(0xf00),
 229                 .flags  = IORESOURCE_IRQ,
 230         },
 231 };
 232
 233 static struct platform_device cmt_device = {
 234         .name           = "sh_cmt",
 235         .id             = 0,
 236         .dev = {
 237                 .platform_data  = &cmt_platform_data,
 238         },
 239         .resource       = cmt_resources,
 240         .num_resources  = ARRAY_SIZE(cmt_resources),
 241 };
 242
 243 static struct sh_timer_config tmu0_platform_data = {
 244         .channel_offset = 0x04,
 245         .timer_bit = 0,
 246         .clockevent_rating = 200,
 247 };
 248
 249 static struct resource tmu0_resources[] = {
 250         [0] = {
 251                 .start  = 0xffd80008,
 252                 .end    = 0xffd80013,
 253                 .flags  = IORESOURCE_MEM,
 254         },
 255         [1] = {
 256                 .start  = evt2irq(0x400),
 257                 .flags  = IORESOURCE_IRQ,
 258         },
 259 };
 260
 261 static struct platform_device tmu0_device = {
 262         .name           = "sh_tmu",
 263         .id             = 0,
 264         .dev = {
 265                 .platform_data  = &tmu0_platform_data,
 266         },
 267         .resource       = tmu0_resources,
 268         .num_resources  = ARRAY_SIZE(tmu0_resources),
 269 };
 270
 271 static struct sh_timer_config tmu1_platform_data = {
 272         .channel_offset = 0x10,
 273         .timer_bit = 1,
 274         .clocksource_rating = 200,
 275 };
 276
 277 static struct resource tmu1_resources[] = {
 278         [0] = {
 279                 .start  = 0xffd80014,
 280                 .end    = 0xffd8001f,
 281                 .flags  = IORESOURCE_MEM,
 282         },
 283         [1] = {
 284                 .start  = evt2irq(0x420),
 285                 .flags  = IORESOURCE_IRQ,
 286         },
 287 };
 288
 289 static struct platform_device tmu1_device = {
 290         .name           = "sh_tmu",
 291         .id             = 1,
 292         .dev = {
 293                 .platform_data  = &tmu1_platform_data,
 294         },
 295         .resource       = tmu1_resources,
 296         .num_resources  = ARRAY_SIZE(tmu1_resources),
 297 };
 298
 299 static struct sh_timer_config tmu2_platform_data = {
 300         .channel_offset = 0x1c,
 301         .timer_bit = 2,
 302 };
 303
 304 static struct resource tmu2_resources[] = {
 305         [0] = {
 306                 .start  = 0xffd80020,
 307                 .end    = 0xffd8002b,
 308                 .flags  = IORESOURCE_MEM,
 309         },
 310         [1] = {
 311                 .start  = evt2irq(0x440),
 312                 .flags  = IORESOURCE_IRQ,
 313         },
 314 };
 315
 316 static struct platform_device tmu2_device = {
 317         .name           = "sh_tmu",
 318         .id             = 2,
 319         .dev = {
 320                 .platform_data  = &tmu2_platform_data,
 321         },
 322         .resource       = tmu2_resources,
 323         .num_resources  = ARRAY_SIZE(tmu2_resources),
 324 };
 325
 326 static struct platform_device *sh7343_devices[] __initdata = {
 327         &scif0_device,
 328         &scif1_device,
 329         &scif2_device,
 330         &scif3_device,
 331         &cmt_device,
 332         &tmu0_device,
 333         &tmu1_device,
 334         &tmu2_device,
 335         &iic0_device,
 336         &iic1_device,
 337         &vpu_device,
 338         &veu_device,
 339         &jpu_device,
 340 };
 341
 342 static int __init sh7343_devices_setup(void)
 343 {
 344         platform_resource_setup_memory(&vpu_device, "vpu", 1 << 20);
 345         platform_resource_setup_memory(&veu_device, "veu", 2 << 20);
 346         platform_resource_setup_memory(&jpu_device, "jpu", 2 << 20);
 347
 348         return platform_add_devices(sh7343_devices,
 349                                     ARRAY_SIZE(sh7343_devices));
 350 }
 351 arch_initcall(sh7343_devices_setup);
 352
 353 static struct platform_device *sh7343_early_devices[] __initdata = {
 354         &scif0_device,
 355         &scif1_device,
 356         &scif2_device,
 357         &scif3_device,
 358         &cmt_device,
 359         &tmu0_device,
 360         &tmu1_device,
 361         &tmu2_device,
 362 };
 363
 364 void __init plat_early_device_setup(void)
 365 {
 366         early_platform_add_devices(sh7343_early_devices,
 367                                    ARRAY_SIZE(sh7343_early_devices));
 368 }
 369
 370 enum {
 371         UNUSED = 0,
 372         ENABLED,
 373         DISABLED,
 374
 375         /* interrupt sources */
 376         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
 377         DMAC0, DMAC1, DMAC2, DMAC3,
 378         VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU,
 379         MFI, VPU, TPU, Z3D4, USBI0, USBI1,
 380         MMC_ERR, MMC_TRAN, MMC_FSTAT, MMC_FRDY,
 381         DMAC4, DMAC5, DMAC_DADERR,
 382         KEYSC,
 383         SCIF, SCIF1, SCIF2, SCIF3,
 384         SIOF0, SIOF1, SIO,
 385         FLCTL_FLSTEI, FLCTL_FLENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
 386         I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI,
 387         I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI,
 388         SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI,
 389         IRDA, SDHI, CMT, TSIF, SIU,
 390         TMU0, TMU1, TMU2,
 391         JPU, LCDC,
 392
 393         /* interrupt groups */
 394
 395         DMAC0123, VIOVOU, MMC, DMAC45, FLCTL, I2C0, I2C1, SIM, USB,
 396 };
 397
 398 static struct intc_vect vectors[] __initdata = {
 399         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
 400         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
 401         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
 402         INTC_VECT(IRQ6, 0x6c0), INTC_VECT(IRQ7, 0x6e0),
 403         INTC_VECT(I2C1_ALI, 0x780), INTC_VECT(I2C1_TACKI, 0x7a0),
 404         INTC_VECT(I2C1_WAITI, 0x7c0), INTC_VECT(I2C1_DTEI, 0x7e0),
 405         INTC_VECT(DMAC0, 0x800), INTC_VECT(DMAC1, 0x820),
 406         INTC_VECT(DMAC2, 0x840), INTC_VECT(DMAC3, 0x860),
 407         INTC_VECT(VIO_CEUI, 0x880), INTC_VECT(VIO_BEUI, 0x8a0),
 408         INTC_VECT(VIO_VEUI, 0x8c0), INTC_VECT(VOU, 0x8e0),
 409         INTC_VECT(MFI, 0x900), INTC_VECT(VPU, 0x980),
 410         INTC_VECT(TPU, 0x9a0), INTC_VECT(Z3D4, 0x9e0),
 411         INTC_VECT(USBI0, 0xa20), INTC_VECT(USBI1, 0xa40),
 412         INTC_VECT(MMC_ERR, 0xb00), INTC_VECT(MMC_TRAN, 0xb20),
 413         INTC_VECT(MMC_FSTAT, 0xb40), INTC_VECT(MMC_FRDY, 0xb60),
 414         INTC_VECT(DMAC4, 0xb80), INTC_VECT(DMAC5, 0xba0),
 415         INTC_VECT(DMAC_DADERR, 0xbc0), INTC_VECT(KEYSC, 0xbe0),
 416         INTC_VECT(SCIF, 0xc00), INTC_VECT(SCIF1, 0xc20),
 417         INTC_VECT(SCIF2, 0xc40), INTC_VECT(SCIF3, 0xc60),
 418         INTC_VECT(SIOF0, 0xc80), INTC_VECT(SIOF1, 0xca0),
 419         INTC_VECT(SIO, 0xd00),
 420         INTC_VECT(FLCTL_FLSTEI, 0xd80), INTC_VECT(FLCTL_FLENDI, 0xda0),
 421         INTC_VECT(FLCTL_FLTREQ0I, 0xdc0), INTC_VECT(FLCTL_FLTREQ1I, 0xde0),
 422         INTC_VECT(I2C0_ALI, 0xe00), INTC_VECT(I2C0_TACKI, 0xe20),
 423         INTC_VECT(I2C0_WAITI, 0xe40), INTC_VECT(I2C0_DTEI, 0xe60),
 424         INTC_VECT(SDHI, 0xe80), INTC_VECT(SDHI, 0xea0),
 425         INTC_VECT(SDHI, 0xec0), INTC_VECT(SDHI, 0xee0),
 426         INTC_VECT(CMT, 0xf00), INTC_VECT(TSIF, 0xf20),
 427         INTC_VECT(SIU, 0xf80),
 428         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 429         INTC_VECT(TMU2, 0x440),
 430         INTC_VECT(JPU, 0x560), INTC_VECT(LCDC, 0x580),
 431 };
 432
 433 static struct intc_group groups[] __initdata = {
 434         INTC_GROUP(DMAC0123, DMAC0, DMAC1, DMAC2, DMAC3),
 435         INTC_GROUP(VIOVOU, VIO_CEUI, VIO_BEUI, VIO_VEUI, VOU),
 436         INTC_GROUP(MMC, MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR),
 437         INTC_GROUP(DMAC45, DMAC4, DMAC5, DMAC_DADERR),
 438         INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLENDI,
 439                    FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
 440         INTC_GROUP(I2C0, I2C0_ALI, I2C0_TACKI, I2C0_WAITI, I2C0_DTEI),
 441         INTC_GROUP(I2C1, I2C1_ALI, I2C1_TACKI, I2C1_WAITI, I2C1_DTEI),
 442         INTC_GROUP(SIM, SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI),
 443         INTC_GROUP(USB, USBI0, USBI1),
 444 };
 445
 446 static struct intc_mask_reg mask_registers[] __initdata = {
 447         { 0xa4080084, 0xa40800c4, 8, /* IMR1 / IMCR1 */
 448           { VOU, VIO_VEUI, VIO_BEUI, VIO_CEUI, DMAC3, DMAC2, DMAC1, DMAC0 } },
 449         { 0xa4080088, 0xa40800c8, 8, /* IMR2 / IMCR2 */
 450           { 0, 0, 0, VPU, 0, 0, 0, MFI } },
 451         { 0xa408008c, 0xa40800cc, 8, /* IMR3 / IMCR3 */
 452           { SIM_TEI, SIM_TXI, SIM_RXI, SIM_ERI, 0, 0, 0, IRDA } },
 453         { 0xa4080090, 0xa40800d0, 8, /* IMR4 / IMCR4 */
 454           { 0, TMU2, TMU1, TMU0, JPU, 0, 0, LCDC } },
 455         { 0xa4080094, 0xa40800d4, 8, /* IMR5 / IMCR5 */
 456           { KEYSC, DMAC_DADERR, DMAC5, DMAC4, SCIF3, SCIF2, SCIF1, SCIF } },
 457         { 0xa4080098, 0xa40800d8, 8, /* IMR6 / IMCR6 */
 458           { 0, 0, 0, SIO, Z3D4, 0, SIOF1, SIOF0 } },
 459         { 0xa408009c, 0xa40800dc, 8, /* IMR7 / IMCR7 */
 460           { I2C0_DTEI, I2C0_WAITI, I2C0_TACKI, I2C0_ALI,
 461             FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLENDI, FLCTL_FLSTEI } },
 462         { 0xa40800a0, 0xa40800e0, 8, /* IMR8 / IMCR8 */
 463           { DISABLED, ENABLED, ENABLED, ENABLED, 0, 0, 0, SIU } },
 464         { 0xa40800a4, 0xa40800e4, 8, /* IMR9 / IMCR9 */
 465           { 0, 0, 0, CMT, 0, USBI1, USBI0 } },
 466         { 0xa40800a8, 0xa40800e8, 8, /* IMR10 / IMCR10 */
 467           { MMC_FRDY, MMC_FSTAT, MMC_TRAN, MMC_ERR } },
 468         { 0xa40800ac, 0xa40800ec, 8, /* IMR11 / IMCR11 */
 469           { I2C1_DTEI, I2C1_WAITI, I2C1_TACKI, I2C1_ALI, TPU, 0, 0, TSIF } },
 470         { 0xa4140044, 0xa4140064, 8, /* INTMSK00 / INTMSKCLR00 */
 471           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 472 };
 473
 474 static struct intc_prio_reg prio_registers[] __initdata = {
 475         { 0xa4080000, 0, 16, 4, /* IPRA */ { TMU0, TMU1, TMU2 } },
 476         { 0xa4080004, 0, 16, 4, /* IPRB */ { JPU, LCDC, SIM } },
 477         { 0xa4080010, 0, 16, 4, /* IPRE */ { DMAC0123, VIOVOU, MFI, VPU } },
 478         { 0xa4080014, 0, 16, 4, /* IPRF */ { KEYSC, DMAC45, USB, CMT } },
 479         { 0xa4080018, 0, 16, 4, /* IPRG */ { SCIF, SCIF1, SCIF2, SCIF3 } },
 480         { 0xa408001c, 0, 16, 4, /* IPRH */ { SIOF0, SIOF1, FLCTL, I2C0 } },
 481         { 0xa4080020, 0, 16, 4, /* IPRI */ { SIO, 0, TSIF, I2C1 } },
 482         { 0xa4080024, 0, 16, 4, /* IPRJ */ { Z3D4, 0, SIU } },
 483         { 0xa4080028, 0, 16, 4, /* IPRK */ { 0, MMC, 0, SDHI } },
 484         { 0xa408002c, 0, 16, 4, /* IPRL */ { 0, 0, TPU } },
 485         { 0xa4140010, 0, 32, 4, /* INTPRI00 */
 486           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 487 };
 488
 489 static struct intc_sense_reg sense_registers[] __initdata = {
 490         { 0xa414001c, 16, 2, /* ICR1 */
 491           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 492 };
 493
 494 static struct intc_mask_reg ack_registers[] __initdata = {
 495         { 0xa4140024, 0, 8, /* INTREQ00 */
 496           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
 497 };
 498
 499 static struct intc_desc intc_desc __initdata = {
 500         .name = "sh7343",
 501         .force_enable = ENABLED,
 502         .force_disable = DISABLED,
 503         .hw = INTC_HW_DESC(vectors, groups, mask_registers,
 504                            prio_registers, sense_registers, ack_registers),
 505 };
 506
 507 void __init plat_irq_setup(void)
 508 {
 509         register_intc_controller(&intc_desc);
 510 }