4 * Copyright (C) 2006 - 2008 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
13 #include <linux/serial_sci.h>
14 #include <linux/sh_timer.h>
15 #include <linux/sh_intc.h>
18 static struct plat_sci_port scif0_platform_data
= {
19 .flags
= UPF_BOOT_AUTOCONF
,
20 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_REIE
| SCSCR_TOIE
,
24 static struct resource scif0_resources
[] = {
25 DEFINE_RES_MEM(0xff923000, 0x100),
26 DEFINE_RES_IRQ(evt2irq(0x9a0)),
29 static struct platform_device scif0_device
= {
32 .resource
= scif0_resources
,
33 .num_resources
= ARRAY_SIZE(scif0_resources
),
35 .platform_data
= &scif0_platform_data
,
39 static struct plat_sci_port scif1_platform_data
= {
40 .flags
= UPF_BOOT_AUTOCONF
,
41 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_REIE
| SCSCR_TOIE
,
45 static struct resource scif1_resources
[] = {
46 DEFINE_RES_MEM(0xff924000, 0x100),
47 DEFINE_RES_IRQ(evt2irq(0x9c0)),
50 static struct platform_device scif1_device
= {
53 .resource
= scif1_resources
,
54 .num_resources
= ARRAY_SIZE(scif1_resources
),
56 .platform_data
= &scif1_platform_data
,
60 static struct plat_sci_port scif2_platform_data
= {
61 .flags
= UPF_BOOT_AUTOCONF
,
62 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_REIE
| SCSCR_TOIE
,
66 static struct resource scif2_resources
[] = {
67 DEFINE_RES_MEM(0xff925000, 0x100),
68 DEFINE_RES_IRQ(evt2irq(0x9e0)),
71 static struct platform_device scif2_device
= {
74 .resource
= scif2_resources
,
75 .num_resources
= ARRAY_SIZE(scif2_resources
),
77 .platform_data
= &scif2_platform_data
,
81 static struct plat_sci_port scif3_platform_data
= {
82 .flags
= UPF_BOOT_AUTOCONF
,
83 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_REIE
| SCSCR_TOIE
,
87 static struct resource scif3_resources
[] = {
88 DEFINE_RES_MEM(0xff926000, 0x100),
89 DEFINE_RES_IRQ(evt2irq(0xa00)),
92 static struct platform_device scif3_device
= {
95 .resource
= scif3_resources
,
96 .num_resources
= ARRAY_SIZE(scif3_resources
),
98 .platform_data
= &scif3_platform_data
,
102 static struct plat_sci_port scif4_platform_data
= {
103 .flags
= UPF_BOOT_AUTOCONF
,
104 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_REIE
| SCSCR_TOIE
,
108 static struct resource scif4_resources
[] = {
109 DEFINE_RES_MEM(0xff927000, 0x100),
110 DEFINE_RES_IRQ(evt2irq(0xa20)),
113 static struct platform_device scif4_device
= {
116 .resource
= scif4_resources
,
117 .num_resources
= ARRAY_SIZE(scif4_resources
),
119 .platform_data
= &scif4_platform_data
,
123 static struct plat_sci_port scif5_platform_data
= {
124 .flags
= UPF_BOOT_AUTOCONF
,
125 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_REIE
| SCSCR_TOIE
,
129 static struct resource scif5_resources
[] = {
130 DEFINE_RES_MEM(0xff928000, 0x100),
131 DEFINE_RES_IRQ(evt2irq(0xa40)),
134 static struct platform_device scif5_device
= {
137 .resource
= scif5_resources
,
138 .num_resources
= ARRAY_SIZE(scif5_resources
),
140 .platform_data
= &scif5_platform_data
,
144 static struct plat_sci_port scif6_platform_data
= {
145 .flags
= UPF_BOOT_AUTOCONF
,
146 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_REIE
| SCSCR_TOIE
,
150 static struct resource scif6_resources
[] = {
151 DEFINE_RES_MEM(0xff929000, 0x100),
152 DEFINE_RES_IRQ(evt2irq(0xa60)),
155 static struct platform_device scif6_device
= {
158 .resource
= scif6_resources
,
159 .num_resources
= ARRAY_SIZE(scif6_resources
),
161 .platform_data
= &scif6_platform_data
,
165 static struct plat_sci_port scif7_platform_data
= {
166 .flags
= UPF_BOOT_AUTOCONF
,
167 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_REIE
| SCSCR_TOIE
,
171 static struct resource scif7_resources
[] = {
172 DEFINE_RES_MEM(0xff92a000, 0x100),
173 DEFINE_RES_IRQ(evt2irq(0xa80)),
176 static struct platform_device scif7_device
= {
179 .resource
= scif7_resources
,
180 .num_resources
= ARRAY_SIZE(scif7_resources
),
182 .platform_data
= &scif7_platform_data
,
186 static struct plat_sci_port scif8_platform_data
= {
187 .flags
= UPF_BOOT_AUTOCONF
,
188 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_REIE
| SCSCR_TOIE
,
192 static struct resource scif8_resources
[] = {
193 DEFINE_RES_MEM(0xff92b000, 0x100),
194 DEFINE_RES_IRQ(evt2irq(0xaa0)),
197 static struct platform_device scif8_device
= {
200 .resource
= scif8_resources
,
201 .num_resources
= ARRAY_SIZE(scif8_resources
),
203 .platform_data
= &scif8_platform_data
,
207 static struct plat_sci_port scif9_platform_data
= {
208 .flags
= UPF_BOOT_AUTOCONF
,
209 .scscr
= SCSCR_RE
| SCSCR_TE
| SCSCR_REIE
| SCSCR_TOIE
,
213 static struct resource scif9_resources
[] = {
214 DEFINE_RES_MEM(0xff92c000, 0x100),
215 DEFINE_RES_IRQ(evt2irq(0xac0)),
218 static struct platform_device scif9_device
= {
221 .resource
= scif9_resources
,
222 .num_resources
= ARRAY_SIZE(scif9_resources
),
224 .platform_data
= &scif9_platform_data
,
228 static struct sh_timer_config tmu0_platform_data
= {
229 .channel_offset
= 0x04,
231 .clockevent_rating
= 200,
234 static struct resource tmu0_resources
[] = {
238 .flags
= IORESOURCE_MEM
,
241 .start
= evt2irq(0x400),
242 .flags
= IORESOURCE_IRQ
,
246 static struct platform_device tmu0_device
= {
250 .platform_data
= &tmu0_platform_data
,
252 .resource
= tmu0_resources
,
253 .num_resources
= ARRAY_SIZE(tmu0_resources
),
256 static struct sh_timer_config tmu1_platform_data
= {
257 .channel_offset
= 0x10,
259 .clocksource_rating
= 200,
262 static struct resource tmu1_resources
[] = {
266 .flags
= IORESOURCE_MEM
,
269 .start
= evt2irq(0x420),
270 .flags
= IORESOURCE_IRQ
,
274 static struct platform_device tmu1_device
= {
278 .platform_data
= &tmu1_platform_data
,
280 .resource
= tmu1_resources
,
281 .num_resources
= ARRAY_SIZE(tmu1_resources
),
284 static struct sh_timer_config tmu2_platform_data
= {
285 .channel_offset
= 0x1c,
289 static struct resource tmu2_resources
[] = {
293 .flags
= IORESOURCE_MEM
,
296 .start
= evt2irq(0x440),
297 .flags
= IORESOURCE_IRQ
,
301 static struct platform_device tmu2_device
= {
305 .platform_data
= &tmu2_platform_data
,
307 .resource
= tmu2_resources
,
308 .num_resources
= ARRAY_SIZE(tmu2_resources
),
311 static struct sh_timer_config tmu3_platform_data
= {
312 .channel_offset
= 0x04,
316 static struct resource tmu3_resources
[] = {
320 .flags
= IORESOURCE_MEM
,
323 .start
= evt2irq(0x460),
324 .flags
= IORESOURCE_IRQ
,
328 static struct platform_device tmu3_device
= {
332 .platform_data
= &tmu3_platform_data
,
334 .resource
= tmu3_resources
,
335 .num_resources
= ARRAY_SIZE(tmu3_resources
),
338 static struct sh_timer_config tmu4_platform_data
= {
339 .channel_offset
= 0x10,
343 static struct resource tmu4_resources
[] = {
347 .flags
= IORESOURCE_MEM
,
350 .start
= evt2irq(0x480),
351 .flags
= IORESOURCE_IRQ
,
355 static struct platform_device tmu4_device
= {
359 .platform_data
= &tmu4_platform_data
,
361 .resource
= tmu4_resources
,
362 .num_resources
= ARRAY_SIZE(tmu4_resources
),
365 static struct sh_timer_config tmu5_platform_data
= {
366 .channel_offset
= 0x1c,
370 static struct resource tmu5_resources
[] = {
374 .flags
= IORESOURCE_MEM
,
377 .start
= evt2irq(0x4a0),
378 .flags
= IORESOURCE_IRQ
,
382 static struct platform_device tmu5_device
= {
386 .platform_data
= &tmu5_platform_data
,
388 .resource
= tmu5_resources
,
389 .num_resources
= ARRAY_SIZE(tmu5_resources
),
392 static struct sh_timer_config tmu6_platform_data
= {
393 .channel_offset
= 0x04,
397 static struct resource tmu6_resources
[] = {
401 .flags
= IORESOURCE_MEM
,
404 .start
= evt2irq(0x4c0),
405 .flags
= IORESOURCE_IRQ
,
409 static struct platform_device tmu6_device
= {
413 .platform_data
= &tmu6_platform_data
,
415 .resource
= tmu6_resources
,
416 .num_resources
= ARRAY_SIZE(tmu6_resources
),
419 static struct sh_timer_config tmu7_platform_data
= {
420 .channel_offset
= 0x10,
424 static struct resource tmu7_resources
[] = {
428 .flags
= IORESOURCE_MEM
,
431 .start
= evt2irq(0x4e0),
432 .flags
= IORESOURCE_IRQ
,
436 static struct platform_device tmu7_device
= {
440 .platform_data
= &tmu7_platform_data
,
442 .resource
= tmu7_resources
,
443 .num_resources
= ARRAY_SIZE(tmu7_resources
),
446 static struct sh_timer_config tmu8_platform_data
= {
447 .channel_offset
= 0x1c,
451 static struct resource tmu8_resources
[] = {
455 .flags
= IORESOURCE_MEM
,
458 .start
= evt2irq(0x500),
459 .flags
= IORESOURCE_IRQ
,
463 static struct platform_device tmu8_device
= {
467 .platform_data
= &tmu8_platform_data
,
469 .resource
= tmu8_resources
,
470 .num_resources
= ARRAY_SIZE(tmu8_resources
),
473 static struct platform_device
*sh7770_devices
[] __initdata
= {
495 static int __init
sh7770_devices_setup(void)
497 return platform_add_devices(sh7770_devices
,
498 ARRAY_SIZE(sh7770_devices
));
500 arch_initcall(sh7770_devices_setup
);
502 static struct platform_device
*sh7770_early_devices
[] __initdata
= {
524 void __init
plat_early_device_setup(void)
526 early_platform_add_devices(sh7770_early_devices
,
527 ARRAY_SIZE(sh7770_early_devices
));
533 /* interrupt sources */
534 IRL_LLLL
, IRL_LLLH
, IRL_LLHL
, IRL_LLHH
,
535 IRL_LHLL
, IRL_LHLH
, IRL_LHHL
, IRL_LHHH
,
536 IRL_HLLL
, IRL_HLLH
, IRL_HLHL
, IRL_HLHH
,
537 IRL_HHLL
, IRL_HHLH
, IRL_HHHL
,
539 IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
,
542 TMU0
, TMU1
, TMU2
, TMU2_TICPI
,
543 TMU3
, TMU4
, TMU5
, TMU5_TICPI
,
545 HAC
, IPI
, SPDIF
, HUDI
, I2C
,
546 DMAC0_DMINT0
, DMAC0_DMINT1
, DMAC0_DMINT2
,
547 I2S0
, I2S1
, I2S2
, I2S3
,
548 SRC_RX
, SRC_TX
, SRC_SPDIF
,
549 DU
, VIDEO_IN
, REMOTE
, YUV
, USB
, ATAPI
, CAN
, GPS
, GFX2D
,
550 GFX3D_MBX
, GFX3D_DMAC
,
553 SCIF089
, SCIF1234
, SCIF567
,
555 BBDMAC_0_3
, BBDMAC_4_7
, BBDMAC_8_10
, BBDMAC_11_14
,
556 BBDMAC_15_18
, BBDMAC_19_22
, BBDMAC_23_26
, BBDMAC_27
,
557 BBDMAC_28
, BBDMAC_29
, BBDMAC_30
, BBDMAC_31
,
559 /* interrupt groups */
560 TMU
, DMAC
, I2S
, SRC
, GFX3D
, SPI
, SCIF
, BBDMAC
,
563 static struct intc_vect vectors
[] __initdata
= {
564 INTC_VECT(GPIO
, 0x3e0),
565 INTC_VECT(TMU0
, 0x400), INTC_VECT(TMU1
, 0x420),
566 INTC_VECT(TMU2
, 0x440), INTC_VECT(TMU2_TICPI
, 0x460),
567 INTC_VECT(TMU3
, 0x480), INTC_VECT(TMU4
, 0x4a0),
568 INTC_VECT(TMU5
, 0x4c0), INTC_VECT(TMU5_TICPI
, 0x4e0),
569 INTC_VECT(TMU6
, 0x500), INTC_VECT(TMU7
, 0x520),
570 INTC_VECT(TMU8
, 0x540),
571 INTC_VECT(HAC
, 0x580), INTC_VECT(IPI
, 0x5c0),
572 INTC_VECT(SPDIF
, 0x5e0),
573 INTC_VECT(HUDI
, 0x600), INTC_VECT(I2C
, 0x620),
574 INTC_VECT(DMAC0_DMINT0
, 0x640), INTC_VECT(DMAC0_DMINT1
, 0x660),
575 INTC_VECT(DMAC0_DMINT2
, 0x680),
576 INTC_VECT(I2S0
, 0x6a0), INTC_VECT(I2S1
, 0x6c0),
577 INTC_VECT(I2S2
, 0x6e0), INTC_VECT(I2S3
, 0x700),
578 INTC_VECT(SRC_RX
, 0x720), INTC_VECT(SRC_TX
, 0x740),
579 INTC_VECT(SRC_SPDIF
, 0x760),
580 INTC_VECT(DU
, 0x780), INTC_VECT(VIDEO_IN
, 0x7a0),
581 INTC_VECT(REMOTE
, 0x7c0), INTC_VECT(YUV
, 0x7e0),
582 INTC_VECT(USB
, 0x840), INTC_VECT(ATAPI
, 0x860),
583 INTC_VECT(CAN
, 0x880), INTC_VECT(GPS
, 0x8a0),
584 INTC_VECT(GFX2D
, 0x8c0),
585 INTC_VECT(GFX3D_MBX
, 0x900), INTC_VECT(GFX3D_DMAC
, 0x920),
586 INTC_VECT(EXBUS_ATA
, 0x940),
587 INTC_VECT(SPI0
, 0x960), INTC_VECT(SPI1
, 0x980),
588 INTC_VECT(SCIF089
, 0x9a0), INTC_VECT(SCIF1234
, 0x9c0),
589 INTC_VECT(SCIF1234
, 0x9e0), INTC_VECT(SCIF1234
, 0xa00),
590 INTC_VECT(SCIF1234
, 0xa20), INTC_VECT(SCIF567
, 0xa40),
591 INTC_VECT(SCIF567
, 0xa60), INTC_VECT(SCIF567
, 0xa80),
592 INTC_VECT(SCIF089
, 0xaa0), INTC_VECT(SCIF089
, 0xac0),
593 INTC_VECT(ADC
, 0xb20),
594 INTC_VECT(BBDMAC_0_3
, 0xba0), INTC_VECT(BBDMAC_0_3
, 0xbc0),
595 INTC_VECT(BBDMAC_0_3
, 0xbe0), INTC_VECT(BBDMAC_0_3
, 0xc00),
596 INTC_VECT(BBDMAC_4_7
, 0xc20), INTC_VECT(BBDMAC_4_7
, 0xc40),
597 INTC_VECT(BBDMAC_4_7
, 0xc60), INTC_VECT(BBDMAC_4_7
, 0xc80),
598 INTC_VECT(BBDMAC_8_10
, 0xca0), INTC_VECT(BBDMAC_8_10
, 0xcc0),
599 INTC_VECT(BBDMAC_8_10
, 0xce0), INTC_VECT(BBDMAC_11_14
, 0xd00),
600 INTC_VECT(BBDMAC_11_14
, 0xd20), INTC_VECT(BBDMAC_11_14
, 0xd40),
601 INTC_VECT(BBDMAC_11_14
, 0xd60), INTC_VECT(BBDMAC_15_18
, 0xd80),
602 INTC_VECT(BBDMAC_15_18
, 0xda0), INTC_VECT(BBDMAC_15_18
, 0xdc0),
603 INTC_VECT(BBDMAC_15_18
, 0xde0), INTC_VECT(BBDMAC_19_22
, 0xe00),
604 INTC_VECT(BBDMAC_19_22
, 0xe20), INTC_VECT(BBDMAC_19_22
, 0xe40),
605 INTC_VECT(BBDMAC_19_22
, 0xe60), INTC_VECT(BBDMAC_23_26
, 0xe80),
606 INTC_VECT(BBDMAC_23_26
, 0xea0), INTC_VECT(BBDMAC_23_26
, 0xec0),
607 INTC_VECT(BBDMAC_23_26
, 0xee0), INTC_VECT(BBDMAC_27
, 0xf00),
608 INTC_VECT(BBDMAC_28
, 0xf20), INTC_VECT(BBDMAC_29
, 0xf40),
609 INTC_VECT(BBDMAC_30
, 0xf60), INTC_VECT(BBDMAC_31
, 0xf80),
612 static struct intc_group groups
[] __initdata
= {
613 INTC_GROUP(TMU
, TMU0
, TMU1
, TMU2
, TMU2_TICPI
, TMU3
, TMU4
, TMU5
,
614 TMU5_TICPI
, TMU6
, TMU7
, TMU8
),
615 INTC_GROUP(DMAC
, DMAC0_DMINT0
, DMAC0_DMINT1
, DMAC0_DMINT2
),
616 INTC_GROUP(I2S
, I2S0
, I2S1
, I2S2
, I2S3
),
617 INTC_GROUP(SRC
, SRC_RX
, SRC_TX
, SRC_SPDIF
),
618 INTC_GROUP(GFX3D
, GFX3D_MBX
, GFX3D_DMAC
),
619 INTC_GROUP(SPI
, SPI0
, SPI1
),
620 INTC_GROUP(SCIF
, SCIF089
, SCIF1234
, SCIF567
),
622 BBDMAC_0_3
, BBDMAC_4_7
, BBDMAC_8_10
, BBDMAC_11_14
,
623 BBDMAC_15_18
, BBDMAC_19_22
, BBDMAC_23_26
, BBDMAC_27
,
624 BBDMAC_28
, BBDMAC_29
, BBDMAC_30
, BBDMAC_31
),
627 static struct intc_mask_reg mask_registers
[] __initdata
= {
628 { 0xffe00040, 0xffe00044, 32, /* INT2MSKR / INT2MSKCR */
629 { 0, BBDMAC
, ADC
, SCIF
, SPI
, EXBUS_ATA
, GFX3D
, GFX2D
,
630 GPS
, CAN
, ATAPI
, USB
, YUV
, REMOTE
, VIDEO_IN
, DU
, SRC
, I2S
,
631 DMAC
, I2C
, HUDI
, SPDIF
, IPI
, HAC
, TMU
, GPIO
} },
634 static struct intc_prio_reg prio_registers
[] __initdata
= {
635 { 0xffe00000, 0, 32, 8, /* INT2PRI0 */ { GPIO
, TMU0
, 0, HAC
} },
636 { 0xffe00004, 0, 32, 8, /* INT2PRI1 */ { IPI
, SPDIF
, HUDI
, I2C
} },
637 { 0xffe00008, 0, 32, 8, /* INT2PRI2 */ { DMAC
, I2S
, SRC
, DU
} },
638 { 0xffe0000c, 0, 32, 8, /* INT2PRI3 */ { VIDEO_IN
, REMOTE
, YUV
, USB
} },
639 { 0xffe00010, 0, 32, 8, /* INT2PRI4 */ { ATAPI
, CAN
, GPS
, GFX2D
} },
640 { 0xffe00014, 0, 32, 8, /* INT2PRI5 */ { 0, GFX3D
, EXBUS_ATA
, SPI
} },
641 { 0xffe00018, 0, 32, 8, /* INT2PRI6 */ { SCIF1234
, SCIF567
, SCIF089
} },
642 { 0xffe0001c, 0, 32, 8, /* INT2PRI7 */ { ADC
, 0, 0, BBDMAC_0_3
} },
643 { 0xffe00020, 0, 32, 8, /* INT2PRI8 */
644 { BBDMAC_4_7
, BBDMAC_8_10
, BBDMAC_11_14
, BBDMAC_15_18
} },
645 { 0xffe00024, 0, 32, 8, /* INT2PRI9 */
646 { BBDMAC_19_22
, BBDMAC_23_26
, BBDMAC_27
, BBDMAC_28
} },
647 { 0xffe00028, 0, 32, 8, /* INT2PRI10 */
648 { BBDMAC_29
, BBDMAC_30
, BBDMAC_31
} },
649 { 0xffe0002c, 0, 32, 8, /* INT2PRI11 */
650 { TMU1
, TMU2
, TMU2_TICPI
, TMU3
} },
651 { 0xffe00030, 0, 32, 8, /* INT2PRI12 */
652 { TMU4
, TMU5
, TMU5_TICPI
, TMU6
} },
653 { 0xffe00034, 0, 32, 8, /* INT2PRI13 */
657 static DECLARE_INTC_DESC(intc_desc
, "sh7770", vectors
, groups
,
658 mask_registers
, prio_registers
, NULL
);
660 /* Support for external interrupt pins in IRQ mode */
661 static struct intc_vect irq_vectors
[] __initdata
= {
662 INTC_VECT(IRQ0
, 0x240), INTC_VECT(IRQ1
, 0x280),
663 INTC_VECT(IRQ2
, 0x2c0), INTC_VECT(IRQ3
, 0x300),
664 INTC_VECT(IRQ4
, 0x340), INTC_VECT(IRQ5
, 0x380),
667 static struct intc_mask_reg irq_mask_registers
[] __initdata
= {
668 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
669 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, } },
672 static struct intc_prio_reg irq_prio_registers
[] __initdata
= {
673 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0
, IRQ1
, IRQ2
, IRQ3
,
677 static struct intc_sense_reg irq_sense_registers
[] __initdata
= {
678 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0
, IRQ1
, IRQ2
, IRQ3
,
682 static DECLARE_INTC_DESC(intc_irq_desc
, "sh7770-irq", irq_vectors
,
683 NULL
, irq_mask_registers
, irq_prio_registers
,
684 irq_sense_registers
);
686 /* External interrupt pins in IRL mode */
687 static struct intc_vect irl_vectors
[] __initdata
= {
688 INTC_VECT(IRL_LLLL
, 0x200), INTC_VECT(IRL_LLLH
, 0x220),
689 INTC_VECT(IRL_LLHL
, 0x240), INTC_VECT(IRL_LLHH
, 0x260),
690 INTC_VECT(IRL_LHLL
, 0x280), INTC_VECT(IRL_LHLH
, 0x2a0),
691 INTC_VECT(IRL_LHHL
, 0x2c0), INTC_VECT(IRL_LHHH
, 0x2e0),
692 INTC_VECT(IRL_HLLL
, 0x300), INTC_VECT(IRL_HLLH
, 0x320),
693 INTC_VECT(IRL_HLHL
, 0x340), INTC_VECT(IRL_HLHH
, 0x360),
694 INTC_VECT(IRL_HHLL
, 0x380), INTC_VECT(IRL_HHLH
, 0x3a0),
695 INTC_VECT(IRL_HHHL
, 0x3c0),
698 static struct intc_mask_reg irl3210_mask_registers
[] __initdata
= {
699 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
700 { IRL_LLLL
, IRL_LLLH
, IRL_LLHL
, IRL_LLHH
,
701 IRL_LHLL
, IRL_LHLH
, IRL_LHHL
, IRL_LHHH
,
702 IRL_HLLL
, IRL_HLLH
, IRL_HLHL
, IRL_HLHH
,
703 IRL_HHLL
, IRL_HHLH
, IRL_HHHL
, } },
706 static struct intc_mask_reg irl7654_mask_registers
[] __initdata
= {
707 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
708 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
709 IRL_LLLL
, IRL_LLLH
, IRL_LLHL
, IRL_LLHH
,
710 IRL_LHLL
, IRL_LHLH
, IRL_LHHL
, IRL_LHHH
,
711 IRL_HLLL
, IRL_HLLH
, IRL_HLHL
, IRL_HLHH
,
712 IRL_HHLL
, IRL_HHLH
, IRL_HHHL
, } },
715 static DECLARE_INTC_DESC(intc_irl7654_desc
, "sh7780-irl7654", irl_vectors
,
716 NULL
, irl7654_mask_registers
, NULL
, NULL
);
718 static DECLARE_INTC_DESC(intc_irl3210_desc
, "sh7780-irl3210", irl_vectors
,
719 NULL
, irl3210_mask_registers
, NULL
, NULL
);
721 #define INTC_ICR0 0xffd00000
722 #define INTC_INTMSK0 0xffd00044
723 #define INTC_INTMSK1 0xffd00048
724 #define INTC_INTMSK2 0xffd40080
725 #define INTC_INTMSKCLR1 0xffd00068
726 #define INTC_INTMSKCLR2 0xffd40084
728 void __init
plat_irq_setup(void)
731 __raw_writel(0xff000000, INTC_INTMSK0
);
733 /* disable IRL3-0 + IRL7-4 */
734 __raw_writel(0xc0000000, INTC_INTMSK1
);
735 __raw_writel(0xfffefffe, INTC_INTMSK2
);
737 /* select IRL mode for IRL3-0 + IRL7-4 */
738 __raw_writel(__raw_readl(INTC_ICR0
) & ~0x00c00000, INTC_ICR0
);
740 /* disable holding function, ie enable "SH-4 Mode" */
741 __raw_writel(__raw_readl(INTC_ICR0
) | 0x00200000, INTC_ICR0
);
743 register_intc_controller(&intc_desc
);
746 void __init
plat_irq_setup_pins(int mode
)
750 /* select IRQ mode for IRL3-0 + IRL7-4 */
751 __raw_writel(__raw_readl(INTC_ICR0
) | 0x00c00000, INTC_ICR0
);
752 register_intc_controller(&intc_irq_desc
);
754 case IRQ_MODE_IRL7654
:
755 /* enable IRL7-4 but don't provide any masking */
756 __raw_writel(0x40000000, INTC_INTMSKCLR1
);
757 __raw_writel(0x0000fffe, INTC_INTMSKCLR2
);
759 case IRQ_MODE_IRL3210
:
760 /* enable IRL0-3 but don't provide any masking */
761 __raw_writel(0x80000000, INTC_INTMSKCLR1
);
762 __raw_writel(0xfffe0000, INTC_INTMSKCLR2
);
764 case IRQ_MODE_IRL7654_MASK
:
765 /* enable IRL7-4 and mask using cpu intc controller */
766 __raw_writel(0x40000000, INTC_INTMSKCLR1
);
767 register_intc_controller(&intc_irl7654_desc
);
769 case IRQ_MODE_IRL3210_MASK
:
770 /* enable IRL0-3 and mask using cpu intc controller */
771 __raw_writel(0x80000000, INTC_INTMSKCLR1
);
772 register_intc_controller(&intc_irl3210_desc
);