arch/sh/kernel/cpu/sh4a/setup-sh7770.c

   1 /*
   2  * SH7770 Setup
   3  *
   4  *  Copyright (C) 2006 - 2008  Paul Mundt
   5  *
   6  * This file is subject to the terms and conditions of the GNU General Public
   7  * License.  See the file "COPYING" in the main directory of this archive
   8  * for more details.
   9  */
  10 #include <linux/platform_device.h>
  11 #include <linux/init.h>
  12 #include <linux/serial.h>
  13 #include <linux/serial_sci.h>
  14 #include <linux/sh_timer.h>
  15 #include <linux/sh_intc.h>
  16 #include <linux/io.h>
  17
  18 static struct plat_sci_port scif0_platform_data = {
  19         .flags          = UPF_BOOT_AUTOCONF,
  20         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
  21         .type           = PORT_SCIF,
  22 };
  23
  24 static struct resource scif0_resources[] = {
  25         DEFINE_RES_MEM(0xff923000, 0x100),
  26         DEFINE_RES_IRQ(evt2irq(0x9a0)),
  27 };
  28
  29 static struct platform_device scif0_device = {
  30         .name           = "sh-sci",
  31         .id             = 0,
  32         .resource       = scif0_resources,
  33         .num_resources  = ARRAY_SIZE(scif0_resources),
  34         .dev            = {
  35                 .platform_data  = &scif0_platform_data,
  36         },
  37 };
  38
  39 static struct plat_sci_port scif1_platform_data = {
  40         .flags          = UPF_BOOT_AUTOCONF,
  41         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
  42         .type           = PORT_SCIF,
  43 };
  44
  45 static struct resource scif1_resources[] = {
  46         DEFINE_RES_MEM(0xff924000, 0x100),
  47         DEFINE_RES_IRQ(evt2irq(0x9c0)),
  48 };
  49
  50 static struct platform_device scif1_device = {
  51         .name           = "sh-sci",
  52         .id             = 1,
  53         .resource       = scif1_resources,
  54         .num_resources  = ARRAY_SIZE(scif1_resources),
  55         .dev            = {
  56                 .platform_data  = &scif1_platform_data,
  57         },
  58 };
  59
  60 static struct plat_sci_port scif2_platform_data = {
  61         .flags          = UPF_BOOT_AUTOCONF,
  62         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
  63         .type           = PORT_SCIF,
  64 };
  65
  66 static struct resource scif2_resources[] = {
  67         DEFINE_RES_MEM(0xff925000, 0x100),
  68         DEFINE_RES_IRQ(evt2irq(0x9e0)),
  69 };
  70
  71 static struct platform_device scif2_device = {
  72         .name           = "sh-sci",
  73         .id             = 2,
  74         .resource       = scif2_resources,
  75         .num_resources  = ARRAY_SIZE(scif2_resources),
  76         .dev            = {
  77                 .platform_data  = &scif2_platform_data,
  78         },
  79 };
  80
  81 static struct plat_sci_port scif3_platform_data = {
  82         .flags          = UPF_BOOT_AUTOCONF,
  83         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
  84         .type           = PORT_SCIF,
  85 };
  86
  87 static struct resource scif3_resources[] = {
  88         DEFINE_RES_MEM(0xff926000, 0x100),
  89         DEFINE_RES_IRQ(evt2irq(0xa00)),
  90 };
  91
  92 static struct platform_device scif3_device = {
  93         .name           = "sh-sci",
  94         .id             = 3,
  95         .resource       = scif3_resources,
  96         .num_resources  = ARRAY_SIZE(scif3_resources),
  97         .dev            = {
  98                 .platform_data  = &scif3_platform_data,
  99         },
 100 };
 101
 102 static struct plat_sci_port scif4_platform_data = {
 103         .flags          = UPF_BOOT_AUTOCONF,
 104         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
 105         .type           = PORT_SCIF,
 106 };
 107
 108 static struct resource scif4_resources[] = {
 109         DEFINE_RES_MEM(0xff927000, 0x100),
 110         DEFINE_RES_IRQ(evt2irq(0xa20)),
 111 };
 112
 113 static struct platform_device scif4_device = {
 114         .name           = "sh-sci",
 115         .id             = 4,
 116         .resource       = scif4_resources,
 117         .num_resources  = ARRAY_SIZE(scif4_resources),
 118         .dev            = {
 119                 .platform_data  = &scif4_platform_data,
 120         },
 121 };
 122
 123 static struct plat_sci_port scif5_platform_data = {
 124         .flags          = UPF_BOOT_AUTOCONF,
 125         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
 126         .type           = PORT_SCIF,
 127 };
 128
 129 static struct resource scif5_resources[] = {
 130         DEFINE_RES_MEM(0xff928000, 0x100),
 131         DEFINE_RES_IRQ(evt2irq(0xa40)),
 132 };
 133
 134 static struct platform_device scif5_device = {
 135         .name           = "sh-sci",
 136         .id             = 5,
 137         .resource       = scif5_resources,
 138         .num_resources  = ARRAY_SIZE(scif5_resources),
 139         .dev            = {
 140                 .platform_data  = &scif5_platform_data,
 141         },
 142 };
 143
 144 static struct plat_sci_port scif6_platform_data = {
 145         .flags          = UPF_BOOT_AUTOCONF,
 146         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
 147         .type           = PORT_SCIF,
 148 };
 149
 150 static struct resource scif6_resources[] = {
 151         DEFINE_RES_MEM(0xff929000, 0x100),
 152         DEFINE_RES_IRQ(evt2irq(0xa60)),
 153 };
 154
 155 static struct platform_device scif6_device = {
 156         .name           = "sh-sci",
 157         .id             = 6,
 158         .resource       = scif6_resources,
 159         .num_resources  = ARRAY_SIZE(scif6_resources),
 160         .dev            = {
 161                 .platform_data  = &scif6_platform_data,
 162         },
 163 };
 164
 165 static struct plat_sci_port scif7_platform_data = {
 166         .flags          = UPF_BOOT_AUTOCONF,
 167         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
 168         .type           = PORT_SCIF,
 169 };
 170
 171 static struct resource scif7_resources[] = {
 172         DEFINE_RES_MEM(0xff92a000, 0x100),
 173         DEFINE_RES_IRQ(evt2irq(0xa80)),
 174 };
 175
 176 static struct platform_device scif7_device = {
 177         .name           = "sh-sci",
 178         .id             = 7,
 179         .resource       = scif7_resources,
 180         .num_resources  = ARRAY_SIZE(scif7_resources),
 181         .dev            = {
 182                 .platform_data  = &scif7_platform_data,
 183         },
 184 };
 185
 186 static struct plat_sci_port scif8_platform_data = {
 187         .flags          = UPF_BOOT_AUTOCONF,
 188         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
 189         .type           = PORT_SCIF,
 190 };
 191
 192 static struct resource scif8_resources[] = {
 193         DEFINE_RES_MEM(0xff92b000, 0x100),
 194         DEFINE_RES_IRQ(evt2irq(0xaa0)),
 195 };
 196
 197 static struct platform_device scif8_device = {
 198         .name           = "sh-sci",
 199         .id             = 8,
 200         .resource       = scif8_resources,
 201         .num_resources  = ARRAY_SIZE(scif8_resources),
 202         .dev            = {
 203                 .platform_data  = &scif8_platform_data,
 204         },
 205 };
 206
 207 static struct plat_sci_port scif9_platform_data = {
 208         .flags          = UPF_BOOT_AUTOCONF,
 209         .scscr          = SCSCR_RE | SCSCR_TE | SCSCR_REIE | SCSCR_TOIE,
 210         .type           = PORT_SCIF,
 211 };
 212
 213 static struct resource scif9_resources[] = {
 214         DEFINE_RES_MEM(0xff92c000, 0x100),
 215         DEFINE_RES_IRQ(evt2irq(0xac0)),
 216 };
 217
 218 static struct platform_device scif9_device = {
 219         .name           = "sh-sci",
 220         .id             = 9,
 221         .resource       = scif9_resources,
 222         .num_resources  = ARRAY_SIZE(scif9_resources),
 223         .dev            = {
 224                 .platform_data  = &scif9_platform_data,
 225         },
 226 };
 227
 228 static struct sh_timer_config tmu0_platform_data = {
 229         .channel_offset = 0x04,
 230         .timer_bit = 0,
 231         .clockevent_rating = 200,
 232 };
 233
 234 static struct resource tmu0_resources[] = {
 235         [0] = {
 236                 .start  = 0xffd80008,
 237                 .end    = 0xffd80013,
 238                 .flags  = IORESOURCE_MEM,
 239         },
 240         [1] = {
 241                 .start  = evt2irq(0x400),
 242                 .flags  = IORESOURCE_IRQ,
 243         },
 244 };
 245
 246 static struct platform_device tmu0_device = {
 247         .name           = "sh_tmu",
 248         .id             = 0,
 249         .dev = {
 250                 .platform_data  = &tmu0_platform_data,
 251         },
 252         .resource       = tmu0_resources,
 253         .num_resources  = ARRAY_SIZE(tmu0_resources),
 254 };
 255
 256 static struct sh_timer_config tmu1_platform_data = {
 257         .channel_offset = 0x10,
 258         .timer_bit = 1,
 259         .clocksource_rating = 200,
 260 };
 261
 262 static struct resource tmu1_resources[] = {
 263         [0] = {
 264                 .start  = 0xffd80014,
 265                 .end    = 0xffd8001f,
 266                 .flags  = IORESOURCE_MEM,
 267         },
 268         [1] = {
 269                 .start  = evt2irq(0x420),
 270                 .flags  = IORESOURCE_IRQ,
 271         },
 272 };
 273
 274 static struct platform_device tmu1_device = {
 275         .name           = "sh_tmu",
 276         .id             = 1,
 277         .dev = {
 278                 .platform_data  = &tmu1_platform_data,
 279         },
 280         .resource       = tmu1_resources,
 281         .num_resources  = ARRAY_SIZE(tmu1_resources),
 282 };
 283
 284 static struct sh_timer_config tmu2_platform_data = {
 285         .channel_offset = 0x1c,
 286         .timer_bit = 2,
 287 };
 288
 289 static struct resource tmu2_resources[] = {
 290         [0] = {
 291                 .start  = 0xffd80020,
 292                 .end    = 0xffd8002f,
 293                 .flags  = IORESOURCE_MEM,
 294         },
 295         [1] = {
 296                 .start  = evt2irq(0x440),
 297                 .flags  = IORESOURCE_IRQ,
 298         },
 299 };
 300
 301 static struct platform_device tmu2_device = {
 302         .name           = "sh_tmu",
 303         .id             = 2,
 304         .dev = {
 305                 .platform_data  = &tmu2_platform_data,
 306         },
 307         .resource       = tmu2_resources,
 308         .num_resources  = ARRAY_SIZE(tmu2_resources),
 309 };
 310
 311 static struct sh_timer_config tmu3_platform_data = {
 312         .channel_offset = 0x04,
 313         .timer_bit = 0,
 314 };
 315
 316 static struct resource tmu3_resources[] = {
 317         [0] = {
 318                 .start  = 0xffd81008,
 319                 .end    = 0xffd81013,
 320                 .flags  = IORESOURCE_MEM,
 321         },
 322         [1] = {
 323                 .start  = evt2irq(0x460),
 324                 .flags  = IORESOURCE_IRQ,
 325         },
 326 };
 327
 328 static struct platform_device tmu3_device = {
 329         .name           = "sh_tmu",
 330         .id             = 3,
 331         .dev = {
 332                 .platform_data  = &tmu3_platform_data,
 333         },
 334         .resource       = tmu3_resources,
 335         .num_resources  = ARRAY_SIZE(tmu3_resources),
 336 };
 337
 338 static struct sh_timer_config tmu4_platform_data = {
 339         .channel_offset = 0x10,
 340         .timer_bit = 1,
 341 };
 342
 343 static struct resource tmu4_resources[] = {
 344         [0] = {
 345                 .start  = 0xffd81014,
 346                 .end    = 0xffd8101f,
 347                 .flags  = IORESOURCE_MEM,
 348         },
 349         [1] = {
 350                 .start  = evt2irq(0x480),
 351                 .flags  = IORESOURCE_IRQ,
 352         },
 353 };
 354
 355 static struct platform_device tmu4_device = {
 356         .name           = "sh_tmu",
 357         .id             = 4,
 358         .dev = {
 359                 .platform_data  = &tmu4_platform_data,
 360         },
 361         .resource       = tmu4_resources,
 362         .num_resources  = ARRAY_SIZE(tmu4_resources),
 363 };
 364
 365 static struct sh_timer_config tmu5_platform_data = {
 366         .channel_offset = 0x1c,
 367         .timer_bit = 2,
 368 };
 369
 370 static struct resource tmu5_resources[] = {
 371         [0] = {
 372                 .start  = 0xffd81020,
 373                 .end    = 0xffd8102f,
 374                 .flags  = IORESOURCE_MEM,
 375         },
 376         [1] = {
 377                 .start  = evt2irq(0x4a0),
 378                 .flags  = IORESOURCE_IRQ,
 379         },
 380 };
 381
 382 static struct platform_device tmu5_device = {
 383         .name           = "sh_tmu",
 384         .id             = 5,
 385         .dev = {
 386                 .platform_data  = &tmu5_platform_data,
 387         },
 388         .resource       = tmu5_resources,
 389         .num_resources  = ARRAY_SIZE(tmu5_resources),
 390 };
 391
 392 static struct sh_timer_config tmu6_platform_data = {
 393         .channel_offset = 0x04,
 394         .timer_bit = 0,
 395 };
 396
 397 static struct resource tmu6_resources[] = {
 398         [0] = {
 399                 .start  = 0xffd82008,
 400                 .end    = 0xffd82013,
 401                 .flags  = IORESOURCE_MEM,
 402         },
 403         [1] = {
 404                 .start  = evt2irq(0x4c0),
 405                 .flags  = IORESOURCE_IRQ,
 406         },
 407 };
 408
 409 static struct platform_device tmu6_device = {
 410         .name           = "sh_tmu",
 411         .id             = 6,
 412         .dev = {
 413                 .platform_data  = &tmu6_platform_data,
 414         },
 415         .resource       = tmu6_resources,
 416         .num_resources  = ARRAY_SIZE(tmu6_resources),
 417 };
 418
 419 static struct sh_timer_config tmu7_platform_data = {
 420         .channel_offset = 0x10,
 421         .timer_bit = 1,
 422 };
 423
 424 static struct resource tmu7_resources[] = {
 425         [0] = {
 426                 .start  = 0xffd82014,
 427                 .end    = 0xffd8201f,
 428                 .flags  = IORESOURCE_MEM,
 429         },
 430         [1] = {
 431                 .start  = evt2irq(0x4e0),
 432                 .flags  = IORESOURCE_IRQ,
 433         },
 434 };
 435
 436 static struct platform_device tmu7_device = {
 437         .name           = "sh_tmu",
 438         .id             = 7,
 439         .dev = {
 440                 .platform_data  = &tmu7_platform_data,
 441         },
 442         .resource       = tmu7_resources,
 443         .num_resources  = ARRAY_SIZE(tmu7_resources),
 444 };
 445
 446 static struct sh_timer_config tmu8_platform_data = {
 447         .channel_offset = 0x1c,
 448         .timer_bit = 2,
 449 };
 450
 451 static struct resource tmu8_resources[] = {
 452         [0] = {
 453                 .start  = 0xffd82020,
 454                 .end    = 0xffd8202b,
 455                 .flags  = IORESOURCE_MEM,
 456         },
 457         [1] = {
 458                 .start  = evt2irq(0x500),
 459                 .flags  = IORESOURCE_IRQ,
 460         },
 461 };
 462
 463 static struct platform_device tmu8_device = {
 464         .name           = "sh_tmu",
 465         .id             = 8,
 466         .dev = {
 467                 .platform_data  = &tmu8_platform_data,
 468         },
 469         .resource       = tmu8_resources,
 470         .num_resources  = ARRAY_SIZE(tmu8_resources),
 471 };
 472
 473 static struct platform_device *sh7770_devices[] __initdata = {
 474         &scif0_device,
 475         &scif1_device,
 476         &scif2_device,
 477         &scif3_device,
 478         &scif4_device,
 479         &scif5_device,
 480         &scif6_device,
 481         &scif7_device,
 482         &scif8_device,
 483         &scif9_device,
 484         &tmu0_device,
 485         &tmu1_device,
 486         &tmu2_device,
 487         &tmu3_device,
 488         &tmu4_device,
 489         &tmu5_device,
 490         &tmu6_device,
 491         &tmu7_device,
 492         &tmu8_device,
 493 };
 494
 495 static int __init sh7770_devices_setup(void)
 496 {
 497         return platform_add_devices(sh7770_devices,
 498                                     ARRAY_SIZE(sh7770_devices));
 499 }
 500 arch_initcall(sh7770_devices_setup);
 501
 502 static struct platform_device *sh7770_early_devices[] __initdata = {
 503         &scif0_device,
 504         &scif1_device,
 505         &scif2_device,
 506         &scif3_device,
 507         &scif4_device,
 508         &scif5_device,
 509         &scif6_device,
 510         &scif7_device,
 511         &scif8_device,
 512         &scif9_device,
 513         &tmu0_device,
 514         &tmu1_device,
 515         &tmu2_device,
 516         &tmu3_device,
 517         &tmu4_device,
 518         &tmu5_device,
 519         &tmu6_device,
 520         &tmu7_device,
 521         &tmu8_device,
 522 };
 523
 524 void __init plat_early_device_setup(void)
 525 {
 526         early_platform_add_devices(sh7770_early_devices,
 527                                    ARRAY_SIZE(sh7770_early_devices));
 528 }
 529
 530 enum {
 531         UNUSED = 0,
 532
 533         /* interrupt sources */
 534         IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 535         IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 536         IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 537         IRL_HHLL, IRL_HHLH, IRL_HHHL,
 538
 539         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
 540
 541         GPIO,
 542         TMU0, TMU1, TMU2, TMU2_TICPI,
 543         TMU3, TMU4, TMU5, TMU5_TICPI,
 544         TMU6, TMU7, TMU8,
 545         HAC, IPI, SPDIF, HUDI, I2C,
 546         DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2,
 547         I2S0, I2S1, I2S2, I2S3,
 548         SRC_RX, SRC_TX, SRC_SPDIF,
 549         DU, VIDEO_IN, REMOTE, YUV, USB, ATAPI, CAN, GPS, GFX2D,
 550         GFX3D_MBX, GFX3D_DMAC,
 551         EXBUS_ATA,
 552         SPI0, SPI1,
 553         SCIF089, SCIF1234, SCIF567,
 554         ADC,
 555         BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14,
 556         BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27,
 557         BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31,
 558
 559         /* interrupt groups */
 560         TMU, DMAC, I2S, SRC, GFX3D, SPI, SCIF, BBDMAC,
 561 };
 562
 563 static struct intc_vect vectors[] __initdata = {
 564         INTC_VECT(GPIO, 0x3e0),
 565         INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
 566         INTC_VECT(TMU2, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
 567         INTC_VECT(TMU3, 0x480), INTC_VECT(TMU4, 0x4a0),
 568         INTC_VECT(TMU5, 0x4c0), INTC_VECT(TMU5_TICPI, 0x4e0),
 569         INTC_VECT(TMU6, 0x500), INTC_VECT(TMU7, 0x520),
 570         INTC_VECT(TMU8, 0x540),
 571         INTC_VECT(HAC, 0x580), INTC_VECT(IPI, 0x5c0),
 572         INTC_VECT(SPDIF, 0x5e0),
 573         INTC_VECT(HUDI, 0x600), INTC_VECT(I2C, 0x620),
 574         INTC_VECT(DMAC0_DMINT0, 0x640), INTC_VECT(DMAC0_DMINT1, 0x660),
 575         INTC_VECT(DMAC0_DMINT2, 0x680),
 576         INTC_VECT(I2S0, 0x6a0), INTC_VECT(I2S1, 0x6c0),
 577         INTC_VECT(I2S2, 0x6e0), INTC_VECT(I2S3, 0x700),
 578         INTC_VECT(SRC_RX, 0x720), INTC_VECT(SRC_TX, 0x740),
 579         INTC_VECT(SRC_SPDIF, 0x760),
 580         INTC_VECT(DU, 0x780), INTC_VECT(VIDEO_IN, 0x7a0),
 581         INTC_VECT(REMOTE, 0x7c0), INTC_VECT(YUV, 0x7e0),
 582         INTC_VECT(USB, 0x840), INTC_VECT(ATAPI, 0x860),
 583         INTC_VECT(CAN, 0x880), INTC_VECT(GPS, 0x8a0),
 584         INTC_VECT(GFX2D, 0x8c0),
 585         INTC_VECT(GFX3D_MBX, 0x900), INTC_VECT(GFX3D_DMAC, 0x920),
 586         INTC_VECT(EXBUS_ATA, 0x940),
 587         INTC_VECT(SPI0, 0x960), INTC_VECT(SPI1, 0x980),
 588         INTC_VECT(SCIF089, 0x9a0), INTC_VECT(SCIF1234, 0x9c0),
 589         INTC_VECT(SCIF1234, 0x9e0), INTC_VECT(SCIF1234, 0xa00),
 590         INTC_VECT(SCIF1234, 0xa20), INTC_VECT(SCIF567, 0xa40),
 591         INTC_VECT(SCIF567, 0xa60), INTC_VECT(SCIF567, 0xa80),
 592         INTC_VECT(SCIF089, 0xaa0), INTC_VECT(SCIF089, 0xac0),
 593         INTC_VECT(ADC, 0xb20),
 594         INTC_VECT(BBDMAC_0_3, 0xba0), INTC_VECT(BBDMAC_0_3, 0xbc0),
 595         INTC_VECT(BBDMAC_0_3, 0xbe0), INTC_VECT(BBDMAC_0_3, 0xc00),
 596         INTC_VECT(BBDMAC_4_7, 0xc20), INTC_VECT(BBDMAC_4_7, 0xc40),
 597         INTC_VECT(BBDMAC_4_7, 0xc60), INTC_VECT(BBDMAC_4_7, 0xc80),
 598         INTC_VECT(BBDMAC_8_10, 0xca0), INTC_VECT(BBDMAC_8_10, 0xcc0),
 599         INTC_VECT(BBDMAC_8_10, 0xce0), INTC_VECT(BBDMAC_11_14, 0xd00),
 600         INTC_VECT(BBDMAC_11_14, 0xd20), INTC_VECT(BBDMAC_11_14, 0xd40),
 601         INTC_VECT(BBDMAC_11_14, 0xd60), INTC_VECT(BBDMAC_15_18, 0xd80),
 602         INTC_VECT(BBDMAC_15_18, 0xda0), INTC_VECT(BBDMAC_15_18, 0xdc0),
 603         INTC_VECT(BBDMAC_15_18, 0xde0), INTC_VECT(BBDMAC_19_22, 0xe00),
 604         INTC_VECT(BBDMAC_19_22, 0xe20), INTC_VECT(BBDMAC_19_22, 0xe40),
 605         INTC_VECT(BBDMAC_19_22, 0xe60), INTC_VECT(BBDMAC_23_26, 0xe80),
 606         INTC_VECT(BBDMAC_23_26, 0xea0), INTC_VECT(BBDMAC_23_26, 0xec0),
 607         INTC_VECT(BBDMAC_23_26, 0xee0), INTC_VECT(BBDMAC_27, 0xf00),
 608         INTC_VECT(BBDMAC_28, 0xf20), INTC_VECT(BBDMAC_29, 0xf40),
 609         INTC_VECT(BBDMAC_30, 0xf60), INTC_VECT(BBDMAC_31, 0xf80),
 610 };
 611
 612 static struct intc_group groups[] __initdata = {
 613         INTC_GROUP(TMU, TMU0, TMU1, TMU2, TMU2_TICPI, TMU3, TMU4, TMU5,
 614                    TMU5_TICPI, TMU6, TMU7, TMU8),
 615         INTC_GROUP(DMAC, DMAC0_DMINT0, DMAC0_DMINT1, DMAC0_DMINT2),
 616         INTC_GROUP(I2S, I2S0, I2S1, I2S2, I2S3),
 617         INTC_GROUP(SRC, SRC_RX, SRC_TX, SRC_SPDIF),
 618         INTC_GROUP(GFX3D, GFX3D_MBX, GFX3D_DMAC),
 619         INTC_GROUP(SPI, SPI0, SPI1),
 620         INTC_GROUP(SCIF, SCIF089, SCIF1234, SCIF567),
 621         INTC_GROUP(BBDMAC,
 622                    BBDMAC_0_3, BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14,
 623                    BBDMAC_15_18, BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27,
 624                    BBDMAC_28, BBDMAC_29, BBDMAC_30, BBDMAC_31),
 625 };
 626
 627 static struct intc_mask_reg mask_registers[] __initdata = {
 628         { 0xffe00040, 0xffe00044, 32, /* INT2MSKR / INT2MSKCR */
 629           { 0, BBDMAC, ADC, SCIF, SPI, EXBUS_ATA, GFX3D, GFX2D,
 630             GPS, CAN, ATAPI, USB, YUV, REMOTE, VIDEO_IN, DU, SRC, I2S,
 631             DMAC, I2C, HUDI, SPDIF, IPI, HAC, TMU, GPIO } },
 632 };
 633
 634 static struct intc_prio_reg prio_registers[] __initdata = {
 635         { 0xffe00000, 0, 32, 8, /* INT2PRI0 */ { GPIO, TMU0, 0, HAC } },
 636         { 0xffe00004, 0, 32, 8, /* INT2PRI1 */ { IPI, SPDIF, HUDI, I2C } },
 637         { 0xffe00008, 0, 32, 8, /* INT2PRI2 */ { DMAC, I2S, SRC, DU } },
 638         { 0xffe0000c, 0, 32, 8, /* INT2PRI3 */ { VIDEO_IN, REMOTE, YUV, USB } },
 639         { 0xffe00010, 0, 32, 8, /* INT2PRI4 */ { ATAPI, CAN, GPS, GFX2D } },
 640         { 0xffe00014, 0, 32, 8, /* INT2PRI5 */ { 0, GFX3D, EXBUS_ATA, SPI } },
 641         { 0xffe00018, 0, 32, 8, /* INT2PRI6 */ { SCIF1234, SCIF567, SCIF089 } },
 642         { 0xffe0001c, 0, 32, 8, /* INT2PRI7 */ { ADC, 0, 0, BBDMAC_0_3 } },
 643         { 0xffe00020, 0, 32, 8, /* INT2PRI8 */
 644           { BBDMAC_4_7, BBDMAC_8_10, BBDMAC_11_14, BBDMAC_15_18 } },
 645         { 0xffe00024, 0, 32, 8, /* INT2PRI9 */
 646           { BBDMAC_19_22, BBDMAC_23_26, BBDMAC_27, BBDMAC_28 } },
 647         { 0xffe00028, 0, 32, 8, /* INT2PRI10 */
 648           { BBDMAC_29, BBDMAC_30, BBDMAC_31 } },
 649         { 0xffe0002c, 0, 32, 8, /* INT2PRI11 */
 650           { TMU1, TMU2, TMU2_TICPI, TMU3 } },
 651         { 0xffe00030, 0, 32, 8, /* INT2PRI12 */
 652           { TMU4, TMU5, TMU5_TICPI, TMU6 } },
 653         { 0xffe00034, 0, 32, 8, /* INT2PRI13 */
 654           { TMU7, TMU8 } },
 655 };
 656
 657 static DECLARE_INTC_DESC(intc_desc, "sh7770", vectors, groups,
 658                          mask_registers, prio_registers, NULL);
 659
 660 /* Support for external interrupt pins in IRQ mode */
 661 static struct intc_vect irq_vectors[] __initdata = {
 662         INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
 663         INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
 664         INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
 665 };
 666
 667 static struct intc_mask_reg irq_mask_registers[] __initdata = {
 668         { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
 669           { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, } },
 670 };
 671
 672 static struct intc_prio_reg irq_prio_registers[] __initdata = {
 673         { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0, IRQ1, IRQ2, IRQ3,
 674                                                IRQ4, IRQ5, } },
 675 };
 676
 677 static struct intc_sense_reg irq_sense_registers[] __initdata = {
 678         { 0xffd0001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
 679                                             IRQ4, IRQ5, } },
 680 };
 681
 682 static DECLARE_INTC_DESC(intc_irq_desc, "sh7770-irq", irq_vectors,
 683                          NULL, irq_mask_registers, irq_prio_registers,
 684                          irq_sense_registers);
 685
 686 /* External interrupt pins in IRL mode */
 687 static struct intc_vect irl_vectors[] __initdata = {
 688         INTC_VECT(IRL_LLLL, 0x200), INTC_VECT(IRL_LLLH, 0x220),
 689         INTC_VECT(IRL_LLHL, 0x240), INTC_VECT(IRL_LLHH, 0x260),
 690         INTC_VECT(IRL_LHLL, 0x280), INTC_VECT(IRL_LHLH, 0x2a0),
 691         INTC_VECT(IRL_LHHL, 0x2c0), INTC_VECT(IRL_LHHH, 0x2e0),
 692         INTC_VECT(IRL_HLLL, 0x300), INTC_VECT(IRL_HLLH, 0x320),
 693         INTC_VECT(IRL_HLHL, 0x340), INTC_VECT(IRL_HLHH, 0x360),
 694         INTC_VECT(IRL_HHLL, 0x380), INTC_VECT(IRL_HHLH, 0x3a0),
 695         INTC_VECT(IRL_HHHL, 0x3c0),
 696 };
 697
 698 static struct intc_mask_reg irl3210_mask_registers[] __initdata = {
 699         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 700           { IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 701             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 702             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 703             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 704 };
 705
 706 static struct intc_mask_reg irl7654_mask_registers[] __initdata = {
 707         { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
 708           { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
 709             IRL_LLLL, IRL_LLLH, IRL_LLHL, IRL_LLHH,
 710             IRL_LHLL, IRL_LHLH, IRL_LHHL, IRL_LHHH,
 711             IRL_HLLL, IRL_HLLH, IRL_HLHL, IRL_HLHH,
 712             IRL_HHLL, IRL_HHLH, IRL_HHHL, } },
 713 };
 714
 715 static DECLARE_INTC_DESC(intc_irl7654_desc, "sh7780-irl7654", irl_vectors,
 716                          NULL, irl7654_mask_registers, NULL, NULL);
 717
 718 static DECLARE_INTC_DESC(intc_irl3210_desc, "sh7780-irl3210", irl_vectors,
 719                          NULL, irl3210_mask_registers, NULL, NULL);
 720
 721 #define INTC_ICR0       0xffd00000
 722 #define INTC_INTMSK0    0xffd00044
 723 #define INTC_INTMSK1    0xffd00048
 724 #define INTC_INTMSK2    0xffd40080
 725 #define INTC_INTMSKCLR1 0xffd00068
 726 #define INTC_INTMSKCLR2 0xffd40084
 727
 728 void __init plat_irq_setup(void)
 729 {
 730         /* disable IRQ7-0 */
 731         __raw_writel(0xff000000, INTC_INTMSK0);
 732
 733         /* disable IRL3-0 + IRL7-4 */
 734         __raw_writel(0xc0000000, INTC_INTMSK1);
 735         __raw_writel(0xfffefffe, INTC_INTMSK2);
 736
 737         /* select IRL mode for IRL3-0 + IRL7-4 */
 738         __raw_writel(__raw_readl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
 739
 740         /* disable holding function, ie enable "SH-4 Mode" */
 741         __raw_writel(__raw_readl(INTC_ICR0) | 0x00200000, INTC_ICR0);
 742
 743         register_intc_controller(&intc_desc);
 744 }
 745
 746 void __init plat_irq_setup_pins(int mode)
 747 {
 748         switch (mode) {
 749         case IRQ_MODE_IRQ:
 750                 /* select IRQ mode for IRL3-0 + IRL7-4 */
 751                 __raw_writel(__raw_readl(INTC_ICR0) | 0x00c00000, INTC_ICR0);
 752                 register_intc_controller(&intc_irq_desc);
 753                 break;
 754         case IRQ_MODE_IRL7654:
 755                 /* enable IRL7-4 but don't provide any masking */
 756                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 757                 __raw_writel(0x0000fffe, INTC_INTMSKCLR2);
 758                 break;
 759         case IRQ_MODE_IRL3210:
 760                 /* enable IRL0-3 but don't provide any masking */
 761                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 762                 __raw_writel(0xfffe0000, INTC_INTMSKCLR2);
 763                 break;
 764         case IRQ_MODE_IRL7654_MASK:
 765                 /* enable IRL7-4 and mask using cpu intc controller */
 766                 __raw_writel(0x40000000, INTC_INTMSKCLR1);
 767                 register_intc_controller(&intc_irl7654_desc);
 768                 break;
 769         case IRQ_MODE_IRL3210_MASK:
 770                 /* enable IRL0-3 and mask using cpu intc controller */
 771                 __raw_writel(0x80000000, INTC_INTMSKCLR1);
 772                 register_intc_controller(&intc_irl3210_desc);
 773                 break;
 774         default:
 775                 BUG();
 776         }
 777 }