4 * Copyright (C) 2006 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/platform_device.h>
11 #include <linux/init.h>
12 #include <linux/serial.h>
15 static struct resource rtc_resources
[] = {
18 .end
= 0xffe80000 + 0x58 - 1,
19 .flags
= IORESOURCE_IO
,
24 .flags
= IORESOURCE_IRQ
,
29 .flags
= IORESOURCE_IRQ
,
34 .flags
= IORESOURCE_IRQ
,
38 static struct platform_device rtc_device
= {
41 .num_resources
= ARRAY_SIZE(rtc_resources
),
42 .resource
= rtc_resources
,
45 static struct plat_sci_port sci_platform_data
[] = {
47 .mapbase
= 0xffe00000,
48 .flags
= UPF_BOOT_AUTOCONF
,
50 .irqs
= { 40, 41, 43, 42 },
52 .mapbase
= 0xffe10000,
53 .flags
= UPF_BOOT_AUTOCONF
,
55 .irqs
= { 76, 77, 79, 78 },
61 static struct platform_device sci_device
= {
65 .platform_data
= sci_platform_data
,
69 static struct platform_device
*sh7780_devices
[] __initdata
= {
74 static int __init
sh7780_devices_setup(void)
76 return platform_add_devices(sh7780_devices
,
77 ARRAY_SIZE(sh7780_devices
));
79 __initcall(sh7780_devices_setup
);
84 /* interrupt sources */
86 IRL_LLLL
, IRL_LLLH
, IRL_LLHL
, IRL_LLHH
,
87 IRL_LHLL
, IRL_LHLH
, IRL_LHHL
, IRL_LHHH
,
88 IRL_HLLL
, IRL_HLLH
, IRL_HLHL
, IRL_HLHH
,
89 IRL_HHLL
, IRL_HHLH
, IRL_HHHL
,
91 IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
,
92 RTC_ATI
, RTC_PRI
, RTC_CUI
,
94 TMU0
, TMU1
, TMU2
, TMU2_TICPI
,
96 DMAC0_DMINT0
, DMAC0_DMINT1
, DMAC0_DMINT2
, DMAC0_DMINT3
, DMAC0_DMAE
,
97 SCIF0_ERI
, SCIF0_RXI
, SCIF0_BRI
, SCIF0_TXI
,
98 DMAC0_DMINT4
, DMAC0_DMINT5
, DMAC1_DMINT6
, DMAC1_DMINT7
,
100 PCISERR
, PCIINTA
, PCIINTB
, PCIINTC
, PCIINTD
,
101 PCIERR
, PCIPWD3
, PCIPWD2
, PCIPWD1
, PCIPWD0
,
102 SCIF1_ERI
, SCIF1_RXI
, SCIF1_BRI
, SCIF1_TXI
,
104 MMCIF_FSTAT
, MMCIF_TRAN
, MMCIF_ERR
, MMCIF_FRDY
,
105 DMAC1_DMINT8
, DMAC1_DMINT9
, DMAC1_DMINT10
, DMAC1_DMINT11
,
108 FLCTL_FLSTE
, FLCTL_FLEND
, FLCTL_FLTRQ0
, FLCTL_FLTRQ1
,
109 GPIOI0
, GPIOI1
, GPIOI2
, GPIOI3
,
111 /* interrupt groups */
113 RTC
, TMU012
, DMAC0
, SCIF0
, DMAC45
, DMAC1
,
114 PCIC5
, SCIF1
, MMCIF
, TMU345
, FLCTL
, GPIO
,
117 static struct intc_vect vectors
[] = {
118 INTC_VECT(RTC_ATI
, 0x480), INTC_VECT(RTC_PRI
, 0x4a0),
119 INTC_VECT(RTC_CUI
, 0x4c0),
120 INTC_VECT(WDT
, 0x560),
121 INTC_VECT(TMU0
, 0x580), INTC_VECT(TMU1
, 0x5a0),
122 INTC_VECT(TMU2
, 0x5c0), INTC_VECT(TMU2_TICPI
, 0x5e0),
123 INTC_VECT(HUDI
, 0x600),
124 INTC_VECT(DMAC0_DMINT0
, 0x640), INTC_VECT(DMAC0_DMINT1
, 0x660),
125 INTC_VECT(DMAC0_DMINT2
, 0x680), INTC_VECT(DMAC0_DMINT3
, 0x6a0),
126 INTC_VECT(DMAC0_DMAE
, 0x6c0),
127 INTC_VECT(SCIF0_ERI
, 0x700), INTC_VECT(SCIF0_RXI
, 0x720),
128 INTC_VECT(SCIF0_BRI
, 0x740), INTC_VECT(SCIF0_TXI
, 0x760),
129 INTC_VECT(DMAC0_DMINT4
, 0x780), INTC_VECT(DMAC0_DMINT5
, 0x7a0),
130 INTC_VECT(DMAC1_DMINT6
, 0x7c0), INTC_VECT(DMAC1_DMINT7
, 0x7e0),
131 INTC_VECT(CMT
, 0x900), INTC_VECT(HAC
, 0x980),
132 INTC_VECT(PCISERR
, 0xa00), INTC_VECT(PCIINTA
, 0xa20),
133 INTC_VECT(PCIINTB
, 0xa40), INTC_VECT(PCIINTC
, 0xa60),
134 INTC_VECT(PCIINTD
, 0xa80), INTC_VECT(PCIERR
, 0xaa0),
135 INTC_VECT(PCIPWD3
, 0xac0), INTC_VECT(PCIPWD2
, 0xae0),
136 INTC_VECT(PCIPWD1
, 0xb00), INTC_VECT(PCIPWD0
, 0xb20),
137 INTC_VECT(SCIF1_ERI
, 0xb80), INTC_VECT(SCIF1_RXI
, 0xba0),
138 INTC_VECT(SCIF1_BRI
, 0xbc0), INTC_VECT(SCIF1_TXI
, 0xbe0),
139 INTC_VECT(SIOF
, 0xc00), INTC_VECT(HSPI
, 0xc80),
140 INTC_VECT(MMCIF_FSTAT
, 0xd00), INTC_VECT(MMCIF_TRAN
, 0xd20),
141 INTC_VECT(MMCIF_ERR
, 0xd40), INTC_VECT(MMCIF_FRDY
, 0xd60),
142 INTC_VECT(DMAC1_DMINT8
, 0xd80), INTC_VECT(DMAC1_DMINT9
, 0xda0),
143 INTC_VECT(DMAC1_DMINT10
, 0xdc0), INTC_VECT(DMAC1_DMINT11
, 0xde0),
144 INTC_VECT(TMU3
, 0xe00), INTC_VECT(TMU4
, 0xe20),
145 INTC_VECT(TMU5
, 0xe40),
146 INTC_VECT(SSI
, 0xe80),
147 INTC_VECT(FLCTL_FLSTE
, 0xf00), INTC_VECT(FLCTL_FLEND
, 0xf20),
148 INTC_VECT(FLCTL_FLTRQ0
, 0xf40), INTC_VECT(FLCTL_FLTRQ1
, 0xf60),
149 INTC_VECT(GPIOI0
, 0xf80), INTC_VECT(GPIOI1
, 0xfa0),
150 INTC_VECT(GPIOI2
, 0xfc0), INTC_VECT(GPIOI3
, 0xfe0),
153 static struct intc_group groups
[] = {
154 INTC_GROUP(RTC
, RTC_ATI
, RTC_PRI
, RTC_CUI
),
155 INTC_GROUP(TMU012
, TMU0
, TMU1
, TMU2
, TMU2_TICPI
),
156 INTC_GROUP(DMAC0
, DMAC0_DMINT0
, DMAC0_DMINT1
, DMAC0_DMINT2
,
157 DMAC0_DMINT3
, DMAC0_DMINT4
, DMAC0_DMINT5
, DMAC0_DMAE
),
158 INTC_GROUP(SCIF0
, SCIF0_ERI
, SCIF0_RXI
, SCIF0_BRI
, SCIF0_TXI
),
159 INTC_GROUP(DMAC1
, DMAC1_DMINT6
, DMAC1_DMINT7
, DMAC1_DMINT8
,
160 DMAC1_DMINT9
, DMAC1_DMINT10
, DMAC1_DMINT11
),
161 INTC_GROUP(PCIC5
, PCIERR
, PCIPWD3
, PCIPWD2
, PCIPWD1
, PCIPWD0
),
162 INTC_GROUP(SCIF1
, SCIF1_ERI
, SCIF1_RXI
, SCIF1_BRI
, SCIF1_TXI
),
163 INTC_GROUP(MMCIF
, MMCIF_FSTAT
, MMCIF_TRAN
, MMCIF_ERR
, MMCIF_FRDY
),
164 INTC_GROUP(TMU345
, TMU3
, TMU4
, TMU5
),
165 INTC_GROUP(FLCTL
, FLCTL_FLSTE
, FLCTL_FLEND
,
166 FLCTL_FLTRQ0
, FLCTL_FLTRQ1
),
167 INTC_GROUP(GPIO
, GPIOI0
, GPIOI1
, GPIOI2
, GPIOI3
),
170 static struct intc_prio priorities
[] = {
175 static struct intc_mask_reg mask_registers
[] = {
176 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
177 { 0, 0, 0, 0, 0, 0, GPIO
, FLCTL
,
178 SSI
, MMCIF
, HSPI
, SIOF
, PCIC5
, PCIINTD
, PCIINTC
, PCIINTB
,
179 PCIINTA
, PCISERR
, HAC
, CMT
, 0, 0, DMAC1
, DMAC0
,
180 HUDI
, 0, WDT
, SCIF1
, SCIF0
, RTC
, TMU345
, TMU012
} },
183 static struct intc_prio_reg prio_registers
[] = {
184 { 0xffd40000, 0, 32, 8, /* INT2PRI0 */ { TMU0
, TMU1
,
185 TMU2
, TMU2_TICPI
} },
186 { 0xffd40004, 0, 32, 8, /* INT2PRI1 */ { TMU3
, TMU4
, TMU5
, RTC
} },
187 { 0xffd40008, 0, 32, 8, /* INT2PRI2 */ { SCIF0
, SCIF1
, WDT
} },
188 { 0xffd4000c, 0, 32, 8, /* INT2PRI3 */ { HUDI
, DMAC0
, DMAC1
} },
189 { 0xffd40010, 0, 32, 8, /* INT2PRI4 */ { CMT
, HAC
,
190 PCISERR
, PCIINTA
, } },
191 { 0xffd40014, 0, 32, 8, /* INT2PRI5 */ { PCIINTB
, PCIINTC
,
193 { 0xffd40018, 0, 32, 8, /* INT2PRI6 */ { SIOF
, HSPI
, MMCIF
, SSI
} },
194 { 0xffd4001c, 0, 32, 8, /* INT2PRI7 */ { FLCTL
, GPIO
} },
197 static DECLARE_INTC_DESC(intc_desc
, "sh7780", vectors
, groups
, priorities
,
198 mask_registers
, prio_registers
, NULL
);
200 /* Support for external interrupt pins in IRQ mode */
202 static struct intc_vect irq_vectors
[] = {
203 INTC_VECT(IRQ0
, 0x240), INTC_VECT(IRQ1
, 0x280),
204 INTC_VECT(IRQ2
, 0x2c0), INTC_VECT(IRQ3
, 0x300),
205 INTC_VECT(IRQ4
, 0x340), INTC_VECT(IRQ5
, 0x380),
206 INTC_VECT(IRQ6
, 0x3c0), INTC_VECT(IRQ7
, 0x200),
209 static struct intc_mask_reg irq_mask_registers
[] = {
210 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
211 { IRQ0
, IRQ1
, IRQ2
, IRQ3
, IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
214 static struct intc_prio_reg irq_prio_registers
[] = {
215 { 0xffd00010, 0, 32, 4, /* INTPRI */ { IRQ0
, IRQ1
, IRQ2
, IRQ3
,
216 IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
219 static struct intc_sense_reg irq_sense_registers
[] = {
220 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0
, IRQ1
, IRQ2
, IRQ3
,
221 IRQ4
, IRQ5
, IRQ6
, IRQ7
} },
224 static DECLARE_INTC_DESC(intc_irq_desc
, "sh7780-irq", irq_vectors
,
225 NULL
, NULL
, irq_mask_registers
, irq_prio_registers
,
226 irq_sense_registers
);
228 /* External interrupt pins in IRL mode */
230 static struct intc_vect irl_vectors
[] = {
231 INTC_VECT(IRL_LLLL
, 0x200), INTC_VECT(IRL_LLLH
, 0x220),
232 INTC_VECT(IRL_LLHL
, 0x240), INTC_VECT(IRL_LLHH
, 0x260),
233 INTC_VECT(IRL_LHLL
, 0x280), INTC_VECT(IRL_LHLH
, 0x2a0),
234 INTC_VECT(IRL_LHHL
, 0x2c0), INTC_VECT(IRL_LHHH
, 0x2e0),
235 INTC_VECT(IRL_HLLL
, 0x300), INTC_VECT(IRL_HLLH
, 0x320),
236 INTC_VECT(IRL_HLHL
, 0x340), INTC_VECT(IRL_HLHH
, 0x360),
237 INTC_VECT(IRL_HHLL
, 0x380), INTC_VECT(IRL_HHLH
, 0x3a0),
238 INTC_VECT(IRL_HHHL
, 0x3c0),
241 static struct intc_mask_reg irl3210_mask_registers
[] = {
242 { 0xffd00080, 0xffd00084, 32, /* INTMSK2 / INTMSKCLR2 */
243 { IRL_LLLL
, IRL_LLLH
, IRL_LLHL
, IRL_LLHH
,
244 IRL_LHLL
, IRL_LHLH
, IRL_LHHL
, IRL_LHHH
,
245 IRL_HLLL
, IRL_HLLH
, IRL_HLHL
, IRL_HLHH
,
246 IRL_HHLL
, IRL_HHLH
, IRL_HHHL
, } },
249 static struct intc_mask_reg irl7654_mask_registers
[] = {
250 { 0xffd00080, 0xffd00084, 32, /* INTMSK2 / INTMSKCLR2 */
251 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
252 IRL_LLLL
, IRL_LLLH
, IRL_LLHL
, IRL_LLHH
,
253 IRL_LHLL
, IRL_LHLH
, IRL_LHHL
, IRL_LHHH
,
254 IRL_HLLL
, IRL_HLLH
, IRL_HLHL
, IRL_HLHH
,
255 IRL_HHLL
, IRL_HHLH
, IRL_HHHL
, } },
258 static DECLARE_INTC_DESC(intc_irl7654_desc
, "sh7780-irl7654", irl_vectors
,
259 NULL
, NULL
, irl7654_mask_registers
, NULL
, NULL
);
261 static DECLARE_INTC_DESC(intc_irl3210_desc
, "sh7780-irl3210", irl_vectors
,
262 NULL
, NULL
, irl3210_mask_registers
, NULL
, NULL
);
264 void __init
plat_irq_setup(void)
266 register_intc_controller(&intc_desc
);
269 void __init
plat_irq_setup_pins(int mode
)
273 register_intc_controller(&intc_irq_desc
);
275 case IRQ_MODE_IRL7654
:
276 register_intc_controller(&intc_irl7654_desc
);
278 case IRQ_MODE_IRL3210
:
279 register_intc_controller(&intc_irl3210_desc
);