2 * arch/sh/kernel/timers/timer-mtu2.c - MTU2 Timer Support
4 * Copyright (C) 2005 Paul Mundt
6 * Based off of arch/sh/kernel/timers/timer-tmu.c
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <linux/interrupt.h>
15 #include <linux/spinlock.h>
16 #include <linux/seqlock.h>
17 #include <asm/timer.h>
20 #include <asm/clock.h>
23 * We use channel 1 for our lowly system timer. Channel 2 would be the other
24 * likely candidate, but we leave it alone as it has higher divisors that
25 * would be of more use to other more interesting applications.
27 * TODO: Presently we only implement a 16-bit single-channel system timer.
28 * However, we can implement channel cascade if we go the overflow route and
29 * get away with using 2 MTU2 channels as a 32-bit timer.
32 static DEFINE_SPINLOCK(mtu2_lock
);
34 #define MTU2_TSTR 0xfffe4280
35 #define MTU2_TCR_1 0xfffe4380
36 #define MTU2_TMDR_1 0xfffe4381
37 #define MTU2_TIOR_1 0xfffe4382
38 #define MTU2_TIER_1 0xfffe4384
39 #define MTU2_TSR_1 0xfffe4385
40 #define MTU2_TCNT_1 0xfffe4386 /* 16-bit counter */
41 #define MTU2_TGRA_1 0xfffe438a
43 #define STBCR3 0xfffe0408
45 #define MTU2_TSTR_CST1 (1 << 1) /* Counter Start 1 */
47 #define MTU2_TSR_TGFA (1 << 0) /* GRA compare match */
49 #define MTU2_TIER_TGIEA (1 << 0) /* GRA compare match interrupt enable */
51 #define MTU2_TCR_INIT 0x22
53 #define MTU2_TCR_CALIB 0x00
55 static unsigned long mtu2_timer_get_offset(void)
60 static int count_p
= 0x7fff; /* for the first call after boot */
61 static unsigned long jiffies_p
= 0;
64 * cache volatile jiffies temporarily; we have IRQs turned off.
66 unsigned long jiffies_t
;
68 spin_lock_irqsave(&mtu2_lock
, flags
);
69 /* timer count may underflow right here */
70 count
= ctrl_inw(MTU2_TCNT_1
); /* read the latched count */
75 * avoiding timer inconsistencies (they are rare, but they happen)...
76 * there is one kind of problem that must be avoided here:
77 * 1. the timer counter underflows
80 if (jiffies_t
== jiffies_p
) {
81 if (count
> count_p
) {
82 if (ctrl_inb(MTU2_TSR_1
) & MTU2_TSR_TGFA
) {
85 printk("%s (): hardware timer problem?\n",
90 jiffies_p
= jiffies_t
;
93 spin_unlock_irqrestore(&mtu2_lock
, flags
);
95 count
= ((LATCH
-1) - count
) * TICK_SIZE
;
96 count
= (count
+ LATCH
/2) / LATCH
;
101 static irqreturn_t
mtu2_timer_interrupt(int irq
, void *dev_id
,
102 struct pt_regs
*regs
)
104 unsigned long timer_status
;
107 timer_status
= ctrl_inb(MTU2_TSR_1
);
108 timer_status
&= ~MTU2_TSR_TGFA
;
109 ctrl_outb(timer_status
, MTU2_TSR_1
);
112 write_seqlock(&xtime_lock
);
113 handle_timer_tick(regs
);
114 write_sequnlock(&xtime_lock
);
119 static struct irqaction mtu2_irq
= {
121 .handler
= mtu2_timer_interrupt
,
122 .flags
= SA_INTERRUPT
,
123 .mask
= CPU_MASK_NONE
,
127 * Hah! We'll see if this works (switching from usecs to nsecs).
129 static unsigned long mtu2_timer_get_frequency(void)
132 struct timespec ts1
, ts2
;
133 unsigned long diff_nsec
;
134 unsigned long factor
;
136 /* Setup the timer: We don't want to generate interrupts, just
137 * have it count down at its natural rate.
140 ctrl_outb(ctrl_inb(MTU2_TSTR
) & ~MTU2_TSTR_CST1
, MTU2_TSTR
);
141 ctrl_outb(MTU2_TCR_CALIB
, MTU2_TCR_1
);
142 ctrl_outb(ctrl_inb(MTU2_TIER_1
) & ~MTU2_TIER_TGIEA
, MTU2_TIER_1
);
143 ctrl_outw(0, MTU2_TCNT_1
);
149 } while (ts1
.tv_nsec
== ts2
.tv_nsec
&& ts1
.tv_sec
== ts2
.tv_sec
);
151 /* actually start the timer */
152 ctrl_outw(ctrl_inw(CMT_CMSTR
) | 0x01, CMT_CMSTR
);
156 } while (ts1
.tv_nsec
== ts2
.tv_nsec
&& ts1
.tv_sec
== ts2
.tv_sec
);
158 freq
= ctrl_inw(MTU2_TCNT_0
);
159 if (ts2
.tv_nsec
< ts1
.tv_nsec
) {
160 ts2
.tv_nsec
+= 1000000000;
164 diff_nsec
= (ts2
.tv_sec
- ts1
.tv_sec
) * 1000000000 + (ts2
.tv_nsec
- ts1
.tv_nsec
);
166 /* this should work well if the RTC has a precision of n Hz, where
167 * n is an integer. I don't think we have to worry about the other
169 factor
= (1000000000 + diff_nsec
/2) / diff_nsec
;
171 if (factor
* diff_nsec
> 1100000000 ||
172 factor
* diff_nsec
< 900000000)
173 panic("weird RTC (diff_nsec %ld)", diff_nsec
);
175 return freq
* factor
;
178 static unsigned int divisors
[] = { 1, 4, 16, 64, 1, 1, 256 };
180 static void mtu2_clk_init(struct clk
*clk
)
182 u8 idx
= MTU2_TCR_INIT
& 0x7;
184 clk
->rate
= clk
->parent
->rate
/ divisors
[idx
];
185 /* Start TCNT counting */
186 ctrl_outb(ctrl_inb(MTU2_TSTR
) | MTU2_TSTR_CST1
, MTU2_TSTR
);
190 static void mtu2_clk_recalc(struct clk
*clk
)
192 u8 idx
= ctrl_inb(MTU2_TCR_1
) & 0x7;
193 clk
->rate
= clk
->parent
->rate
/ divisors
[idx
];
196 static struct clk_ops mtu2_clk_ops
= {
197 .init
= mtu2_clk_init
,
198 .recalc
= mtu2_clk_recalc
,
201 static struct clk mtu2_clk1
= {
203 .ops
= &mtu2_clk_ops
,
206 static int mtu2_timer_start(void)
208 ctrl_outb(ctrl_inb(MTU2_TSTR
) | MTU2_TSTR_CST1
, MTU2_TSTR
);
212 static int mtu2_timer_stop(void)
214 ctrl_outb(ctrl_inb(MTU2_TSTR
) & ~MTU2_TSTR_CST1
, MTU2_TSTR
);
218 static int mtu2_timer_init(void)
221 unsigned long interval
;
223 setup_irq(TIMER_IRQ
, &mtu2_irq
);
225 mtu2_clk1
.parent
= clk_get("module_clk");
227 ctrl_outb(ctrl_inb(STBCR3
) & (~0x20), STBCR3
);
229 /* Normal operation */
230 ctrl_outb(0, MTU2_TMDR_1
);
231 ctrl_outb(MTU2_TCR_INIT
, MTU2_TCR_1
);
232 ctrl_outb(0x01, MTU2_TIOR_1
);
234 /* Enable underflow interrupt */
235 ctrl_outb(ctrl_inb(MTU2_TIER_1
) | MTU2_TIER_TGIEA
, MTU2_TIER_1
);
237 interval
= CONFIG_SH_PCLK_FREQ
/ 16 / HZ
;
238 printk(KERN_INFO
"Interval = %ld\n", interval
);
240 ctrl_outw(interval
, MTU2_TGRA_1
);
241 ctrl_outw(0, MTU2_TCNT_1
);
243 clk_register(&mtu2_clk1
);
244 clk_enable(&mtu2_clk1
);
249 struct sys_timer_ops mtu2_timer_ops
= {
250 .init
= mtu2_timer_init
,
251 .start
= mtu2_timer_start
,
252 .stop
= mtu2_timer_stop
,
253 .get_frequency
= mtu2_timer_get_frequency
,
254 .get_offset
= mtu2_timer_get_offset
,
257 struct sys_timer mtu2_timer
= {
259 .ops
= &mtu2_timer_ops
,