arch/sh/kernel/timers/timer-tmu.c

   1 /*
   2  * arch/sh/kernel/timers/timer-tmu.c - TMU Timer Support
   3  *
   4  *  Copyright (C) 2005 - 2007  Paul Mundt
   5  *
   6  * TMU handling code hacked out of arch/sh/kernel/time.c
   7  *
   8  *  Copyright (C) 1999  Tetsuya Okada & Niibe Yutaka
   9  *  Copyright (C) 2000  Philipp Rumpf <prumpf@tux.org>
  10  *  Copyright (C) 2002, 2003, 2004  Paul Mundt
  11  *  Copyright (C) 2002  M. R. Brown  <mrbrown@linux-sh.org>
  12  *
  13  * This file is subject to the terms and conditions of the GNU General Public
  14  * License.  See the file "COPYING" in the main directory of this archive
  15  * for more details.
  16  */
  17 #include <linux/init.h>
  18 #include <linux/kernel.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/seqlock.h>
  21 #include <linux/clockchips.h>
  22 #include <asm/timer.h>
  23 #include <asm/rtc.h>
  24 #include <asm/io.h>
  25 #include <asm/irq.h>
  26 #include <asm/clock.h>
  27
  28 #define TMU_TOCR_INIT   0x00
  29 #define TMU_TCR_INIT    0x0020
  30
  31 #define TMU0            (0)
  32 #define TMU1            (1)
  33
  34 static inline void _tmu_start(int tmu_num)
  35 {
  36         ctrl_outb(ctrl_inb(TMU_012_TSTR) | (0x1<<tmu_num), TMU_012_TSTR);
  37 }
  38
  39 static inline void _tmu_set_irq(int tmu_num, int enabled)
  40 {
  41         register unsigned long tmu_tcr = TMU0_TCR + (0xc*tmu_num);
  42         ctrl_outw( (enabled ? ctrl_inw(tmu_tcr) | (1<<5) : ctrl_inw(tmu_tcr) & ~(1<<5)), tmu_tcr);
  43 }
  44
  45 static inline void _tmu_stop(int tmu_num)
  46 {
  47         ctrl_outb(ctrl_inb(TMU_012_TSTR) & ~(0x1<<tmu_num), TMU_012_TSTR);
  48 }
  49
  50 static inline void _tmu_clear_status(int tmu_num)
  51 {
  52         register unsigned long tmu_tcr = TMU0_TCR + (0xc*tmu_num);
  53         /* Clear UNF bit */
  54         ctrl_outw(ctrl_inw(tmu_tcr) & ~0x100, tmu_tcr);
  55 }
  56
  57 static inline unsigned long _tmu_read(int tmu_num)
  58 {
  59         return ctrl_inl(TMU0_TCNT+0xC*tmu_num);
  60 }
  61
  62 static int tmu_timer_start(void)
  63 {
  64         _tmu_start(TMU0);
  65         _tmu_start(TMU1);
  66         _tmu_set_irq(TMU0,1);
  67         return 0;
  68 }
  69
  70 static int tmu_timer_stop(void)
  71 {
  72         _tmu_stop(TMU0);
  73         _tmu_stop(TMU1);
  74         _tmu_clear_status(TMU0);
  75         return 0;
  76 }
  77
  78 /*
  79  * also when the module_clk is scaled the TMU1
  80  * will show the same frequency
  81  */
  82 static int tmus_are_scaled;
  83
  84 static cycle_t tmu_timer_read(void)
  85 {
  86         return ((cycle_t)(~_tmu_read(TMU1)))<<tmus_are_scaled;
  87 }
  88
  89
  90 static unsigned long tmu_latest_interval[3];
  91 static void tmu_timer_set_interval(int tmu_num, unsigned long interval, unsigned int reload)
  92 {
  93         unsigned long tmu_tcnt = TMU0_TCNT + tmu_num*0xC;
  94         unsigned long tmu_tcor = TMU0_TCOR + tmu_num*0xC;
  95
  96         _tmu_stop(tmu_num);
  97
  98         ctrl_outl(interval, tmu_tcnt);
  99         tmu_latest_interval[tmu_num] = interval;
 100
 101         /*
 102          * TCNT reloads from TCOR on underflow, clear it if we don't
 103          * intend to auto-reload
 104          */
 105         ctrl_outl( reload ? interval : 0 , tmu_tcor);
 106
 107         _tmu_start(tmu_num);
 108 }
 109
 110 static int tmu_set_next_event(unsigned long cycles,
 111                               struct clock_event_device *evt)
 112 {
 113         tmu_timer_set_interval(TMU0,cycles, evt->mode == CLOCK_EVT_MODE_PERIODIC);
 114         _tmu_set_irq(TMU0,1);
 115         return 0;
 116 }
 117
 118 static void tmu_set_mode(enum clock_event_mode mode,
 119                          struct clock_event_device *evt)
 120 {
 121         switch (mode) {
 122         case CLOCK_EVT_MODE_PERIODIC:
 123                 ctrl_outl(tmu_latest_interval[TMU0], TMU0_TCOR);
 124                 break;
 125         case CLOCK_EVT_MODE_ONESHOT:
 126                 ctrl_outl(0, TMU0_TCOR);
 127                 break;
 128         case CLOCK_EVT_MODE_UNUSED:
 129         case CLOCK_EVT_MODE_SHUTDOWN:
 130         case CLOCK_EVT_MODE_RESUME:
 131                 break;
 132         }
 133 }
 134
 135 static struct clock_event_device tmu0_clockevent = {
 136         .name           = "tmu0",
 137         .shift          = 32,
 138         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 139         .set_mode       = tmu_set_mode,
 140         .set_next_event = tmu_set_next_event,
 141 };
 142
 143 static irqreturn_t tmu_timer_interrupt(int irq, void *dummy)
 144 {
 145         struct clock_event_device *evt = &tmu0_clockevent;
 146         _tmu_clear_status(TMU0);
 147         _tmu_set_irq(TMU0,tmu0_clockevent.mode != CLOCK_EVT_MODE_ONESHOT);
 148
 149         switch (tmu0_clockevent.mode) {
 150         case CLOCK_EVT_MODE_ONESHOT:
 151         case CLOCK_EVT_MODE_PERIODIC:
 152                 evt->event_handler(evt);
 153                 break;
 154         default:
 155                 break;
 156         }
 157
 158         return IRQ_HANDLED;
 159 }
 160
 161 static struct irqaction tmu0_irq = {
 162         .name           = "periodic/oneshot timer",
 163         .handler        = tmu_timer_interrupt,
 164         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 165 };
 166
 167 static void __init tmu_clk_init(struct clk *clk)
 168 {
 169         u8 divisor  = TMU_TCR_INIT & 0x7;
 170         int tmu_num = clk->name[3]-'0';
 171         ctrl_outw(TMU_TCR_INIT, TMU0_TCR+(tmu_num*0xC));
 172         clk->rate = clk_get_rate(clk->parent) / (4 << (divisor << 1));
 173 }
 174
 175 static void tmu_clk_recalc(struct clk *clk)
 176 {
 177         int tmu_num = clk->name[3]-'0';
 178         unsigned long prev_rate = clk_get_rate(clk);
 179         unsigned long flags;
 180         u8 divisor = ctrl_inw(TMU0_TCR+tmu_num*0xC) & 0x7;
 181         clk->rate  = clk_get_rate(clk->parent) / (4 << (divisor << 1));
 182
 183         if(prev_rate==clk_get_rate(clk))
 184                 return;
 185
 186         if(tmu_num)
 187                 return; /* No more work on TMU1 */
 188
 189         local_irq_save(flags);
 190         tmus_are_scaled = (prev_rate > clk->rate);
 191
 192         _tmu_stop(TMU0);
 193
 194         tmu0_clockevent.mult = div_sc(clk->rate, NSEC_PER_SEC,
 195                                 tmu0_clockevent.shift);
 196         tmu0_clockevent.max_delta_ns =
 197                         clockevent_delta2ns(-1, &tmu0_clockevent);
 198         tmu0_clockevent.min_delta_ns =
 199                         clockevent_delta2ns(1, &tmu0_clockevent);
 200
 201         if (tmus_are_scaled)
 202                 tmu_latest_interval[TMU0] >>= 1;
 203         else
 204                 tmu_latest_interval[TMU0] <<= 1;
 205
 206         tmu_timer_set_interval(TMU0,
 207                 tmu_latest_interval[TMU0],
 208                 tmu0_clockevent.mode == CLOCK_EVT_MODE_PERIODIC);
 209
 210         _tmu_start(TMU0);
 211
 212         local_irq_restore(flags);
 213 }
 214
 215 static struct clk_ops tmu_clk_ops = {
 216         .init           = tmu_clk_init,
 217         .recalc         = tmu_clk_recalc,
 218 };
 219
 220 static struct clk tmu0_clk = {
 221         .name           = "tmu0_clk",
 222         .ops            = &tmu_clk_ops,
 223 };
 224
 225 static struct clk tmu1_clk = {
 226         .name           = "tmu1_clk",
 227         .ops            = &tmu_clk_ops,
 228 };
 229
 230 static int tmu_timer_init(void)
 231 {
 232         unsigned long interval;
 233         unsigned long frequency;
 234
 235         setup_irq(CONFIG_SH_TIMER_IRQ, &tmu0_irq);
 236
 237         tmu0_clk.parent = clk_get(NULL, "module_clk");
 238         tmu1_clk.parent = clk_get(NULL, "module_clk");
 239
 240         tmu_timer_stop();
 241
 242 #if !defined(CONFIG_CPU_SUBTYPE_SH7720) && \
 243     !defined(CONFIG_CPU_SUBTYPE_SH7721) && \
 244     !defined(CONFIG_CPU_SUBTYPE_SH7760) && \
 245     !defined(CONFIG_CPU_SUBTYPE_SH7785) && \
 246     !defined(CONFIG_CPU_SUBTYPE_SH7786) && \
 247     !defined(CONFIG_CPU_SUBTYPE_SHX3)
 248         ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
 249 #endif
 250
 251         clk_register(&tmu0_clk);
 252         clk_register(&tmu1_clk);
 253         clk_enable(&tmu0_clk);
 254         clk_enable(&tmu1_clk);
 255
 256         frequency = clk_get_rate(&tmu0_clk);
 257         interval = (frequency + HZ / 2) / HZ;
 258
 259         tmu_timer_set_interval(TMU0,interval, 1);
 260         tmu_timer_set_interval(TMU1,~0,1);
 261
 262         _tmu_start(TMU1);
 263
 264         clocksource_sh.rating = 200;
 265         clocksource_sh.mask = CLOCKSOURCE_MASK(32);
 266         clocksource_sh.read = tmu_timer_read;
 267         clocksource_sh.shift = 10;
 268         clocksource_sh.mult = clocksource_hz2mult(clk_get_rate(&tmu1_clk),
 269                                                   clocksource_sh.shift);
 270         clocksource_sh.flags = CLOCK_SOURCE_IS_CONTINUOUS;
 271         clocksource_register(&clocksource_sh);
 272
 273         tmu0_clockevent.mult = div_sc(frequency, NSEC_PER_SEC,
 274                                       tmu0_clockevent.shift);
 275         tmu0_clockevent.max_delta_ns =
 276                         clockevent_delta2ns(-1, &tmu0_clockevent);
 277         tmu0_clockevent.min_delta_ns =
 278                         clockevent_delta2ns(1, &tmu0_clockevent);
 279
 280         tmu0_clockevent.cpumask = cpumask_of(0);
 281         tmu0_clockevent.rating = 100;
 282
 283         clockevents_register_device(&tmu0_clockevent);
 284
 285         return 0;
 286 }
 287
 288 static struct sys_timer_ops tmu_timer_ops = {
 289         .init           = tmu_timer_init,
 290         .start          = tmu_timer_start,
 291         .stop           = tmu_timer_stop,
 292 };
 293
 294 struct sys_timer tmu_timer = {
 295         .name   = "tmu",
 296         .ops    = &tmu_timer_ops,
 297 };