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git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blob - arch/sh/mm/cache-sh4.c
2 * arch/sh/mm/cache-sh4.c
4 * Copyright (C) 1999, 2000, 2002 Niibe Yutaka
5 * Copyright (C) 2001 - 2009 Paul Mundt
6 * Copyright (C) 2003 Richard Curnow
7 * Copyright (c) 2007 STMicroelectronics (R&D) Ltd.
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file "COPYING" in the main directory of this archive
13 #include <linux/init.h>
16 #include <linux/mutex.h>
18 #include <linux/highmem.h>
19 #include <asm/mmu_context.h>
20 #include <asm/cache_insns.h>
21 #include <asm/cacheflush.h>
24 * The maximum number of pages we support up to when doing ranged dcache
25 * flushing. Anything exceeding this will simply flush the dcache in its
28 #define MAX_ICACHE_PAGES 32
30 static void __flush_cache_one(unsigned long addr
, unsigned long phys
,
31 unsigned long exec_offset
);
34 * Write back the range of D-cache, and purge the I-cache.
36 * Called from kernel/module.c:sys_init_module and routine for a.out format,
37 * signal handler code and kprobes code
39 static void sh4_flush_icache_range(void *args
)
41 struct flusher_data
*data
= args
;
42 unsigned long start
, end
;
43 unsigned long flags
, v
;
49 /* If there are too many pages then just blow away the caches */
50 if (((end
- start
) >> PAGE_SHIFT
) >= MAX_ICACHE_PAGES
) {
51 local_flush_cache_all(NULL
);
56 * Selectively flush d-cache then invalidate the i-cache.
57 * This is inefficient, so only use this for small ranges.
59 start
&= ~(L1_CACHE_BYTES
-1);
60 end
+= L1_CACHE_BYTES
-1;
61 end
&= ~(L1_CACHE_BYTES
-1);
63 local_irq_save(flags
);
66 for (v
= start
; v
< end
; v
+= L1_CACHE_BYTES
) {
67 unsigned long icacheaddr
;
72 icacheaddr
= CACHE_IC_ADDRESS_ARRAY
| (v
&
73 cpu_data
->icache
.entry_mask
);
75 /* Clear i-cache line valid-bit */
76 n
= boot_cpu_data
.icache
.n_aliases
;
77 for (i
= 0; i
< cpu_data
->icache
.ways
; i
++) {
78 for (j
= 0; j
< n
; j
++)
79 __raw_writel(0, icacheaddr
+ (j
* PAGE_SIZE
));
80 icacheaddr
+= cpu_data
->icache
.way_incr
;
85 local_irq_restore(flags
);
88 static inline void flush_cache_one(unsigned long start
, unsigned long phys
)
90 unsigned long flags
, exec_offset
= 0;
93 * All types of SH-4 require PC to be uncached to operate on the I-cache.
94 * Some types of SH-4 require PC to be uncached to operate on the D-cache.
96 if ((boot_cpu_data
.flags
& CPU_HAS_P2_FLUSH_BUG
) ||
97 (start
< CACHE_OC_ADDRESS_ARRAY
))
98 exec_offset
= cached_to_uncached
;
100 local_irq_save(flags
);
101 __flush_cache_one(start
, phys
, exec_offset
);
102 local_irq_restore(flags
);
106 * Write back & invalidate the D-cache of the page.
107 * (To avoid "alias" issues)
109 static void sh4_flush_dcache_page(void *arg
)
111 struct page
*page
= arg
;
112 unsigned long addr
= (unsigned long)page_address(page
);
114 struct address_space
*mapping
= page_mapping_file(page
);
116 if (mapping
&& !mapping_mapped(mapping
))
117 clear_bit(PG_dcache_clean
, &page
->flags
);
120 flush_cache_one(CACHE_OC_ADDRESS_ARRAY
|
121 (addr
& shm_align_mask
), page_to_phys(page
));
126 /* TODO: Selective icache invalidation through IC address array.. */
127 static void flush_icache_all(void)
129 unsigned long flags
, ccr
;
131 local_irq_save(flags
);
135 ccr
= __raw_readl(SH_CCR
);
136 ccr
|= CCR_CACHE_ICI
;
137 __raw_writel(ccr
, SH_CCR
);
140 * back_to_cached() will take care of the barrier for us, don't add
145 local_irq_restore(flags
);
148 static void flush_dcache_all(void)
150 unsigned long addr
, end_addr
, entry_offset
;
152 end_addr
= CACHE_OC_ADDRESS_ARRAY
+
153 (current_cpu_data
.dcache
.sets
<<
154 current_cpu_data
.dcache
.entry_shift
) *
155 current_cpu_data
.dcache
.ways
;
157 entry_offset
= 1 << current_cpu_data
.dcache
.entry_shift
;
159 for (addr
= CACHE_OC_ADDRESS_ARRAY
; addr
< end_addr
; ) {
160 __raw_writel(0, addr
); addr
+= entry_offset
;
161 __raw_writel(0, addr
); addr
+= entry_offset
;
162 __raw_writel(0, addr
); addr
+= entry_offset
;
163 __raw_writel(0, addr
); addr
+= entry_offset
;
164 __raw_writel(0, addr
); addr
+= entry_offset
;
165 __raw_writel(0, addr
); addr
+= entry_offset
;
166 __raw_writel(0, addr
); addr
+= entry_offset
;
167 __raw_writel(0, addr
); addr
+= entry_offset
;
171 static void sh4_flush_cache_all(void *unused
)
178 * Note : (RPC) since the caches are physically tagged, the only point
179 * of flush_cache_mm for SH-4 is to get rid of aliases from the
180 * D-cache. The assumption elsewhere, e.g. flush_cache_range, is that
181 * lines can stay resident so long as the virtual address they were
182 * accessed with (hence cache set) is in accord with the physical
183 * address (i.e. tag). It's no different here.
185 * Caller takes mm->mmap_sem.
187 static void sh4_flush_cache_mm(void *arg
)
189 struct mm_struct
*mm
= arg
;
191 if (cpu_context(smp_processor_id(), mm
) == NO_CONTEXT
)
198 * Write back and invalidate I/D-caches for the page.
200 * ADDR: Virtual Address (U0 address)
201 * PFN: Physical page number
203 static void sh4_flush_cache_page(void *args
)
205 struct flusher_data
*data
= args
;
206 struct vm_area_struct
*vma
;
208 unsigned long address
, pfn
, phys
;
209 int map_coherent
= 0;
218 address
= data
->addr1
& PAGE_MASK
;
220 phys
= pfn
<< PAGE_SHIFT
;
221 page
= pfn_to_page(pfn
);
223 if (cpu_context(smp_processor_id(), vma
->vm_mm
) == NO_CONTEXT
)
226 pgd
= pgd_offset(vma
->vm_mm
, address
);
227 p4d
= p4d_offset(pgd
, address
);
228 pud
= pud_offset(p4d
, address
);
229 pmd
= pmd_offset(pud
, address
);
230 pte
= pte_offset_kernel(pmd
, address
);
232 /* If the page isn't present, there is nothing to do here. */
233 if (!(pte_val(*pte
) & _PAGE_PRESENT
))
236 if ((vma
->vm_mm
== current
->active_mm
))
240 * Use kmap_coherent or kmap_atomic to do flushes for
241 * another ASID than the current one.
243 map_coherent
= (current_cpu_data
.dcache
.n_aliases
&&
244 test_bit(PG_dcache_clean
, &page
->flags
) &&
245 page_mapcount(page
));
247 vaddr
= kmap_coherent(page
, address
);
249 vaddr
= kmap_atomic(page
);
251 address
= (unsigned long)vaddr
;
254 flush_cache_one(CACHE_OC_ADDRESS_ARRAY
|
255 (address
& shm_align_mask
), phys
);
257 if (vma
->vm_flags
& VM_EXEC
)
262 kunmap_coherent(vaddr
);
264 kunmap_atomic(vaddr
);
269 * Write back and invalidate D-caches.
271 * START, END: Virtual Address (U0 address)
273 * NOTE: We need to flush the _physical_ page entry.
274 * Flushing the cache lines for U0 only isn't enough.
275 * We need to flush for P1 too, which may contain aliases.
277 static void sh4_flush_cache_range(void *args
)
279 struct flusher_data
*data
= args
;
280 struct vm_area_struct
*vma
;
281 unsigned long start
, end
;
287 if (cpu_context(smp_processor_id(), vma
->vm_mm
) == NO_CONTEXT
)
291 * If cache is only 4k-per-way, there are never any 'aliases'. Since
292 * the cache is physically tagged, the data can just be left in there.
294 if (boot_cpu_data
.dcache
.n_aliases
== 0)
299 if (vma
->vm_flags
& VM_EXEC
)
306 * @addr: address in memory mapped cache array
307 * @phys: P1 address to flush (has to match tags if addr has 'A' bit
308 * set i.e. associative write)
309 * @exec_offset: set to 0x20000000 if flush has to be executed from P2
312 * The offset into the cache array implied by 'addr' selects the
313 * 'colour' of the virtual address range that will be flushed. The
314 * operation (purge/write-back) is selected by the lower 2 bits of
317 static void __flush_cache_one(unsigned long addr
, unsigned long phys
,
318 unsigned long exec_offset
)
321 unsigned long base_addr
= addr
;
322 struct cache_info
*dcache
;
323 unsigned long way_incr
;
324 unsigned long a
, ea
, p
;
325 unsigned long temp_pc
;
327 dcache
= &boot_cpu_data
.dcache
;
328 /* Write this way for better assembly. */
329 way_count
= dcache
->ways
;
330 way_incr
= dcache
->way_incr
;
333 * Apply exec_offset (i.e. branch to P2 if required.).
337 * If I write "=r" for the (temp_pc), it puts this in r6 hence
338 * trashing exec_offset before it's been added on - why? Hence
339 * "=&r" as a 'workaround'
341 asm volatile("mov.l 1f, %0\n\t"
347 "2:\n" : "=&r" (temp_pc
) : "r" (exec_offset
));
350 * We know there will be >=1 iteration, so write as do-while to avoid
351 * pointless nead-of-loop check for 0 iterations.
354 ea
= base_addr
+ PAGE_SIZE
;
359 *(volatile unsigned long *)a
= p
;
361 * Next line: intentionally not p+32, saves an add, p
362 * will do since only the cache tag bits need to
365 *(volatile unsigned long *)(a
+32) = p
;
370 base_addr
+= way_incr
;
371 } while (--way_count
!= 0);
374 extern void __weak
sh4__flush_region_init(void);
377 * SH-4 has virtually indexed and physically tagged cache.
379 void __init
sh4_cache_init(void)
381 printk("PVR=%08x CVR=%08x PRR=%08x\n",
382 __raw_readl(CCN_PVR
),
383 __raw_readl(CCN_CVR
),
384 __raw_readl(CCN_PRR
));
386 local_flush_icache_range
= sh4_flush_icache_range
;
387 local_flush_dcache_page
= sh4_flush_dcache_page
;
388 local_flush_cache_all
= sh4_flush_cache_all
;
389 local_flush_cache_mm
= sh4_flush_cache_mm
;
390 local_flush_cache_dup_mm
= sh4_flush_cache_mm
;
391 local_flush_cache_page
= sh4_flush_cache_page
;
392 local_flush_cache_range
= sh4_flush_cache_range
;
394 sh4__flush_region_init();