arch/sh/mm/pg-sh7705.c

   1 /*
   2  * arch/sh/mm/pg-sh7705.c
   3  *
   4  * Copyright (C) 1999, 2000  Niibe Yutaka
   5  * Copyright (C) 2004  Alex Song
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file "COPYING" in the main directory of this archive
   9  * for more details.
  10  *
  11  */
  12
  13 #include <linux/init.h>
  14 #include <linux/mman.h>
  15 #include <linux/mm.h>
  16 #include <linux/threads.h>
  17 #include <linux/fs.h>
  18 #include <asm/addrspace.h>
  19 #include <asm/page.h>
  20 #include <asm/pgtable.h>
  21 #include <asm/processor.h>
  22 #include <asm/cache.h>
  23 #include <asm/io.h>
  24 #include <asm/uaccess.h>
  25 #include <asm/pgalloc.h>
  26 #include <asm/mmu_context.h>
  27 #include <asm/cacheflush.h>
  28
  29 static void __flush_purge_virtual_region(void *p1, void *virt, int size)
  30 {
  31         unsigned long v;
  32         unsigned long begin, end;
  33         unsigned long p1_begin;
  34
  35
  36         begin = L1_CACHE_ALIGN((unsigned long)virt);
  37         end = L1_CACHE_ALIGN((unsigned long)virt + size);
  38
  39         p1_begin = (unsigned long)p1 & ~(L1_CACHE_BYTES - 1);
  40
  41         /* do this the slow way as we may not have TLB entries
  42          * for virt yet. */
  43         for (v = begin; v < end; v += L1_CACHE_BYTES) {
  44                 unsigned long p;
  45                 unsigned long ways, addr;
  46
  47                 p = __pa(p1_begin);
  48
  49                 ways = current_cpu_data.dcache.ways;
  50                 addr = CACHE_OC_ADDRESS_ARRAY;
  51
  52                 do {
  53                         unsigned long data;
  54
  55                         addr |= (v & current_cpu_data.dcache.entry_mask);
  56
  57                         data = ctrl_inl(addr);
  58                         if ((data & CACHE_PHYSADDR_MASK) ==
  59                                (p & CACHE_PHYSADDR_MASK)) {
  60                                 data &= ~(SH_CACHE_UPDATED|SH_CACHE_VALID);
  61                                 ctrl_outl(data, addr);
  62                         }
  63
  64                         addr += current_cpu_data.dcache.way_incr;
  65                 } while (--ways);
  66
  67                 p1_begin += L1_CACHE_BYTES;
  68         }
  69 }
  70
  71 /*
  72  * clear_user_page
  73  * @to: P1 address
  74  * @address: U0 address to be mapped
  75  */
  76 void clear_user_page(void *to, unsigned long address, struct page *pg)
  77 {
  78         if (pages_do_alias(address, (unsigned long)to))
  79                 __flush_purge_virtual_region(to,
  80                                              (void *)(address & 0xfffff000),
  81                                              PAGE_SIZE);
  82
  83         clear_page(to);
  84         __flush_wback_region(to, PAGE_SIZE);
  85 }
  86
  87 /*
  88  * copy_user_page
  89  * @to: P1 address
  90  * @from: P1 address
  91  * @address: U0 address to be mapped
  92  */
  93 void copy_user_page(void *to, void *from, unsigned long address, struct page *pg)
  94 {
  95         if (pages_do_alias(address, (unsigned long)to))
  96                 __flush_purge_virtual_region(to,
  97                                              (void *)(address & 0xfffff000),
  98                                              PAGE_SIZE);
  99
 100         copy_page(to, from);
 101         __flush_wback_region(to, PAGE_SIZE);
 102 }