1 /* head.S: Initial boot code for the Sparc64 port of Linux.
3 * Copyright (C) 1996, 1997, 2007 David S. Miller (davem@davemloft.net)
4 * Copyright (C) 1996 David Sitsky (David.Sitsky@anu.edu.au)
5 * Copyright (C) 1997, 1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
6 * Copyright (C) 1997 Miguel de Icaza (miguel@nuclecu.unam.mx)
9 #include <linux/version.h>
10 #include <linux/errno.h>
11 #include <linux/threads.h>
12 #include <linux/init.h>
13 #include <linux/linkage.h>
14 #include <asm/thread_info.h>
16 #include <asm/pstate.h>
17 #include <asm/ptrace.h>
18 #include <asm/spitfire.h>
20 #include <asm/pgtable.h>
21 #include <asm/errno.h>
22 #include <asm/signal.h>
23 #include <asm/processor.h>
28 #include <asm/ttable.h>
30 #include <asm/cpudata.h>
32 #include <asm/estate.h>
33 #include <asm/sfafsr.h>
34 #include <asm/unistd.h>
35 #include <asm/export.h>
37 /* This section from from _start to sparc64_boot_end should fit into
38 * 0x0000000000404000 to 0x0000000000408000.
41 .globl start, _start, stext, _stext
48 flushw /* Flush register file. */
50 /* This stuff has to be in sync with SILO and other potential boot loaders
51 * Fields should be kept upward compatible and whenever any change is made,
52 * HdrS version should be incremented.
54 .global root_flags, ram_flags, root_dev
55 .global sparc_ramdisk_image, sparc_ramdisk_size
56 .global sparc_ramdisk_image64
59 .word LINUX_VERSION_CODE
63 * 0x0300 : Supports being located at other than 0x4000
64 * 0x0202 : Supports kernel params string
65 * 0x0201 : Supports reboot_command
67 .half 0x0301 /* HdrS version */
81 sparc_ramdisk_image64:
85 /* PROM cif handler code address is in %o4. */
89 /* We need to remap the kernel. Use position independent
90 * code to remap us to KERNBASE.
92 * SILO can invoke us with 32-bit address masking enabled,
93 * so make sure that's clear.
96 andn %g1, PSTATE_AM, %g1
97 wrpr %g1, 0x0, %pstate
101 .globl prom_finddev_name, prom_chosen_path, prom_root_node
102 .globl prom_getprop_name, prom_mmu_name, prom_peer_name
103 .globl prom_callmethod_name, prom_translate_name, prom_root_compatible
104 .globl prom_map_name, prom_unmap_name, prom_mmu_ihandle_cache
105 .globl prom_boot_mapped_pc, prom_boot_mapping_mode
106 .globl prom_boot_mapping_phys_high, prom_boot_mapping_phys_low
107 .globl prom_compatible_name, prom_cpu_path, prom_cpu_compatible
108 .globl is_sun4v, sun4v_chip_type, prom_set_trap_table_name
111 prom_compatible_name:
123 prom_callmethod_name:
131 prom_set_trap_table_name:
132 .asciz "SUNW,set-trap-table"
136 .asciz "SUNW,UltraSPARC-T"
139 prom_sparc64x_prefix:
142 prom_root_compatible:
148 EXPORT_SYMBOL(prom_root_node)
149 prom_mmu_ihandle_cache:
153 prom_boot_mapping_mode:
156 prom_boot_mapping_phys_high:
158 prom_boot_mapping_phys_low:
163 .word SUN4V_CHIP_INVALID
164 EXPORT_SYMBOL(sun4v_chip_type)
168 mov (1b - prom_peer_name), %l1
172 /* prom_root_node = prom_peer(0) */
173 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "peer"
175 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
176 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
177 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, 0
178 stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
180 add %sp, (2047 + 128), %o0 ! argument array
182 ldx [%sp + 2047 + 128 + 0x20], %l4 ! prom root node
183 mov (1b - prom_root_node), %l1
187 mov (1b - prom_getprop_name), %l1
188 mov (1b - prom_compatible_name), %l2
189 mov (1b - prom_root_compatible), %l5
194 /* prom_getproperty(prom_root_node, "compatible",
195 * &prom_root_compatible, 64)
197 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
199 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
201 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
202 stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, prom_root_node
203 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "compatible"
204 stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_root_compatible
206 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size
207 stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
209 add %sp, (2047 + 128), %o0 ! argument array
211 mov (1b - prom_finddev_name), %l1
212 mov (1b - prom_chosen_path), %l2
213 mov (1b - prom_boot_mapped_pc), %l3
218 sub %sp, (192 + 128), %sp
220 /* chosen_node = prom_finddevice("/chosen") */
221 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
223 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
224 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
225 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/chosen"
226 stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
228 add %sp, (2047 + 128), %o0 ! argument array
230 ldx [%sp + 2047 + 128 + 0x20], %l4 ! chosen device node
232 mov (1b - prom_getprop_name), %l1
233 mov (1b - prom_mmu_name), %l2
234 mov (1b - prom_mmu_ihandle_cache), %l5
239 /* prom_mmu_ihandle_cache = prom_getint(chosen_node, "mmu") */
240 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
242 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
244 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
245 stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, chosen_node
246 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "mmu"
247 stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_mmu_ihandle_cache
249 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, sizeof(arg3)
250 stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
252 add %sp, (2047 + 128), %o0 ! argument array
254 mov (1b - prom_callmethod_name), %l1
255 mov (1b - prom_translate_name), %l2
258 lduw [%l5], %l5 ! prom_mmu_ihandle_cache
260 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "call-method"
262 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 3
264 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 5
265 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1: "translate"
266 stx %l5, [%sp + 2047 + 128 + 0x20] ! arg2: prom_mmu_ihandle_cache
270 stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: vaddr, our PC
271 stx %g0, [%sp + 2047 + 128 + 0x30] ! res1
272 stx %g0, [%sp + 2047 + 128 + 0x38] ! res2
273 stx %g0, [%sp + 2047 + 128 + 0x40] ! res3
274 stx %g0, [%sp + 2047 + 128 + 0x48] ! res4
275 stx %g0, [%sp + 2047 + 128 + 0x50] ! res5
277 add %sp, (2047 + 128), %o0 ! argument array
279 ldx [%sp + 2047 + 128 + 0x40], %l1 ! translation mode
280 mov (1b - prom_boot_mapping_mode), %l4
283 mov (1b - prom_boot_mapping_phys_high), %l4
285 ldx [%sp + 2047 + 128 + 0x48], %l2 ! physaddr high
287 ldx [%sp + 2047 + 128 + 0x50], %l3 ! physaddr low
289 srlx %l3, ILOG2_4MB, %l3
290 sllx %l3, ILOG2_4MB, %l3
293 /* Leave service as-is, "call-method" */
295 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 7
297 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
298 mov (1b - prom_map_name), %l3
300 stx %l3, [%sp + 2047 + 128 + 0x18] ! arg1: "map"
301 /* Leave arg2 as-is, prom_mmu_ihandle_cache */
303 stx %l3, [%sp + 2047 + 128 + 0x28] ! arg3: mode (-1 default)
304 /* 4MB align the kernel image size. */
305 set (_end - KERNBASE), %l3
306 set ((4 * 1024 * 1024) - 1), %l4
309 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4: roundup(ksize, 4MB)
310 sethi %hi(KERNBASE), %l3
311 stx %l3, [%sp + 2047 + 128 + 0x38] ! arg5: vaddr (KERNBASE)
312 stx %g0, [%sp + 2047 + 128 + 0x40] ! arg6: empty
313 mov (1b - prom_boot_mapping_phys_low), %l3
316 stx %l3, [%sp + 2047 + 128 + 0x48] ! arg7: phys addr
318 add %sp, (2047 + 128), %o0 ! argument array
320 add %sp, (192 + 128), %sp
322 sethi %hi(prom_root_compatible), %g1
323 or %g1, %lo(prom_root_compatible), %g1
324 sethi %hi(prom_sun4v_name), %g7
325 or %g7, %lo(prom_sun4v_name), %g7
336 sethi %hi(is_sun4v), %g1
337 or %g1, %lo(is_sun4v), %g1
341 /* cpu_node = prom_finddevice("/cpu") */
342 mov (1b - prom_finddev_name), %l1
343 mov (1b - prom_cpu_path), %l2
346 sub %sp, (192 + 128), %sp
348 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "finddevice"
350 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 1
351 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
352 stx %l2, [%sp + 2047 + 128 + 0x18] ! arg1, "/cpu"
353 stx %g0, [%sp + 2047 + 128 + 0x20] ! ret1
355 add %sp, (2047 + 128), %o0 ! argument array
357 ldx [%sp + 2047 + 128 + 0x20], %l4 ! cpu device node
359 mov (1b - prom_getprop_name), %l1
360 mov (1b - prom_compatible_name), %l2
361 mov (1b - prom_cpu_compatible), %l5
366 /* prom_getproperty(cpu_node, "compatible",
367 * &prom_cpu_compatible, 64)
369 stx %l1, [%sp + 2047 + 128 + 0x00] ! service, "getprop"
371 stx %l3, [%sp + 2047 + 128 + 0x08] ! num_args, 4
373 stx %l3, [%sp + 2047 + 128 + 0x10] ! num_rets, 1
374 stx %l4, [%sp + 2047 + 128 + 0x18] ! arg1, cpu_node
375 stx %l2, [%sp + 2047 + 128 + 0x20] ! arg2, "compatible"
376 stx %l5, [%sp + 2047 + 128 + 0x28] ! arg3, &prom_cpu_compatible
378 stx %l3, [%sp + 2047 + 128 + 0x30] ! arg4, size
379 stx %g0, [%sp + 2047 + 128 + 0x38] ! ret1
381 add %sp, (2047 + 128), %o0 ! argument array
383 add %sp, (192 + 128), %sp
385 sethi %hi(prom_cpu_compatible), %g1
386 or %g1, %lo(prom_cpu_compatible), %g1
387 sethi %hi(prom_niagara_prefix), %g7
388 or %g7, %lo(prom_niagara_prefix), %g7
401 89: sethi %hi(prom_cpu_compatible), %g1
402 or %g1, %lo(prom_cpu_compatible), %g1
403 sethi %hi(prom_sparc_prefix), %g7
404 or %g7, %lo(prom_sparc_prefix), %g7
415 sethi %hi(prom_cpu_compatible), %g1
416 or %g1, %lo(prom_cpu_compatible), %g1
426 70: ldub [%g1 + 7], %g2
427 cmp %g2, CPU_ID_NIAGARA3
429 mov SUN4V_CHIP_NIAGARA3, %g4
430 cmp %g2, CPU_ID_NIAGARA4
432 mov SUN4V_CHIP_NIAGARA4, %g4
433 cmp %g2, CPU_ID_NIAGARA5
435 mov SUN4V_CHIP_NIAGARA5, %g4
438 mov SUN4V_CHIP_SPARC_M6, %g4
441 mov SUN4V_CHIP_SPARC_M7, %g4
444 mov SUN4V_CHIP_SPARC_M8, %g4
445 cmp %g2, CPU_ID_SONOMA1
447 mov SUN4V_CHIP_SPARC_SN, %g4
451 91: sethi %hi(prom_cpu_compatible), %g1
452 or %g1, %lo(prom_cpu_compatible), %g1
454 cmp %g2, CPU_ID_NIAGARA1
456 mov SUN4V_CHIP_NIAGARA1, %g4
457 cmp %g2, CPU_ID_NIAGARA2
459 mov SUN4V_CHIP_NIAGARA2, %g4
463 sethi %hi(prom_cpu_compatible), %g1
464 or %g1, %lo(prom_cpu_compatible), %g1
465 sethi %hi(prom_sparc64x_prefix), %g7
466 or %g7, %lo(prom_sparc64x_prefix), %g7
477 mov SUN4V_CHIP_SPARC64X, %g4
480 mov SUN4V_CHIP_UNKNOWN, %g4
481 5: sethi %hi(sun4v_chip_type), %g2
482 or %g2, %lo(sun4v_chip_type), %g2
486 BRANCH_IF_SUN4V(g1, jump_to_sun4u_init)
487 BRANCH_IF_CHEETAH_BASE(g1,g7,cheetah_boot)
488 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,cheetah_plus_boot)
489 ba,pt %xcc, spitfire_boot
493 /* Preserve OBP chosen DCU and DCR register settings. */
494 ba,pt %xcc, cheetah_generic_boot
498 mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
501 sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
502 or %g7, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g7
504 or %g7, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g7
505 stxa %g7, [%g0] ASI_DCU_CONTROL_REG
508 cheetah_generic_boot:
509 mov TSB_EXTENSION_P, %g3
510 stxa %g0, [%g3] ASI_DMMU
511 stxa %g0, [%g3] ASI_IMMU
514 mov TSB_EXTENSION_S, %g3
515 stxa %g0, [%g3] ASI_DMMU
518 mov TSB_EXTENSION_N, %g3
519 stxa %g0, [%g3] ASI_DMMU
520 stxa %g0, [%g3] ASI_IMMU
523 ba,a,pt %xcc, jump_to_sun4u_init
526 /* Typically PROM has already enabled both MMU's and both on-chip
527 * caches, but we do it here anyway just to be paranoid.
529 mov (LSU_CONTROL_IC|LSU_CONTROL_DC|LSU_CONTROL_IM|LSU_CONTROL_DM), %g1
530 stxa %g1, [%g0] ASI_LSU_CONTROL
535 * Make sure we are in privileged mode, have address masking,
536 * using the ordinary globals and have enabled floating
539 * Again, typically PROM has left %pil at 13 or similar, and
540 * (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE) in %pstate.
542 wrpr %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate
551 BRANCH_IF_SUN4V(g1, sun4v_init)
554 mov PRIMARY_CONTEXT, %g7
555 stxa %g0, [%g7] ASI_DMMU
558 mov SECONDARY_CONTEXT, %g7
559 stxa %g0, [%g7] ASI_DMMU
562 ba,a,pt %xcc, sun4u_continue
566 mov PRIMARY_CONTEXT, %g7
567 stxa %g0, [%g7] ASI_MMU
570 mov SECONDARY_CONTEXT, %g7
571 stxa %g0, [%g7] ASI_MMU
573 ba,a,pt %xcc, niagara_tlb_fixup
576 BRANCH_IF_ANY_CHEETAH(g1, g7, cheetah_tlb_fixup)
578 ba,a,pt %xcc, spitfire_tlb_fixup
581 mov 3, %g2 /* Set TLB type to hypervisor. */
582 sethi %hi(tlb_type), %g1
583 stw %g2, [%g1 + %lo(tlb_type)]
585 /* Patch copy/clear ops. */
586 sethi %hi(sun4v_chip_type), %g1
587 lduw [%g1 + %lo(sun4v_chip_type)], %g1
588 cmp %g1, SUN4V_CHIP_NIAGARA1
589 be,pt %xcc, niagara_patch
590 cmp %g1, SUN4V_CHIP_NIAGARA2
591 be,pt %xcc, niagara2_patch
593 cmp %g1, SUN4V_CHIP_NIAGARA3
594 be,pt %xcc, niagara2_patch
596 cmp %g1, SUN4V_CHIP_NIAGARA4
597 be,pt %xcc, niagara4_patch
599 cmp %g1, SUN4V_CHIP_NIAGARA5
600 be,pt %xcc, niagara4_patch
602 cmp %g1, SUN4V_CHIP_SPARC_M6
603 be,pt %xcc, niagara4_patch
605 cmp %g1, SUN4V_CHIP_SPARC_M7
606 be,pt %xcc, niagara4_patch
608 cmp %g1, SUN4V_CHIP_SPARC_M8
609 be,pt %xcc, niagara4_patch
611 cmp %g1, SUN4V_CHIP_SPARC_SN
612 be,pt %xcc, niagara4_patch
615 call generic_patch_copyops
617 call generic_patch_bzero
619 call generic_patch_pageops
625 call niagara4_patch_copyops
627 call niagara4_patch_bzero
629 call niagara4_patch_pageops
636 call niagara2_patch_copyops
638 call niagara_patch_bzero
640 call niagara_patch_pageops
647 call niagara_patch_copyops
649 call niagara_patch_bzero
651 call niagara_patch_pageops
655 /* Patch TLB/cache ops. */
656 call hypervisor_patch_cachetlbops
659 ba,a,pt %xcc, tlb_fixup_done
662 mov 2, %g2 /* Set TLB type to cheetah+. */
663 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g7,1f)
665 mov 1, %g2 /* Set TLB type to cheetah. */
667 1: sethi %hi(tlb_type), %g1
668 stw %g2, [%g1 + %lo(tlb_type)]
670 /* Patch copy/page operations to cheetah optimized versions. */
671 call cheetah_patch_copyops
673 call cheetah_patch_copy_page
675 call cheetah_patch_cachetlbops
678 ba,a,pt %xcc, tlb_fixup_done
681 /* Set TLB type to spitfire. */
683 sethi %hi(tlb_type), %g1
684 stw %g2, [%g1 + %lo(tlb_type)]
687 sethi %hi(init_thread_union), %g6
688 or %g6, %lo(init_thread_union), %g6
689 ldx [%g6 + TI_TASK], %g4
693 sllx %g1, THREAD_SHIFT, %g1
694 sub %g1, (STACKFRAME_SZ + STACK_BIAS), %g1
697 /* Set per-cpu pointer initially to zero, this makes
698 * the boot-cpu use the in-kernel-image per-cpu areas
699 * before setup_per_cpu_area() is invoked.
707 sethi %hi(__bss_start), %o0
708 or %o0, %lo(__bss_start), %o0
710 or %o1, %lo(_end), %o1
715 mov %l7, %o0 ! OpenPROM cif handler
717 /* To create a one-register-window buffer between the kernel's
718 * initial stack and the last stack frame we use from the firmware,
719 * do the rest of the boot from a C helper function.
721 call start_early_boot
727 /* This is meant to allow the sharing of this code between
728 * boot processor invocation (via setup_tba() below) and
729 * secondary processor startup (via trampoline.S). The
730 * former does use this code, the latter does not yet due
731 * to some complexities. That should be fixed up at some
734 * There used to be enormous complexity wrt. transferring
735 * over from the firmware's trap table to the Linux kernel's.
736 * For example, there was a chicken & egg problem wrt. building
737 * the OBP page tables, yet needing to be on the Linux kernel
738 * trap table (to translate PAGE_OFFSET addresses) in order to
741 * We now handle OBP tlb misses differently, via linear lookups
742 * into the prom_trans[] array. So that specific problem no
743 * longer exists. Yet, unfortunately there are still some issues
744 * preventing trampoline.S from using this code... ho hum.
746 .globl setup_trap_table
750 /* Force interrupts to be disabled. */
752 andn %l0, PSTATE_IE, %o1
753 wrpr %o1, 0x0, %pstate
755 wrpr %g0, PIL_NORMAL_MAX, %pil
757 /* Make the firmware call to jump over to the Linux trap table. */
758 sethi %hi(is_sun4v), %o0
759 lduw [%o0 + %lo(is_sun4v)], %o0
763 TRAP_LOAD_TRAP_BLOCK(%g2, %g3)
764 add %g2, TRAP_PER_CPU_FAULT_INFO, %g2
765 stxa %g2, [%g0] ASI_SCRATCHPAD
767 /* Compute physical address:
769 * paddr = kern_base + (mmfsa_vaddr - KERNBASE)
771 sethi %hi(KERNBASE), %g3
773 sethi %hi(kern_base), %g3
774 ldx [%g3 + %lo(kern_base)], %g3
776 sethi %hi(sparc64_ttable_tl0), %o0
778 set prom_set_trap_table_name, %g2
779 stx %g2, [%sp + 2047 + 128 + 0x00]
781 stx %g2, [%sp + 2047 + 128 + 0x08]
783 stx %g2, [%sp + 2047 + 128 + 0x10]
784 stx %o0, [%sp + 2047 + 128 + 0x18]
785 stx %o1, [%sp + 2047 + 128 + 0x20]
786 sethi %hi(p1275buf), %g2
787 or %g2, %lo(p1275buf), %g2
788 ldx [%g2 + 0x08], %o1
790 add %sp, (2047 + 128), %o0
794 1: sethi %hi(sparc64_ttable_tl0), %o0
795 set prom_set_trap_table_name, %g2
796 stx %g2, [%sp + 2047 + 128 + 0x00]
798 stx %g2, [%sp + 2047 + 128 + 0x08]
800 stx %g2, [%sp + 2047 + 128 + 0x10]
801 stx %o0, [%sp + 2047 + 128 + 0x18]
802 sethi %hi(p1275buf), %g2
803 or %g2, %lo(p1275buf), %g2
804 ldx [%g2 + 0x08], %o1
806 add %sp, (2047 + 128), %o0
808 /* Start using proper page size encodings in ctx register. */
809 2: sethi %hi(sparc64_kern_pri_context), %g3
810 ldx [%g3 + %lo(sparc64_kern_pri_context)], %g2
812 mov PRIMARY_CONTEXT, %g1
814 661: stxa %g2, [%g1] ASI_DMMU
815 .section .sun4v_1insn_patch, "ax"
817 stxa %g2, [%g1] ASI_MMU
822 BRANCH_IF_SUN4V(o2, 1f)
824 /* Kill PROM timer */
825 sethi %hi(0x80000000), %o2
827 wr %o2, 0, %tick_cmpr
829 BRANCH_IF_ANY_CHEETAH(o2, o3, 1f)
833 /* Disable STICK_INT interrupts. */
835 sethi %hi(0x80000000), %o2
840 wrpr %g0, %g0, %wstate
842 call init_irqwork_curcpu
845 /* Now we can restore interrupt state. */
856 /* The boot processor is the only cpu which invokes this
857 * routine, the other cpus set things up via trampoline.S.
858 * So save the OBP trap table address here.
861 sethi %hi(prom_tba), %o1
862 or %o1, %lo(prom_tba), %o1
865 call setup_trap_table
872 #include "etrap_64.S"
873 #include "rtrap_64.S"
874 #include "winfixup.S"
875 #include "fpu_traps.S"
877 #include "getsetcc.S"
879 #include "spiterrs.S"
881 #include "misctrap.S"
882 #include "syscalls.S"
885 #include "sun4v_tlb_miss.S"
886 #include "sun4v_ivec.S"
891 * The following skip makes sure the trap table in ttable.S is aligned
892 * on a 32K boundary as required by the v9 specs for TBA register.
894 * We align to a 32K boundary, then we have the 32K kernel TSB,
895 * the 64K kernel 4MB TSB, and then the 32K aligned trap table.
898 .skip 0x4000 + _start - 1b
906 .globl swapper_4m_tsb
912 /* Some care needs to be exercised if you try to move the
913 * location of the trap table relative to other things. For
914 * one thing there are br* instructions in some of the
915 * trap table entires which branch back to code in ktlb.S
916 * Those instructions can only handle a signed 16-bit
919 * There is a binutils bug (bugzilla #4558) which causes
920 * the relocation overflow checks for such instructions to
921 * not be done correctly. So bintuils will not notice the
922 * error and will instead write junk into the relocation and
923 * you'll have an unbootable kernel.
925 #include "ttable_64.S"
929 #include "systbls_64.S"
933 .globl prom_tba, tlb_type
935 tlb_type: .word 0 /* Must NOT end up in BSS */
936 EXPORT_SYMBOL(tlb_type)
937 .section ".fixup",#alloc,#execinstr
942 ENDPROC(__retl_efault)
953 ENDPROC(__retl_o1_asi)